src/cpu/mips/vm/mips_64.ad

changeset 321
efc386e63b2c
parent 320
81a2795d6ebd
child 322
f3ca73f849c7
     1.1 --- a/src/cpu/mips/vm/mips_64.ad	Mon Feb 20 21:54:25 2017 +0800
     1.2 +++ b/src/cpu/mips/vm/mips_64.ad	Mon Feb 20 21:58:46 2017 +0800
     1.3 @@ -10967,13 +10967,10 @@
     1.4    ins_cost(100);
     1.5    format %{ "sarL    $dst, $src, $shift @ sarL_Reg_Reg" %}
     1.6    ins_encode %{
     1.7 -    Register creg = T9;
     1.8      Register src_reg = as_Register($src$$reg);
     1.9      Register dst_reg = as_Register($dst$$reg);
    1.10  
    1.11 -    __ move(creg, $shift$$Register);
    1.12 -    __ andi(creg, creg, 0x3f);
    1.13 -	__ dsrav(dst_reg, src_reg, creg);
    1.14 +    __ dsrav(dst_reg, src_reg, $shift$$Register);
    1.15    %}
    1.16    ins_pipe( ialu_regL_regL );
    1.17  %}
    1.18 @@ -10984,13 +10981,10 @@
    1.19    ins_cost(100);
    1.20    format %{ "slrL    $dst, $src, $shift @ slrL_Reg_Reg" %}
    1.21    ins_encode %{
    1.22 -    Register creg = T9;
    1.23      Register src_reg = as_Register($src$$reg);
    1.24      Register dst_reg = as_Register($dst$$reg);
    1.25  
    1.26 -    __ move(creg, $shift$$Register);
    1.27 -    __ andi(creg, creg, 0x3f); 
    1.28 -    __ dsrlv(dst_reg, src_reg, creg);
    1.29 +    __ dsrlv(dst_reg, src_reg, $shift$$Register);
    1.30    %}
    1.31    ins_pipe( ialu_regL_regL );
    1.32  %}

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