src/cpu/mips/vm/mips_64.ad

changeset 395
eeea63acbe68
parent 394
61b347fb2a89
child 396
474ce9f32bce
     1.1 --- a/src/cpu/mips/vm/mips_64.ad	Wed Apr 05 12:41:12 2017 +0800
     1.2 +++ b/src/cpu/mips/vm/mips_64.ad	Thu Apr 06 14:44:34 2017 +0800
     1.3 @@ -13987,7 +13987,7 @@
     1.4  // Floats vector add
     1.5  // kernel does not have emulation of PS instructions yet, so PS instructions is disabled.
     1.6  instruct vadd2F(vecD dst, vecD src) %{
     1.7 -  predicate(n->as_Vector()->length() == 2 && !UseLoongsonISA);
     1.8 +  predicate(n->as_Vector()->length() == 2);
     1.9    match(Set dst (AddVF dst src));
    1.10    format %{ "add.ps   $dst,$src\t! add packed2F" %}
    1.11    ins_encode %{
    1.12 @@ -13997,7 +13997,7 @@
    1.13  %}
    1.14  
    1.15  instruct vadd2F3(vecD dst, vecD src1, vecD src2) %{
    1.16 -  predicate(n->as_Vector()->length() == 2 && !UseLoongsonISA);
    1.17 +  predicate(n->as_Vector()->length() == 2);
    1.18    match(Set dst (AddVF src1 src2));
    1.19    format %{ "add.ps   $dst,$src1,$src2\t! add packed2F" %}
    1.20    ins_encode %{
    1.21 @@ -14010,7 +14010,7 @@
    1.22  
    1.23  // Floats vector sub
    1.24  instruct vsub2F(vecD dst, vecD src) %{
    1.25 -  predicate(n->as_Vector()->length() == 2 && !UseLoongsonISA);
    1.26 +  predicate(n->as_Vector()->length() == 2);
    1.27    match(Set dst (SubVF dst src));
    1.28    format %{ "sub.ps   $dst,$src\t! sub packed2F" %}
    1.29    ins_encode %{
    1.30 @@ -14023,7 +14023,7 @@
    1.31  
    1.32  // Floats vector mul
    1.33  instruct vmul2F(vecD dst, vecD src) %{
    1.34 -  predicate(n->as_Vector()->length() == 2 && !UseLoongsonISA);
    1.35 +  predicate(n->as_Vector()->length() == 2);
    1.36    match(Set dst (MulVF dst src));
    1.37    format %{ "mul.ps   $dst, $src\t! mul packed2F" %}
    1.38    ins_encode %{
    1.39 @@ -14033,7 +14033,7 @@
    1.40  %}
    1.41  
    1.42  instruct vmul2F3(vecD dst, vecD src1, vecD src2) %{
    1.43 -  predicate(n->as_Vector()->length() == 2 && !UseLoongsonISA);
    1.44 +  predicate(n->as_Vector()->length() == 2);
    1.45    match(Set dst (MulVF src1 src2));
    1.46    format %{ "mul.ps   $dst, $src1, $src2\t! mul packed2F" %}
    1.47    ins_encode %{
    1.48 @@ -14045,6 +14045,19 @@
    1.49  // --------------------------------- DIV --------------------------------------
    1.50  // MIPS do not have div.ps
    1.51  
    1.52 +// --------------------------------- MADD --------------------------------------
    1.53 +// Floats vector madd
    1.54 +//instruct vmadd2F(vecD dst, vecD src1, vecD src2, vecD src3) %{
    1.55 +//  predicate(n->as_Vector()->length() == 2);
    1.56 +//  match(Set dst (AddVF (MulVF src1 src2) src3));
    1.57 +//  ins_cost(50);
    1.58 +//  format %{ "madd.ps   $dst, $src3, $src1, $src2\t! madd packed2F" %}
    1.59 +//  ins_encode %{
    1.60 +//    __ madd_ps($dst$$FloatRegister, $src3$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
    1.61 +//  %}
    1.62 +//  ins_pipe( fpu_regF_regF );
    1.63 +//%}
    1.64 +
    1.65  
    1.66  //----------PEEPHOLE RULES-----------------------------------------------------
    1.67  // These must follow all instruction definitions as they use the names

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