1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 1.2 +++ b/src/cpu/ppc/vm/macroAssembler_ppc.hpp Fri Aug 02 16:46:45 2013 +0200 1.3 @@ -0,0 +1,658 @@ 1.4 +/* 1.5 + * Copyright (c) 2002, 2013, Oracle and/or its affiliates. All rights reserved. 1.6 + * Copyright 2012, 2013 SAP AG. All rights reserved. 1.7 + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 1.8 + * 1.9 + * This code is free software; you can redistribute it and/or modify it 1.10 + * under the terms of the GNU General Public License version 2 only, as 1.11 + * published by the Free Software Foundation. 1.12 + * 1.13 + * This code is distributed in the hope that it will be useful, but WITHOUT 1.14 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1.15 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 1.16 + * version 2 for more details (a copy is included in the LICENSE file that 1.17 + * accompanied this code). 1.18 + * 1.19 + * You should have received a copy of the GNU General Public License version 1.20 + * 2 along with this work; if not, write to the Free Software Foundation, 1.21 + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 1.22 + * 1.23 + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 1.24 + * or visit www.oracle.com if you need additional information or have any 1.25 + * questions. 1.26 + * 1.27 + */ 1.28 + 1.29 +#ifndef CPU_PPC_VM_MACROASSEMBLER_PPC_HPP 1.30 +#define CPU_PPC_VM_MACROASSEMBLER_PPC_HPP 1.31 + 1.32 +#include "asm/assembler.hpp" 1.33 + 1.34 +// MacroAssembler extends Assembler by a few frequently used macros. 1.35 + 1.36 +class ciTypeArray; 1.37 + 1.38 +class MacroAssembler: public Assembler { 1.39 + public: 1.40 + MacroAssembler(CodeBuffer* code) : Assembler(code) {} 1.41 + 1.42 + // 1.43 + // Optimized instruction emitters 1.44 + // 1.45 + 1.46 + inline static int largeoffset_si16_si16_hi(int si31) { return (si31 + (1<<15)) >> 16; } 1.47 + inline static int largeoffset_si16_si16_lo(int si31) { return si31 - (((si31 + (1<<15)) >> 16) << 16); } 1.48 + 1.49 + // load d = *[a+si31] 1.50 + // Emits several instructions if the offset is not encodable in one instruction. 1.51 + void ld_largeoffset_unchecked(Register d, int si31, Register a, int emit_filler_nop); 1.52 + void ld_largeoffset (Register d, int si31, Register a, int emit_filler_nop); 1.53 + inline static bool is_ld_largeoffset(address a); 1.54 + inline static int get_ld_largeoffset_offset(address a); 1.55 + 1.56 + inline void round_to(Register r, int modulus); 1.57 + 1.58 + // Load/store with type given by parameter. 1.59 + void load_sized_value( Register dst, RegisterOrConstant offs, Register base, size_t size_in_bytes, bool is_signed); 1.60 + void store_sized_value(Register dst, RegisterOrConstant offs, Register base, size_t size_in_bytes); 1.61 + 1.62 + // Move register if destination register and target register are different 1.63 + inline void mr_if_needed(Register rd, Register rs); 1.64 + 1.65 + // nop padding 1.66 + void align(int modulus); 1.67 + 1.68 + // 1.69 + // Constants, loading constants, TOC support 1.70 + // 1.71 + 1.72 + // Address of the global TOC. 1.73 + inline static address global_toc(); 1.74 + // Offset of given address to the global TOC. 1.75 + inline static int offset_to_global_toc(const address addr); 1.76 + 1.77 + // Address of TOC of the current method. 1.78 + inline address method_toc(); 1.79 + // Offset of given address to TOC of the current method. 1.80 + inline int offset_to_method_toc(const address addr); 1.81 + 1.82 + // Global TOC. 1.83 + void calculate_address_from_global_toc(Register dst, address addr, 1.84 + bool hi16 = true, bool lo16 = true, 1.85 + bool add_relocation = true, bool emit_dummy_addr = false); 1.86 + inline void calculate_address_from_global_toc_hi16only(Register dst, address addr) { 1.87 + calculate_address_from_global_toc(dst, addr, true, false); 1.88 + }; 1.89 + inline void calculate_address_from_global_toc_lo16only(Register dst, address addr) { 1.90 + calculate_address_from_global_toc(dst, addr, false, true); 1.91 + }; 1.92 + 1.93 + inline static bool is_calculate_address_from_global_toc_at(address a, address bound); 1.94 + static int patch_calculate_address_from_global_toc_at(address a, address addr, address bound); 1.95 + static address get_address_of_calculate_address_from_global_toc_at(address a, address addr); 1.96 + 1.97 +#ifdef _LP64 1.98 + // Patch narrow oop constant. 1.99 + inline static bool is_set_narrow_oop(address a, address bound); 1.100 + static int patch_set_narrow_oop(address a, address bound, narrowOop data); 1.101 + static narrowOop get_narrow_oop(address a, address bound); 1.102 +#endif 1.103 + 1.104 + inline static bool is_load_const_at(address a); 1.105 + 1.106 + // Emits an oop const to the constant pool, loads the constant, and 1.107 + // sets a relocation info with address current_pc. 1.108 + void load_const_from_method_toc(Register dst, AddressLiteral& a, Register toc); 1.109 + void load_toc_from_toc(Register dst, AddressLiteral& a, Register toc) { 1.110 + assert(dst == R2_TOC, "base register must be TOC"); 1.111 + load_const_from_method_toc(dst, a, toc); 1.112 + } 1.113 + 1.114 + static bool is_load_const_from_method_toc_at(address a); 1.115 + static int get_offset_of_load_const_from_method_toc_at(address a); 1.116 + 1.117 + // Get the 64 bit constant from a `load_const' sequence. 1.118 + static long get_const(address load_const); 1.119 + 1.120 + // Patch the 64 bit constant of a `load_const' sequence. This is a 1.121 + // low level procedure. It neither flushes the instruction cache nor 1.122 + // is it atomic. 1.123 + static void patch_const(address load_const, long x); 1.124 + 1.125 + // Metadata in code that we have to keep track of. 1.126 + AddressLiteral allocate_metadata_address(Metadata* obj); // allocate_index 1.127 + AddressLiteral constant_metadata_address(Metadata* obj); // find_index 1.128 + // Oops used directly in compiled code are stored in the constant pool, 1.129 + // and loaded from there. 1.130 + // Allocate new entry for oop in constant pool. Generate relocation. 1.131 + AddressLiteral allocate_oop_address(jobject obj); 1.132 + // Find oop obj in constant pool. Return relocation with it's index. 1.133 + AddressLiteral constant_oop_address(jobject obj); 1.134 + 1.135 + // Find oop in constant pool and emit instructions to load it. 1.136 + // Uses constant_oop_address. 1.137 + inline void set_oop_constant(jobject obj, Register d); 1.138 + // Same as load_address. 1.139 + inline void set_oop (AddressLiteral obj_addr, Register d); 1.140 + 1.141 + // Read runtime constant: Issue load if constant not yet established, 1.142 + // else use real constant. 1.143 + virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, 1.144 + Register tmp, 1.145 + int offset); 1.146 + 1.147 + // 1.148 + // branch, jump 1.149 + // 1.150 + 1.151 + inline void pd_patch_instruction(address branch, address target); 1.152 + NOT_PRODUCT(static void pd_print_patched_instruction(address branch);) 1.153 + 1.154 + // Conditional far branch for destinations encodable in 24+2 bits. 1.155 + // Same interface as bc, e.g. no inverse boint-field. 1.156 + enum { 1.157 + bc_far_optimize_not = 0, 1.158 + bc_far_optimize_on_relocate = 1 1.159 + }; 1.160 + // optimize: flag for telling the conditional far branch to optimize 1.161 + // itself when relocated. 1.162 + void bc_far(int boint, int biint, Label& dest, int optimize); 1.163 + // Relocation of conditional far branches. 1.164 + static bool is_bc_far_at(address instruction_addr); 1.165 + static address get_dest_of_bc_far_at(address instruction_addr); 1.166 + static void set_dest_of_bc_far_at(address instruction_addr, address dest); 1.167 + private: 1.168 + static bool inline is_bc_far_variant1_at(address instruction_addr); 1.169 + static bool inline is_bc_far_variant2_at(address instruction_addr); 1.170 + static bool inline is_bc_far_variant3_at(address instruction_addr); 1.171 + public: 1.172 + 1.173 + // Convenience bc_far versions. 1.174 + inline void blt_far(ConditionRegister crx, Label& L, int optimize); 1.175 + inline void bgt_far(ConditionRegister crx, Label& L, int optimize); 1.176 + inline void beq_far(ConditionRegister crx, Label& L, int optimize); 1.177 + inline void bso_far(ConditionRegister crx, Label& L, int optimize); 1.178 + inline void bge_far(ConditionRegister crx, Label& L, int optimize); 1.179 + inline void ble_far(ConditionRegister crx, Label& L, int optimize); 1.180 + inline void bne_far(ConditionRegister crx, Label& L, int optimize); 1.181 + inline void bns_far(ConditionRegister crx, Label& L, int optimize); 1.182 + 1.183 + // Emit, identify and patch a NOT mt-safe patchable 64 bit absolute call/jump. 1.184 + private: 1.185 + enum { 1.186 + bxx64_patchable_instruction_count = (2/*load_codecache_const*/ + 3/*5load_const*/ + 1/*mtctr*/ + 1/*bctrl*/), 1.187 + bxx64_patchable_size = bxx64_patchable_instruction_count * BytesPerInstWord, 1.188 + bxx64_patchable_ret_addr_offset = bxx64_patchable_size 1.189 + }; 1.190 + void bxx64_patchable(address target, relocInfo::relocType rt, bool link); 1.191 + static bool is_bxx64_patchable_at( address instruction_addr, bool link); 1.192 + // Does the instruction use a pc-relative encoding of the destination? 1.193 + static bool is_bxx64_patchable_pcrelative_at( address instruction_addr, bool link); 1.194 + static bool is_bxx64_patchable_variant1_at( address instruction_addr, bool link); 1.195 + // Load destination relative to global toc. 1.196 + static bool is_bxx64_patchable_variant1b_at( address instruction_addr, bool link); 1.197 + static bool is_bxx64_patchable_variant2_at( address instruction_addr, bool link); 1.198 + static void set_dest_of_bxx64_patchable_at( address instruction_addr, address target, bool link); 1.199 + static address get_dest_of_bxx64_patchable_at(address instruction_addr, bool link); 1.200 + 1.201 + public: 1.202 + // call 1.203 + enum { 1.204 + bl64_patchable_instruction_count = bxx64_patchable_instruction_count, 1.205 + bl64_patchable_size = bxx64_patchable_size, 1.206 + bl64_patchable_ret_addr_offset = bxx64_patchable_ret_addr_offset 1.207 + }; 1.208 + inline void bl64_patchable(address target, relocInfo::relocType rt) { 1.209 + bxx64_patchable(target, rt, /*link=*/true); 1.210 + } 1.211 + inline static bool is_bl64_patchable_at(address instruction_addr) { 1.212 + return is_bxx64_patchable_at(instruction_addr, /*link=*/true); 1.213 + } 1.214 + inline static bool is_bl64_patchable_pcrelative_at(address instruction_addr) { 1.215 + return is_bxx64_patchable_pcrelative_at(instruction_addr, /*link=*/true); 1.216 + } 1.217 + inline static void set_dest_of_bl64_patchable_at(address instruction_addr, address target) { 1.218 + set_dest_of_bxx64_patchable_at(instruction_addr, target, /*link=*/true); 1.219 + } 1.220 + inline static address get_dest_of_bl64_patchable_at(address instruction_addr) { 1.221 + return get_dest_of_bxx64_patchable_at(instruction_addr, /*link=*/true); 1.222 + } 1.223 + // jump 1.224 + enum { 1.225 + b64_patchable_instruction_count = bxx64_patchable_instruction_count, 1.226 + b64_patchable_size = bxx64_patchable_size, 1.227 + }; 1.228 + inline void b64_patchable(address target, relocInfo::relocType rt) { 1.229 + bxx64_patchable(target, rt, /*link=*/false); 1.230 + } 1.231 + inline static bool is_b64_patchable_at(address instruction_addr) { 1.232 + return is_bxx64_patchable_at(instruction_addr, /*link=*/false); 1.233 + } 1.234 + inline static bool is_b64_patchable_pcrelative_at(address instruction_addr) { 1.235 + return is_bxx64_patchable_pcrelative_at(instruction_addr, /*link=*/false); 1.236 + } 1.237 + inline static void set_dest_of_b64_patchable_at(address instruction_addr, address target) { 1.238 + set_dest_of_bxx64_patchable_at(instruction_addr, target, /*link=*/false); 1.239 + } 1.240 + inline static address get_dest_of_b64_patchable_at(address instruction_addr) { 1.241 + return get_dest_of_bxx64_patchable_at(instruction_addr, /*link=*/false); 1.242 + } 1.243 + 1.244 + // 1.245 + // Support for frame handling 1.246 + // 1.247 + 1.248 + // some ABI-related functions 1.249 + void save_nonvolatile_gprs( Register dst_base, int offset); 1.250 + void restore_nonvolatile_gprs(Register src_base, int offset); 1.251 + void save_volatile_gprs( Register dst_base, int offset); 1.252 + void restore_volatile_gprs(Register src_base, int offset); 1.253 + void save_LR_CR( Register tmp); // tmp contains LR on return. 1.254 + void restore_LR_CR(Register tmp); 1.255 + 1.256 + // Get current PC using bl-next-instruction trick. 1.257 + address get_PC_trash_LR(Register result); 1.258 + 1.259 + // Resize current frame either relatively wrt to current SP or absolute. 1.260 + void resize_frame(Register offset, Register tmp); 1.261 + void resize_frame(int offset, Register tmp); 1.262 + void resize_frame_absolute(Register addr, Register tmp1, Register tmp2); 1.263 + 1.264 + // Push a frame of size bytes. 1.265 + void push_frame(Register bytes, Register tmp); 1.266 + 1.267 + // Push a frame of size `bytes'. No abi space provided. 1.268 + void push_frame(unsigned int bytes, Register tmp); 1.269 + 1.270 + // Push a frame of size `bytes' plus abi112 on top. 1.271 + void push_frame_abi112(unsigned int bytes, Register tmp); 1.272 + 1.273 + // Setup up a new C frame with a spill area for non-volatile GPRs and additional 1.274 + // space for local variables 1.275 + void push_frame_abi112_nonvolatiles(unsigned int bytes, Register tmp); 1.276 + 1.277 + // pop current C frame 1.278 + void pop_frame(); 1.279 + 1.280 + // 1.281 + // Calls 1.282 + // 1.283 + 1.284 + private: 1.285 + address _last_calls_return_pc; 1.286 + 1.287 + // Generic version of a call to C function via a function descriptor 1.288 + // with variable support for C calling conventions (TOC, ENV, etc.). 1.289 + // updates and returns _last_calls_return_pc. 1.290 + address branch_to(Register function_descriptor, bool and_link, bool save_toc_before_call, 1.291 + bool restore_toc_after_call, bool load_toc_of_callee, bool load_env_of_callee); 1.292 + 1.293 + public: 1.294 + 1.295 + // Get the pc where the last call will return to. returns _last_calls_return_pc. 1.296 + inline address last_calls_return_pc(); 1.297 + 1.298 + // Call a C function via a function descriptor and use full C 1.299 + // calling conventions. Updates and returns _last_calls_return_pc. 1.300 + address call_c(Register function_descriptor); 1.301 + address call_c(const FunctionDescriptor* function_descriptor, relocInfo::relocType rt); 1.302 + address call_c_using_toc(const FunctionDescriptor* function_descriptor, relocInfo::relocType rt, 1.303 + Register toc); 1.304 + 1.305 + protected: 1.306 + 1.307 + // It is imperative that all calls into the VM are handled via the 1.308 + // call_VM macros. They make sure that the stack linkage is setup 1.309 + // correctly. call_VM's correspond to ENTRY/ENTRY_X entry points 1.310 + // while call_VM_leaf's correspond to LEAF entry points. 1.311 + // 1.312 + // This is the base routine called by the different versions of 1.313 + // call_VM. The interpreter may customize this version by overriding 1.314 + // it for its purposes (e.g., to save/restore additional registers 1.315 + // when doing a VM call). 1.316 + // 1.317 + // If no last_java_sp is specified (noreg) then SP will be used instead. 1.318 + virtual void call_VM_base( 1.319 + // where an oop-result ends up if any; use noreg otherwise 1.320 + Register oop_result, 1.321 + // to set up last_Java_frame in stubs; use noreg otherwise 1.322 + Register last_java_sp, 1.323 + // the entry point 1.324 + address entry_point, 1.325 + // flag which indicates if exception should be checked 1.326 + bool check_exception=true 1.327 + ); 1.328 + 1.329 + // Support for VM calls. This is the base routine called by the 1.330 + // different versions of call_VM_leaf. The interpreter may customize 1.331 + // this version by overriding it for its purposes (e.g., to 1.332 + // save/restore additional registers when doing a VM call). 1.333 + void call_VM_leaf_base(address entry_point); 1.334 + 1.335 + public: 1.336 + // Call into the VM. 1.337 + // Passes the thread pointer (in R3_ARG1) as a prepended argument. 1.338 + // Makes sure oop return values are visible to the GC. 1.339 + void call_VM(Register oop_result, address entry_point, bool check_exceptions = true); 1.340 + void call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions = true); 1.341 + void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true); 1.342 + void call_VM_leaf(address entry_point); 1.343 + void call_VM_leaf(address entry_point, Register arg_1); 1.344 + void call_VM_leaf(address entry_point, Register arg_1, Register arg_2); 1.345 + void call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3); 1.346 + 1.347 + // Call a stub function via a function descriptor, but don't save 1.348 + // TOC before call, don't setup TOC and ENV for call, and don't 1.349 + // restore TOC after call. Updates and returns _last_calls_return_pc. 1.350 + inline address call_stub(Register function_entry); 1.351 + inline void call_stub_and_return_to(Register function_entry, Register return_pc); 1.352 + 1.353 + // 1.354 + // Java utilities 1.355 + // 1.356 + 1.357 + // Read from the polling page, its address is already in a register. 1.358 + inline void load_from_polling_page(Register polling_page_address, int offset = 0); 1.359 + // Check whether instruction is a read access to the polling page 1.360 + // which was emitted by load_from_polling_page(..). 1.361 + static bool is_load_from_polling_page(int instruction, void* ucontext/*may be NULL*/, 1.362 + address* polling_address_ptr = NULL); 1.363 + 1.364 + // Check whether instruction is a write access to the memory 1.365 + // serialization page realized by one of the instructions stw, stwu, 1.366 + // stwx, or stwux. 1.367 + static bool is_memory_serialization(int instruction, JavaThread* thread, void* ucontext); 1.368 + 1.369 + // Support for NULL-checks 1.370 + // 1.371 + // Generates code that causes a NULL OS exception if the content of reg is NULL. 1.372 + // If the accessed location is M[reg + offset] and the offset is known, provide the 1.373 + // offset. No explicit code generation is needed if the offset is within a certain 1.374 + // range (0 <= offset <= page_size). 1.375 + 1.376 + // Stack overflow checking 1.377 + void bang_stack_with_offset(int offset); 1.378 + 1.379 + // If instruction is a stack bang of the form ld, stdu, or 1.380 + // stdux, return the banged address. Otherwise, return 0. 1.381 + static address get_stack_bang_address(int instruction, void* ucontext); 1.382 + 1.383 + // Atomics 1.384 + // CmpxchgX sets condition register to cmpX(current, compare). 1.385 + // (flag == ne) => (dest_current_value != compare_value), (!swapped) 1.386 + // (flag == eq) => (dest_current_value == compare_value), ( swapped) 1.387 + static inline bool cmpxchgx_hint_acquire_lock() { return true; } 1.388 + // The stxcx will probably not be succeeded by a releasing store. 1.389 + static inline bool cmpxchgx_hint_release_lock() { return false; } 1.390 + static inline bool cmpxchgx_hint_atomic_update() { return false; } 1.391 + 1.392 + // Cmpxchg semantics 1.393 + enum { 1.394 + MemBarNone = 0, 1.395 + MemBarRel = 1, 1.396 + MemBarAcq = 2, 1.397 + MemBarFenceAfter = 4 // use powers of 2 1.398 + }; 1.399 + void cmpxchgw(ConditionRegister flag, 1.400 + Register dest_current_value, Register compare_value, Register exchange_value, Register addr_base, 1.401 + int semantics, bool cmpxchgx_hint = false, 1.402 + Register int_flag_success = noreg, bool contention_hint = false); 1.403 + void cmpxchgd(ConditionRegister flag, 1.404 + Register dest_current_value, Register compare_value, Register exchange_value, Register addr_base, 1.405 + int semantics, bool cmpxchgx_hint = false, 1.406 + Register int_flag_success = noreg, Label* failed = NULL, bool contention_hint = false); 1.407 + 1.408 + // interface method calling 1.409 + void lookup_interface_method(Register recv_klass, 1.410 + Register intf_klass, 1.411 + RegisterOrConstant itable_index, 1.412 + Register method_result, 1.413 + Register temp_reg, Register temp2_reg, 1.414 + Label& no_such_interface); 1.415 + 1.416 + // virtual method calling 1.417 + void lookup_virtual_method(Register recv_klass, 1.418 + RegisterOrConstant vtable_index, 1.419 + Register method_result); 1.420 + 1.421 + // Test sub_klass against super_klass, with fast and slow paths. 1.422 + 1.423 + // The fast path produces a tri-state answer: yes / no / maybe-slow. 1.424 + // One of the three labels can be NULL, meaning take the fall-through. 1.425 + // If super_check_offset is -1, the value is loaded up from super_klass. 1.426 + // No registers are killed, except temp_reg and temp2_reg. 1.427 + // If super_check_offset is not -1, temp2_reg is not used and can be noreg. 1.428 + void check_klass_subtype_fast_path(Register sub_klass, 1.429 + Register super_klass, 1.430 + Register temp1_reg, 1.431 + Register temp2_reg, 1.432 + Label& L_success, 1.433 + Label& L_failure); 1.434 + 1.435 + // The rest of the type check; must be wired to a corresponding fast path. 1.436 + // It does not repeat the fast path logic, so don't use it standalone. 1.437 + // The temp_reg can be noreg, if no temps are available. 1.438 + // It can also be sub_klass or super_klass, meaning it's OK to kill that one. 1.439 + // Updates the sub's secondary super cache as necessary. 1.440 + void check_klass_subtype_slow_path(Register sub_klass, 1.441 + Register super_klass, 1.442 + Register temp1_reg, 1.443 + Register temp2_reg, 1.444 + Label* L_success = NULL, 1.445 + Register result_reg = noreg); 1.446 + 1.447 + // Simplified, combined version, good for typical uses. 1.448 + // Falls through on failure. 1.449 + void check_klass_subtype(Register sub_klass, 1.450 + Register super_klass, 1.451 + Register temp1_reg, 1.452 + Register temp2_reg, 1.453 + Label& L_success); 1.454 + 1.455 + // Method handle support (JSR 292). 1.456 + void check_method_handle_type(Register mtype_reg, Register mh_reg, Register temp_reg, Label& wrong_method_type); 1.457 + 1.458 + RegisterOrConstant argument_offset(RegisterOrConstant arg_slot, Register temp_reg, int extra_slot_offset = 0); 1.459 + 1.460 + // Biased locking support 1.461 + // Upon entry,obj_reg must contain the target object, and mark_reg 1.462 + // must contain the target object's header. 1.463 + // Destroys mark_reg if an attempt is made to bias an anonymously 1.464 + // biased lock. In this case a failure will go either to the slow 1.465 + // case or fall through with the notEqual condition code set with 1.466 + // the expectation that the slow case in the runtime will be called. 1.467 + // In the fall-through case where the CAS-based lock is done, 1.468 + // mark_reg is not destroyed. 1.469 + void biased_locking_enter(ConditionRegister cr_reg, Register obj_reg, Register mark_reg, Register temp_reg, 1.470 + Register temp2_reg, Label& done, Label* slow_case = NULL); 1.471 + // Upon entry, the base register of mark_addr must contain the oop. 1.472 + // Destroys temp_reg. 1.473 + // If allow_delay_slot_filling is set to true, the next instruction 1.474 + // emitted after this one will go in an annulled delay slot if the 1.475 + // biased locking exit case failed. 1.476 + void biased_locking_exit(ConditionRegister cr_reg, Register mark_addr, Register temp_reg, Label& done); 1.477 + 1.478 + void compiler_fast_lock_object( ConditionRegister flag, Register oop, Register box, Register tmp1, Register tmp2, Register tmp3); 1.479 + void compiler_fast_unlock_object(ConditionRegister flag, Register oop, Register box, Register tmp1, Register tmp2, Register tmp3); 1.480 + 1.481 + // Support for serializing memory accesses between threads 1.482 + void serialize_memory(Register thread, Register tmp1, Register tmp2); 1.483 + 1.484 + // GC barrier support. 1.485 + void card_write_barrier_post(Register Rstore_addr, Register Rnew_val, Register Rtmp); 1.486 + void card_table_write(jbyte* byte_map_base, Register Rtmp, Register Robj); 1.487 + 1.488 +#ifndef SERIALGC 1.489 + // General G1 pre-barrier generator. 1.490 + void g1_write_barrier_pre(Register Robj, RegisterOrConstant offset, Register Rpre_val, 1.491 + Register Rtmp1, Register Rtmp2, bool needs_frame = false); 1.492 + // General G1 post-barrier generator 1.493 + void g1_write_barrier_post(Register Rstore_addr, Register Rnew_val, Register Rtmp1, 1.494 + Register Rtmp2, Register Rtmp3, Label *filtered_ext = NULL); 1.495 +#endif // SERIALGC 1.496 + 1.497 + // Support for managing the JavaThread pointer (i.e.; the reference to 1.498 + // thread-local information). 1.499 + 1.500 + // Support for last Java frame (but use call_VM instead where possible): 1.501 + // access R16_thread->last_Java_sp. 1.502 + void set_last_Java_frame(Register last_java_sp, Register last_Java_pc); 1.503 + void reset_last_Java_frame(void); 1.504 + void set_top_ijava_frame_at_SP_as_last_Java_frame(Register sp, Register tmp1); 1.505 + 1.506 + // Read vm result from thread: oop_result = R16_thread->result; 1.507 + void get_vm_result (Register oop_result); 1.508 + void get_vm_result_2(Register metadata_result); 1.509 + 1.510 + static bool needs_explicit_null_check(intptr_t offset); 1.511 + 1.512 + // Trap-instruction-based checks. 1.513 + // Range checks can be distinguished from zero checks as they check 32 bit, 1.514 + // zero checks all 64 bits (tw, td). 1.515 + inline void trap_null_check(Register a, trap_to_bits cmp = traptoEqual); 1.516 + static bool is_trap_null_check(int x) { 1.517 + return is_tdi(x, traptoEqual, -1/*any reg*/, 0) || 1.518 + is_tdi(x, traptoGreaterThanUnsigned, -1/*any reg*/, 0); 1.519 + } 1.520 + 1.521 + inline void trap_zombie_not_entrant(); 1.522 + static bool is_trap_zombie_not_entrant(int x) { return is_tdi(x, traptoUnconditional, 0/*reg 0*/, 1); } 1.523 + 1.524 + inline void trap_should_not_reach_here(); 1.525 + static bool is_trap_should_not_reach_here(int x) { return is_tdi(x, traptoUnconditional, 0/*reg 0*/, 2); } 1.526 + 1.527 + inline void trap_ic_miss_check(Register a, Register b); 1.528 + static bool is_trap_ic_miss_check(int x) { 1.529 + return is_td(x, traptoGreaterThanUnsigned | traptoLessThanUnsigned, -1/*any reg*/, -1/*any reg*/); 1.530 + } 1.531 + 1.532 + // Implicit or explicit null check, jumps to static address exception_entry. 1.533 + inline void null_check_throw(Register a, int offset, Register temp_reg, address exception_entry); 1.534 + 1.535 + // Check accessed object for null. Use SIGTRAP-based null checks on AIX. 1.536 + inline void ld_with_trap_null_check(Register d, int si16, Register s1); 1.537 + // Variant for heap OOPs including decompression of compressed OOPs. 1.538 + inline void load_heap_oop_with_trap_null_check(Register d, RegisterOrConstant offs, Register s1); 1.539 + 1.540 + // Load heap oop and decompress. Loaded oop may not be null. 1.541 + inline void load_heap_oop_not_null(Register d, RegisterOrConstant offs, Register s1 = noreg); 1.542 + 1.543 + // Null allowed. 1.544 + inline void load_heap_oop(Register d, RegisterOrConstant offs, Register s1 = noreg); 1.545 + 1.546 + // Encode/decode heap oop. Oop may not be null, else en/decoding goes wrong. 1.547 + inline void encode_heap_oop_not_null(Register d); 1.548 + inline void decode_heap_oop_not_null(Register d); 1.549 + 1.550 + // Null allowed. 1.551 + inline void decode_heap_oop(Register d); 1.552 + 1.553 + // Load/Store klass oop from klass field. Compress. 1.554 + void load_klass(Register dst, Register src); 1.555 + void load_klass_with_trap_null_check(Register dst, Register src); 1.556 + void store_klass(Register dst_oop, Register klass, Register tmp = R0); 1.557 + void decode_klass_not_null(Register dst, Register src = noreg); 1.558 + void encode_klass_not_null(Register dst, Register src = noreg); 1.559 + 1.560 + // Load common heap base into register. 1.561 + void reinit_heapbase(Register d, Register tmp = noreg); 1.562 + 1.563 + // SIGTRAP-based range checks for arrays. 1.564 + inline void trap_range_check_l(Register a, Register b); 1.565 + inline void trap_range_check_l(Register a, int si16); 1.566 + static bool is_trap_range_check_l(int x) { 1.567 + return (is_tw (x, traptoLessThanUnsigned, -1/*any reg*/, -1/*any reg*/) || 1.568 + is_twi(x, traptoLessThanUnsigned, -1/*any reg*/) ); 1.569 + } 1.570 + inline void trap_range_check_le(Register a, int si16); 1.571 + static bool is_trap_range_check_le(int x) { 1.572 + return is_twi(x, traptoEqual | traptoLessThanUnsigned, -1/*any reg*/); 1.573 + } 1.574 + inline void trap_range_check_g(Register a, int si16); 1.575 + static bool is_trap_range_check_g(int x) { 1.576 + return is_twi(x, traptoGreaterThanUnsigned, -1/*any reg*/); 1.577 + } 1.578 + inline void trap_range_check_ge(Register a, Register b); 1.579 + inline void trap_range_check_ge(Register a, int si16); 1.580 + static bool is_trap_range_check_ge(int x) { 1.581 + return (is_tw (x, traptoEqual | traptoGreaterThanUnsigned, -1/*any reg*/, -1/*any reg*/) || 1.582 + is_twi(x, traptoEqual | traptoGreaterThanUnsigned, -1/*any reg*/) ); 1.583 + } 1.584 + static bool is_trap_range_check(int x) { 1.585 + return is_trap_range_check_l(x) || is_trap_range_check_le(x) || 1.586 + is_trap_range_check_g(x) || is_trap_range_check_ge(x); 1.587 + } 1.588 + 1.589 + // Needle of length 1. 1.590 + void string_indexof_1(Register result, Register haystack, Register haycnt, 1.591 + Register needle, jchar needleChar, 1.592 + Register tmp1, Register tmp2); 1.593 + // General indexof, eventually with constant needle length. 1.594 + void string_indexof(Register result, Register haystack, Register haycnt, 1.595 + Register needle, ciTypeArray* needle_values, Register needlecnt, int needlecntval, 1.596 + Register tmp1, Register tmp2, Register tmp3, Register tmp4); 1.597 + void string_compare(Register str1_reg, Register str2_reg, Register cnt1_reg, Register cnt2_reg, 1.598 + Register result_reg, Register tmp_reg); 1.599 + void char_arrays_equals(Register str1_reg, Register str2_reg, Register cnt_reg, Register result_reg, 1.600 + Register tmp1_reg, Register tmp2_reg, Register tmp3_reg, Register tmp4_reg, 1.601 + Register tmp5_reg); 1.602 + void char_arrays_equalsImm(Register str1_reg, Register str2_reg, int cntval, Register result_reg, 1.603 + Register tmp1_reg, Register tmp2_reg); 1.604 + 1.605 + // 1.606 + // Debugging 1.607 + // 1.608 + 1.609 + // assert on cr0 1.610 + void asm_assert(bool check_equal, const char* msg, int id); 1.611 + void asm_assert_eq(const char* msg, int id) { asm_assert(true, msg, id); } 1.612 + void asm_assert_ne(const char* msg, int id) { asm_assert(false, msg, id); } 1.613 + 1.614 + private: 1.615 + void asm_assert_mems_zero(bool check_equal, int size, int mem_offset, Register mem_base, 1.616 + const char* msg, int id); 1.617 + 1.618 + public: 1.619 + 1.620 + void asm_assert_mem8_is_zero(int mem_offset, Register mem_base, const char* msg, int id) { 1.621 + asm_assert_mems_zero(true, 8, mem_offset, mem_base, msg, id); 1.622 + } 1.623 + void asm_assert_mem8_isnot_zero(int mem_offset, Register mem_base, const char* msg, int id) { 1.624 + asm_assert_mems_zero(false, 8, mem_offset, mem_base, msg, id); 1.625 + } 1.626 + 1.627 + // Verify R16_thread contents. 1.628 + void verify_thread(); 1.629 + 1.630 + // Emit code to verify that reg contains a valid oop if +VerifyOops is set. 1.631 + void verify_oop(Register reg, const char* s = "broken oop"); 1.632 + 1.633 + // TODO: verify method and klass metadata (compare against vptr?) 1.634 + void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {} 1.635 + void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){} 1.636 + 1.637 +#define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__) 1.638 +#define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__) 1.639 + 1.640 + private: 1.641 + 1.642 + enum { 1.643 + stop_stop = 0, 1.644 + stop_untested = 1, 1.645 + stop_unimplemented = 2, 1.646 + stop_shouldnotreachhere = 3, 1.647 + stop_end = 4 1.648 + }; 1.649 + void stop(int type, const char* msg, int id); 1.650 + 1.651 + public: 1.652 + // Prints msg, dumps registers and stops execution. 1.653 + void stop (const char* msg = "", int id = 0) { stop(stop_stop, msg, id); } 1.654 + void untested (const char* msg = "", int id = 0) { stop(stop_untested, msg, id); } 1.655 + void unimplemented(const char* msg = "", int id = 0) { stop(stop_unimplemented, msg, id); } 1.656 + void should_not_reach_here() { stop(stop_shouldnotreachhere, "", -1); } 1.657 + 1.658 + void zap_from_to(Register low, int before, Register high, int after, Register val, Register addr) PRODUCT_RETURN; 1.659 +}; 1.660 + 1.661 +#endif // CPU_PPC_VM_MACROASSEMBLER_PPC_HPP