1.1 --- a/src/share/vm/opto/compile.cpp Thu Aug 22 09:39:54 2013 -0700
1.2 +++ b/src/share/vm/opto/compile.cpp Thu Sep 05 11:04:39 2013 -0700
1.3 @@ -2139,7 +2139,9 @@
1.4 //------------------------------Code_Gen---------------------------------------
1.5 // Given a graph, generate code for it
1.6 void Compile::Code_Gen() {
1.7 - if (failing()) return;
1.8 + if (failing()) {
1.9 + return;
1.10 + }
1.11
1.12 // Perform instruction selection. You might think we could reclaim Matcher
1.13 // memory PDQ, but actually the Matcher is used in generating spill code.
1.14 @@ -2151,12 +2153,11 @@
1.15 // nodes. Mapping is only valid at the root of each matched subtree.
1.16 NOT_PRODUCT( verify_graph_edges(); )
1.17
1.18 - Node_List proj_list;
1.19 - Matcher m(proj_list);
1.20 - _matcher = &m;
1.21 + Matcher matcher;
1.22 + _matcher = &matcher;
1.23 {
1.24 TracePhase t2("matcher", &_t_matcher, true);
1.25 - m.match();
1.26 + matcher.match();
1.27 }
1.28 // In debug mode can dump m._nodes.dump() for mapping of ideal to machine
1.29 // nodes. Mapping is only valid at the root of each matched subtree.
1.30 @@ -2164,31 +2165,26 @@
1.31
1.32 // If you have too many nodes, or if matching has failed, bail out
1.33 check_node_count(0, "out of nodes matching instructions");
1.34 - if (failing()) return;
1.35 + if (failing()) {
1.36 + return;
1.37 + }
1.38
1.39 // Build a proper-looking CFG
1.40 - PhaseCFG cfg(node_arena(), root(), m);
1.41 + PhaseCFG cfg(node_arena(), root(), matcher);
1.42 _cfg = &cfg;
1.43 {
1.44 NOT_PRODUCT( TracePhase t2("scheduler", &_t_scheduler, TimeCompiler); )
1.45 - cfg.Dominators();
1.46 - if (failing()) return;
1.47 -
1.48 + bool success = cfg.do_global_code_motion();
1.49 + if (!success) {
1.50 + return;
1.51 + }
1.52 +
1.53 + print_method(PHASE_GLOBAL_CODE_MOTION, 2);
1.54 NOT_PRODUCT( verify_graph_edges(); )
1.55 -
1.56 - cfg.Estimate_Block_Frequency();
1.57 - cfg.GlobalCodeMotion(m,unique(),proj_list);
1.58 - if (failing()) return;
1.59 -
1.60 - print_method(PHASE_GLOBAL_CODE_MOTION, 2);
1.61 -
1.62 - NOT_PRODUCT( verify_graph_edges(); )
1.63 -
1.64 debug_only( cfg.verify(); )
1.65 }
1.66 - NOT_PRODUCT( verify_graph_edges(); )
1.67 -
1.68 - PhaseChaitin regalloc(unique(), cfg, m);
1.69 +
1.70 + PhaseChaitin regalloc(unique(), cfg, matcher);
1.71 _regalloc = ®alloc;
1.72 {
1.73 TracePhase t2("regalloc", &_t_registerAllocation, true);
1.74 @@ -2209,7 +2205,7 @@
1.75 // can now safely remove it.
1.76 {
1.77 NOT_PRODUCT( TracePhase t2("blockOrdering", &_t_blockOrdering, TimeCompiler); )
1.78 - cfg.remove_empty();
1.79 + cfg.remove_empty_blocks();
1.80 if (do_freq_based_layout()) {
1.81 PhaseBlockLayout layout(cfg);
1.82 } else {
1.83 @@ -2256,38 +2252,50 @@
1.84 _regalloc->dump_frame();
1.85
1.86 Node *n = NULL;
1.87 - for( uint i=0; i<_cfg->_num_blocks; i++ ) {
1.88 - if (VMThread::should_terminate()) { cut_short = true; break; }
1.89 - Block *b = _cfg->_blocks[i];
1.90 - if (b->is_connector() && !Verbose) continue;
1.91 - n = b->_nodes[0];
1.92 - if (pcs && n->_idx < pc_limit)
1.93 + for (uint i = 0; i < _cfg->number_of_blocks(); i++) {
1.94 + if (VMThread::should_terminate()) {
1.95 + cut_short = true;
1.96 + break;
1.97 + }
1.98 + Block* block = _cfg->get_block(i);
1.99 + if (block->is_connector() && !Verbose) {
1.100 + continue;
1.101 + }
1.102 + n = block->_nodes[0];
1.103 + if (pcs && n->_idx < pc_limit) {
1.104 tty->print("%3.3x ", pcs[n->_idx]);
1.105 - else
1.106 + } else {
1.107 tty->print(" ");
1.108 - b->dump_head( &_cfg->_bbs );
1.109 - if (b->is_connector()) {
1.110 + }
1.111 + block->dump_head(_cfg);
1.112 + if (block->is_connector()) {
1.113 tty->print_cr(" # Empty connector block");
1.114 - } else if (b->num_preds() == 2 && b->pred(1)->is_CatchProj() && b->pred(1)->as_CatchProj()->_con == CatchProjNode::fall_through_index) {
1.115 + } else if (block->num_preds() == 2 && block->pred(1)->is_CatchProj() && block->pred(1)->as_CatchProj()->_con == CatchProjNode::fall_through_index) {
1.116 tty->print_cr(" # Block is sole successor of call");
1.117 }
1.118
1.119 // For all instructions
1.120 Node *delay = NULL;
1.121 - for( uint j = 0; j<b->_nodes.size(); j++ ) {
1.122 - if (VMThread::should_terminate()) { cut_short = true; break; }
1.123 - n = b->_nodes[j];
1.124 + for (uint j = 0; j < block->_nodes.size(); j++) {
1.125 + if (VMThread::should_terminate()) {
1.126 + cut_short = true;
1.127 + break;
1.128 + }
1.129 + n = block->_nodes[j];
1.130 if (valid_bundle_info(n)) {
1.131 - Bundle *bundle = node_bundling(n);
1.132 + Bundle* bundle = node_bundling(n);
1.133 if (bundle->used_in_unconditional_delay()) {
1.134 delay = n;
1.135 continue;
1.136 }
1.137 - if (bundle->starts_bundle())
1.138 + if (bundle->starts_bundle()) {
1.139 starts_bundle = '+';
1.140 + }
1.141 }
1.142
1.143 - if (WizardMode) n->dump();
1.144 + if (WizardMode) {
1.145 + n->dump();
1.146 + }
1.147
1.148 if( !n->is_Region() && // Dont print in the Assembly
1.149 !n->is_Phi() && // a few noisely useless nodes
1.150 @@ -3528,7 +3536,7 @@
1.151 }
1.152
1.153 Compile::Constant Compile::ConstantTable::add(MachConstantNode* n, BasicType type, jvalue value) {
1.154 - Block* b = Compile::current()->cfg()->_bbs[n->_idx];
1.155 + Block* b = Compile::current()->cfg()->get_block_for_node(n);
1.156 Constant con(type, value, b->_freq);
1.157 add(con);
1.158 return con;
