1.1 --- a/src/cpu/x86/vm/templateTable_x86_64.cpp Tue Apr 05 19:14:03 2011 -0700 1.2 +++ b/src/cpu/x86/vm/templateTable_x86_64.cpp Thu Apr 07 09:53:20 2011 -0700 1.3 @@ -147,12 +147,21 @@ 1.4 } else { 1.5 __ leaq(rdx, obj); 1.6 } 1.7 - __ g1_write_barrier_pre(rdx, r8, rbx, val != noreg); 1.8 + __ g1_write_barrier_pre(rdx /* obj */, 1.9 + rbx /* pre_val */, 1.10 + r15_thread /* thread */, 1.11 + r8 /* tmp */, 1.12 + val != noreg /* tosca_live */, 1.13 + false /* expand_call */); 1.14 if (val == noreg) { 1.15 __ store_heap_oop_null(Address(rdx, 0)); 1.16 } else { 1.17 __ store_heap_oop(Address(rdx, 0), val); 1.18 - __ g1_write_barrier_post(rdx, val, r8, rbx); 1.19 + __ g1_write_barrier_post(rdx /* store_adr */, 1.20 + val /* new_val */, 1.21 + r15_thread /* thread */, 1.22 + r8 /* tmp */, 1.23 + rbx /* tmp2 */); 1.24 } 1.25 1.26 }