1.1 --- a/src/cpu/sparc/vm/assembler_sparc.hpp Mon May 10 14:58:38 2010 -0700
1.2 +++ b/src/cpu/sparc/vm/assembler_sparc.hpp Tue May 11 15:19:19 2010 -0700
1.3 @@ -1,5 +1,5 @@
1.4 /*
1.5 - * Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved.
1.6 + * Copyright 1997-2010 Sun Microsystems, Inc. All Rights Reserved.
1.7 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
1.8 *
1.9 * This code is free software; you can redistribute it and/or modify it
1.10 @@ -1380,24 +1380,25 @@
1.11
1.12 // pp 181
1.13
1.14 - void and3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | rs2(s2) ); }
1.15 - void and3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1.16 + void and3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | rs2(s2) ); }
1.17 + void and3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1.18 void andcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1.19 void andcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1.20 void andn( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | rs2(s2) ); }
1.21 void andn( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1.22 + void andn( Register s1, RegisterOrConstant s2, Register d);
1.23 void andncc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1.24 void andncc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1.25 - void or3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | rs2(s2) ); }
1.26 - void or3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1.27 + void or3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | rs2(s2) ); }
1.28 + void or3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1.29 void orcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1.30 void orcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1.31 void orn( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | rs2(s2) ); }
1.32 void orn( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1.33 void orncc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1.34 void orncc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1.35 - void xor3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | rs2(s2) ); }
1.36 - void xor3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1.37 + void xor3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | rs2(s2) ); }
1.38 + void xor3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1.39 void xorcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1.40 void xorcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1.41 void xnor( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | rs2(s2) ); }
1.42 @@ -2026,8 +2027,8 @@
1.43 inline void st_ptr(Register d, Register s1, ByteSize simm13a);
1.44 #endif
1.45
1.46 - // ld_long will perform ld for 32 bit VM's and ldx for 64 bit VM's
1.47 - // st_long will perform st for 32 bit VM's and stx for 64 bit VM's
1.48 + // ld_long will perform ldd for 32 bit VM's and ldx for 64 bit VM's
1.49 + // st_long will perform std for 32 bit VM's and stx for 64 bit VM's
1.50 inline void ld_long(Register s1, Register s2, Register d);
1.51 inline void ld_long(Register s1, int simm13a, Register d);
1.52 inline void ld_long(Register s1, RegisterOrConstant s2, Register d);
1.53 @@ -2038,23 +2039,19 @@
1.54 inline void st_long(Register d, const Address& a, int offset = 0);
1.55
1.56 // Helpers for address formation.
1.57 - // They update the dest in place, whether it is a register or constant.
1.58 - // They emit no code at all if src is a constant zero.
1.59 - // If dest is a constant and src is a register, the temp argument
1.60 - // is required, and becomes the result.
1.61 - // If dest is a register and src is a non-simm13 constant,
1.62 - // the temp argument is required, and is used to materialize the constant.
1.63 - void regcon_inc_ptr( RegisterOrConstant& dest, RegisterOrConstant src,
1.64 - Register temp = noreg );
1.65 - void regcon_sll_ptr( RegisterOrConstant& dest, RegisterOrConstant src,
1.66 - Register temp = noreg );
1.67 -
1.68 - RegisterOrConstant ensure_simm13_or_reg(RegisterOrConstant roc, Register Rtemp) {
1.69 - guarantee(Rtemp != noreg, "constant offset overflow");
1.70 - if (is_simm13(roc.constant_or_zero()))
1.71 - return roc; // register or short constant
1.72 - set(roc.as_constant(), Rtemp);
1.73 - return RegisterOrConstant(Rtemp);
1.74 + // - They emit only a move if s2 is a constant zero.
1.75 + // - If dest is a constant and either s1 or s2 is a register, the temp argument is required and becomes the result.
1.76 + // - If dest is a register and either s1 or s2 is a non-simm13 constant, the temp argument is required and used to materialize the constant.
1.77 + RegisterOrConstant regcon_andn_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
1.78 + RegisterOrConstant regcon_inc_ptr( RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
1.79 + RegisterOrConstant regcon_sll_ptr( RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
1.80 +
1.81 + RegisterOrConstant ensure_simm13_or_reg(RegisterOrConstant src, Register temp) {
1.82 + if (is_simm13(src.constant_or_zero()))
1.83 + return src; // register or short constant
1.84 + guarantee(temp != noreg, "constant offset overflow");
1.85 + set(src.as_constant(), temp);
1.86 + return temp;
1.87 }
1.88
1.89 // --------------------------------------------------
1.90 @@ -2303,6 +2300,9 @@
1.91 void lcmp( Register Ra, Register Rb, Register Rresult);
1.92 #endif
1.93
1.94 + // Loading values by size and signed-ness
1.95 + void load_sized_value(Address src, Register dst, size_t size_in_bytes, bool is_signed);
1.96 +
1.97 void float_cmp( bool is_float, int unordered_result,
1.98 FloatRegister Fa, FloatRegister Fb,
1.99 Register Rresult);
1.100 @@ -2421,12 +2421,16 @@
1.101 void check_method_handle_type(Register mtype_reg, Register mh_reg,
1.102 Register temp_reg,
1.103 Label& wrong_method_type);
1.104 - void jump_to_method_handle_entry(Register mh_reg, Register temp_reg);
1.105 + void load_method_handle_vmslots(Register vmslots_reg, Register mh_reg,
1.106 + Register temp_reg);
1.107 + void jump_to_method_handle_entry(Register mh_reg, Register temp_reg, bool emit_delayed_nop = true);
1.108 // offset relative to Gargs of argument at tos[arg_slot].
1.109 // (arg_slot == 0 means the last argument, not the first).
1.110 RegisterOrConstant argument_offset(RegisterOrConstant arg_slot,
1.111 int extra_slot_offset = 0);
1.112 -
1.113 + // Address of Gargs and argument_offset.
1.114 + Address argument_address(RegisterOrConstant arg_slot,
1.115 + int extra_slot_offset = 0);
1.116
1.117 // Stack overflow checking
1.118
