src/share/vm/c1/c1_LIR.cpp

changeset 7598
ddce0b7cee93
parent 6688
15766b73dc1d
child 7854
e8260b6328fb
     1.1 --- a/src/share/vm/c1/c1_LIR.cpp	Fri Feb 20 17:05:39 2015 +0000
     1.2 +++ b/src/share/vm/c1/c1_LIR.cpp	Tue Feb 24 15:04:52 2015 -0500
     1.3 @@ -1,5 +1,5 @@
     1.4  /*
     1.5 - * Copyright (c) 2000, 2014, Oracle and/or its affiliates. All rights reserved.
     1.6 + * Copyright (c) 2000, 2015, Oracle and/or its affiliates. All rights reserved.
     1.7   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
     1.8   *
     1.9   * This code is free software; you can redistribute it and/or modify it
    1.10 @@ -142,16 +142,11 @@
    1.11  
    1.12  
    1.13  #ifndef PRODUCT
    1.14 -void LIR_Address::verify() const {
    1.15 +void LIR_Address::verify0() const {
    1.16  #if defined(SPARC) || defined(PPC)
    1.17    assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used");
    1.18    assert(disp() == 0 || index()->is_illegal(), "can't have both");
    1.19  #endif
    1.20 -#ifdef ARM
    1.21 -  assert(disp() == 0 || index()->is_illegal(), "can't have both");
    1.22 -  // Note: offsets higher than 4096 must not be rejected here. They can
    1.23 -  // be handled by the back-end or will be rejected if not.
    1.24 -#endif
    1.25  #ifdef _LP64
    1.26    assert(base()->is_cpu_register(), "wrong base operand");
    1.27    assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand");

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