1.1 --- a/src/cpu/x86/vm/vm_version_x86_64.cpp Tue Aug 26 15:49:40 2008 -0700
1.2 +++ b/src/cpu/x86/vm/vm_version_x86_64.cpp Wed Aug 27 00:21:55 2008 -0700
1.3 @@ -60,17 +60,17 @@
1.4 //
1.5 // rcx and rdx are first and second argument registers on windows
1.6
1.7 - __ pushq(rbp);
1.8 - __ movq(rbp, c_rarg0); // cpuid_info address
1.9 - __ pushq(rbx);
1.10 - __ pushq(rsi);
1.11 + __ push(rbp);
1.12 + __ mov(rbp, c_rarg0); // cpuid_info address
1.13 + __ push(rbx);
1.14 + __ push(rsi);
1.15
1.16 //
1.17 // we have a chip which supports the "cpuid" instruction
1.18 //
1.19 __ xorl(rax, rax);
1.20 __ cpuid();
1.21 - __ leaq(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
1.22 + __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
1.23 __ movl(Address(rsi, 0), rax);
1.24 __ movl(Address(rsi, 4), rbx);
1.25 __ movl(Address(rsi, 8), rcx);
1.26 @@ -85,13 +85,13 @@
1.27 __ movl(rax, 4);
1.28 __ xorl(rcx, rcx); // L1 cache
1.29 __ cpuid();
1.30 - __ pushq(rax);
1.31 + __ push(rax);
1.32 __ andl(rax, 0x1f); // Determine if valid cache parameters used
1.33 __ orl(rax, rax); // eax[4:0] == 0 indicates invalid cache
1.34 - __ popq(rax);
1.35 + __ pop(rax);
1.36 __ jccb(Assembler::equal, std_cpuid1);
1.37
1.38 - __ leaq(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset())));
1.39 + __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset())));
1.40 __ movl(Address(rsi, 0), rax);
1.41 __ movl(Address(rsi, 4), rbx);
1.42 __ movl(Address(rsi, 8), rcx);
1.43 @@ -103,7 +103,7 @@
1.44 __ bind(std_cpuid1);
1.45 __ movl(rax, 1);
1.46 __ cpuid();
1.47 - __ leaq(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
1.48 + __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
1.49 __ movl(Address(rsi, 0), rax);
1.50 __ movl(Address(rsi, 4), rbx);
1.51 __ movl(Address(rsi, 8), rcx);
1.52 @@ -122,7 +122,7 @@
1.53 //
1.54 __ movl(rax, 0x80000008);
1.55 __ cpuid();
1.56 - __ leaq(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset())));
1.57 + __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset())));
1.58 __ movl(Address(rsi, 0), rax);
1.59 __ movl(Address(rsi, 4), rbx);
1.60 __ movl(Address(rsi, 8), rcx);
1.61 @@ -134,7 +134,7 @@
1.62 __ bind(ext_cpuid5);
1.63 __ movl(rax, 0x80000005);
1.64 __ cpuid();
1.65 - __ leaq(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset())));
1.66 + __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset())));
1.67 __ movl(Address(rsi, 0), rax);
1.68 __ movl(Address(rsi, 4), rbx);
1.69 __ movl(Address(rsi, 8), rcx);
1.70 @@ -146,7 +146,7 @@
1.71 __ bind(ext_cpuid1);
1.72 __ movl(rax, 0x80000001);
1.73 __ cpuid();
1.74 - __ leaq(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset())));
1.75 + __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset())));
1.76 __ movl(Address(rsi, 0), rax);
1.77 __ movl(Address(rsi, 4), rbx);
1.78 __ movl(Address(rsi, 8), rcx);
1.79 @@ -156,9 +156,9 @@
1.80 // return
1.81 //
1.82 __ bind(done);
1.83 - __ popq(rsi);
1.84 - __ popq(rbx);
1.85 - __ popq(rbp);
1.86 + __ pop(rsi);
1.87 + __ pop(rbx);
1.88 + __ pop(rbp);
1.89 __ ret(0);
1.90
1.91 # undef __
