1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/src/cpu/x86/vm/assembler_x86.inline.hpp Wed Aug 27 00:21:55 2008 -0700
1.3 @@ -0,0 +1,87 @@
1.4 +/*
1.5 + * Copyright 1997-2005 Sun Microsystems, Inc. All Rights Reserved.
1.6 + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
1.7 + *
1.8 + * This code is free software; you can redistribute it and/or modify it
1.9 + * under the terms of the GNU General Public License version 2 only, as
1.10 + * published by the Free Software Foundation.
1.11 + *
1.12 + * This code is distributed in the hope that it will be useful, but WITHOUT
1.13 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1.14 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1.15 + * version 2 for more details (a copy is included in the LICENSE file that
1.16 + * accompanied this code).
1.17 + *
1.18 + * You should have received a copy of the GNU General Public License version
1.19 + * 2 along with this work; if not, write to the Free Software Foundation,
1.20 + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
1.21 + *
1.22 + * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
1.23 + * CA 95054 USA or visit www.sun.com if you need additional information or
1.24 + * have any questions.
1.25 + *
1.26 + */
1.27 +
1.28 +inline void MacroAssembler::pd_patch_instruction(address branch, address target) {
1.29 + unsigned char op = branch[0];
1.30 + assert(op == 0xE8 /* call */ ||
1.31 + op == 0xE9 /* jmp */ ||
1.32 + op == 0xEB /* short jmp */ ||
1.33 + (op & 0xF0) == 0x70 /* short jcc */ ||
1.34 + op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */,
1.35 + "Invalid opcode at patch point");
1.36 +
1.37 + if (op == 0xEB || (op & 0xF0) == 0x70) {
1.38 + // short offset operators (jmp and jcc)
1.39 + char* disp = (char*) &branch[1];
1.40 + int imm8 = target - (address) &disp[1];
1.41 + guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset");
1.42 + *disp = imm8;
1.43 + } else {
1.44 + int* disp = (int*) &branch[(op == 0x0F)? 2: 1];
1.45 + int imm32 = target - (address) &disp[1];
1.46 + *disp = imm32;
1.47 + }
1.48 +}
1.49 +
1.50 +#ifndef PRODUCT
1.51 +inline void MacroAssembler::pd_print_patched_instruction(address branch) {
1.52 + const char* s;
1.53 + unsigned char op = branch[0];
1.54 + if (op == 0xE8) {
1.55 + s = "call";
1.56 + } else if (op == 0xE9 || op == 0xEB) {
1.57 + s = "jmp";
1.58 + } else if ((op & 0xF0) == 0x70) {
1.59 + s = "jcc";
1.60 + } else if (op == 0x0F) {
1.61 + s = "jcc";
1.62 + } else {
1.63 + s = "????";
1.64 + }
1.65 + tty->print("%s (unresolved)", s);
1.66 +}
1.67 +#endif // ndef PRODUCT
1.68 +
1.69 +#ifndef _LP64
1.70 +inline int Assembler::prefix_and_encode(int reg_enc, bool byteinst) { return reg_enc; }
1.71 +inline int Assembler::prefixq_and_encode(int reg_enc) { return reg_enc; }
1.72 +
1.73 +inline int Assembler::prefix_and_encode(int dst_enc, int src_enc, bool byteinst) { return dst_enc << 3 | src_enc; }
1.74 +inline int Assembler::prefixq_and_encode(int dst_enc, int src_enc) { return dst_enc << 3 | src_enc; }
1.75 +
1.76 +inline void Assembler::prefix(Register reg) {}
1.77 +inline void Assembler::prefix(Address adr) {}
1.78 +inline void Assembler::prefixq(Address adr) {}
1.79 +
1.80 +inline void Assembler::prefix(Address adr, Register reg, bool byteinst) {}
1.81 +inline void Assembler::prefixq(Address adr, Register reg) {}
1.82 +
1.83 +inline void Assembler::prefix(Address adr, XMMRegister reg) {}
1.84 +#else
1.85 +inline void Assembler::emit_long64(jlong x) {
1.86 + *(jlong*) _code_pos = x;
1.87 + _code_pos += sizeof(jlong);
1.88 + code_section()->set_end(_code_pos);
1.89 +}
1.90 +#endif // _LP64
