1.1 --- a/src/cpu/x86/vm/assembler_x86.cpp Thu Dec 20 14:17:52 2012 -0800
1.2 +++ b/src/cpu/x86/vm/assembler_x86.cpp Thu Dec 20 18:53:44 2012 -0800
1.3 @@ -226,9 +226,9 @@
1.4 assert(isByte(op1) && isByte(op2), "wrong opcode");
1.5 assert(isByte(imm8), "not a byte");
1.6 assert((op1 & 0x01) == 0, "should be 8bit operation");
1.7 - emit_byte(op1);
1.8 - emit_byte(op2 | encode(dst));
1.9 - emit_byte(imm8);
1.10 + emit_int8(op1);
1.11 + emit_int8(op2 | encode(dst));
1.12 + emit_int8(imm8);
1.13 }
1.14
1.15
1.16 @@ -237,12 +237,12 @@
1.17 assert((op1 & 0x01) == 1, "should be 32bit operation");
1.18 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
1.19 if (is8bit(imm32)) {
1.20 - emit_byte(op1 | 0x02); // set sign bit
1.21 - emit_byte(op2 | encode(dst));
1.22 - emit_byte(imm32 & 0xFF);
1.23 + emit_int8(op1 | 0x02); // set sign bit
1.24 + emit_int8(op2 | encode(dst));
1.25 + emit_int8(imm32 & 0xFF);
1.26 } else {
1.27 - emit_byte(op1);
1.28 - emit_byte(op2 | encode(dst));
1.29 + emit_int8(op1);
1.30 + emit_int8(op2 | encode(dst));
1.31 emit_long(imm32);
1.32 }
1.33 }
1.34 @@ -252,8 +252,8 @@
1.35 assert(isByte(op1) && isByte(op2), "wrong opcode");
1.36 assert((op1 & 0x01) == 1, "should be 32bit operation");
1.37 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
1.38 - emit_byte(op1);
1.39 - emit_byte(op2 | encode(dst));
1.40 + emit_int8(op1);
1.41 + emit_int8(op2 | encode(dst));
1.42 emit_long(imm32);
1.43 }
1.44
1.45 @@ -262,11 +262,11 @@
1.46 assert((op1 & 0x01) == 1, "should be 32bit operation");
1.47 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
1.48 if (is8bit(imm32)) {
1.49 - emit_byte(op1 | 0x02); // set sign bit
1.50 + emit_int8(op1 | 0x02); // set sign bit
1.51 emit_operand(rm, adr, 1);
1.52 - emit_byte(imm32 & 0xFF);
1.53 + emit_int8(imm32 & 0xFF);
1.54 } else {
1.55 - emit_byte(op1);
1.56 + emit_int8(op1);
1.57 emit_operand(rm, adr, 4);
1.58 emit_long(imm32);
1.59 }
1.60 @@ -275,8 +275,8 @@
1.61
1.62 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
1.63 assert(isByte(op1) && isByte(op2), "wrong opcode");
1.64 - emit_byte(op1);
1.65 - emit_byte(op2 | encode(dst) << 3 | encode(src));
1.66 + emit_int8(op1);
1.67 + emit_int8(op2 | encode(dst) << 3 | encode(src));
1.68 }
1.69
1.70
1.71 @@ -301,21 +301,21 @@
1.72 // [base + index*scale]
1.73 // [00 reg 100][ss index base]
1.74 assert(index != rsp, "illegal addressing mode");
1.75 - emit_byte(0x04 | regenc);
1.76 - emit_byte(scale << 6 | indexenc | baseenc);
1.77 + emit_int8(0x04 | regenc);
1.78 + emit_int8(scale << 6 | indexenc | baseenc);
1.79 } else if (is8bit(disp) && rtype == relocInfo::none) {
1.80 // [base + index*scale + imm8]
1.81 // [01 reg 100][ss index base] imm8
1.82 assert(index != rsp, "illegal addressing mode");
1.83 - emit_byte(0x44 | regenc);
1.84 - emit_byte(scale << 6 | indexenc | baseenc);
1.85 - emit_byte(disp & 0xFF);
1.86 + emit_int8(0x44 | regenc);
1.87 + emit_int8(scale << 6 | indexenc | baseenc);
1.88 + emit_int8(disp & 0xFF);
1.89 } else {
1.90 // [base + index*scale + disp32]
1.91 // [10 reg 100][ss index base] disp32
1.92 assert(index != rsp, "illegal addressing mode");
1.93 - emit_byte(0x84 | regenc);
1.94 - emit_byte(scale << 6 | indexenc | baseenc);
1.95 + emit_int8(0x84 | regenc);
1.96 + emit_int8(scale << 6 | indexenc | baseenc);
1.97 emit_data(disp, rspec, disp32_operand);
1.98 }
1.99 } else if (base == rsp LP64_ONLY(|| base == r12)) {
1.100 @@ -323,19 +323,19 @@
1.101 if (disp == 0 && rtype == relocInfo::none) {
1.102 // [rsp]
1.103 // [00 reg 100][00 100 100]
1.104 - emit_byte(0x04 | regenc);
1.105 - emit_byte(0x24);
1.106 + emit_int8(0x04 | regenc);
1.107 + emit_int8(0x24);
1.108 } else if (is8bit(disp) && rtype == relocInfo::none) {
1.109 // [rsp + imm8]
1.110 // [01 reg 100][00 100 100] disp8
1.111 - emit_byte(0x44 | regenc);
1.112 - emit_byte(0x24);
1.113 - emit_byte(disp & 0xFF);
1.114 + emit_int8(0x44 | regenc);
1.115 + emit_int8(0x24);
1.116 + emit_int8(disp & 0xFF);
1.117 } else {
1.118 // [rsp + imm32]
1.119 // [10 reg 100][00 100 100] disp32
1.120 - emit_byte(0x84 | regenc);
1.121 - emit_byte(0x24);
1.122 + emit_int8(0x84 | regenc);
1.123 + emit_int8(0x24);
1.124 emit_data(disp, rspec, disp32_operand);
1.125 }
1.126 } else {
1.127 @@ -345,16 +345,16 @@
1.128 base != rbp LP64_ONLY(&& base != r13)) {
1.129 // [base]
1.130 // [00 reg base]
1.131 - emit_byte(0x00 | regenc | baseenc);
1.132 + emit_int8(0x00 | regenc | baseenc);
1.133 } else if (is8bit(disp) && rtype == relocInfo::none) {
1.134 // [base + disp8]
1.135 // [01 reg base] disp8
1.136 - emit_byte(0x40 | regenc | baseenc);
1.137 - emit_byte(disp & 0xFF);
1.138 + emit_int8(0x40 | regenc | baseenc);
1.139 + emit_int8(disp & 0xFF);
1.140 } else {
1.141 // [base + disp32]
1.142 // [10 reg base] disp32
1.143 - emit_byte(0x80 | regenc | baseenc);
1.144 + emit_int8(0x80 | regenc | baseenc);
1.145 emit_data(disp, rspec, disp32_operand);
1.146 }
1.147 }
1.148 @@ -364,14 +364,14 @@
1.149 // [index*scale + disp]
1.150 // [00 reg 100][ss index 101] disp32
1.151 assert(index != rsp, "illegal addressing mode");
1.152 - emit_byte(0x04 | regenc);
1.153 - emit_byte(scale << 6 | indexenc | 0x05);
1.154 + emit_int8(0x04 | regenc);
1.155 + emit_int8(scale << 6 | indexenc | 0x05);
1.156 emit_data(disp, rspec, disp32_operand);
1.157 } else if (rtype != relocInfo::none ) {
1.158 // [disp] (64bit) RIP-RELATIVE (32bit) abs
1.159 // [00 000 101] disp32
1.160
1.161 - emit_byte(0x05 | regenc);
1.162 + emit_int8(0x05 | regenc);
1.163 // Note that the RIP-rel. correction applies to the generated
1.164 // disp field, but _not_ to the target address in the rspec.
1.165
1.166 @@ -391,8 +391,8 @@
1.167 // 32bit never did this, did everything as the rip-rel/disp code above
1.168 // [disp] ABSOLUTE
1.169 // [00 reg 100][00 100 101] disp32
1.170 - emit_byte(0x04 | regenc);
1.171 - emit_byte(0x25);
1.172 + emit_int8(0x04 | regenc);
1.173 + emit_int8(0x25);
1.174 emit_data(disp, rspec, disp32_operand);
1.175 }
1.176 }
1.177 @@ -883,8 +883,8 @@
1.178 void Assembler::emit_farith(int b1, int b2, int i) {
1.179 assert(isByte(b1) && isByte(b2), "wrong opcode");
1.180 assert(0 <= i && i < 8, "illegal stack offset");
1.181 - emit_byte(b1);
1.182 - emit_byte(b2 + i);
1.183 + emit_int8(b1);
1.184 + emit_int8(b2 + i);
1.185 }
1.186
1.187
1.188 @@ -899,7 +899,7 @@
1.189 void Assembler::adcl(Address dst, Register src) {
1.190 InstructionMark im(this);
1.191 prefix(dst, src);
1.192 - emit_byte(0x11);
1.193 + emit_int8(0x11);
1.194 emit_operand(src, dst);
1.195 }
1.196
1.197 @@ -911,7 +911,7 @@
1.198 void Assembler::adcl(Register dst, Address src) {
1.199 InstructionMark im(this);
1.200 prefix(src, dst);
1.201 - emit_byte(0x13);
1.202 + emit_int8(0x13);
1.203 emit_operand(dst, src);
1.204 }
1.205
1.206 @@ -929,7 +929,7 @@
1.207 void Assembler::addl(Address dst, Register src) {
1.208 InstructionMark im(this);
1.209 prefix(dst, src);
1.210 - emit_byte(0x01);
1.211 + emit_int8(0x01);
1.212 emit_operand(src, dst);
1.213 }
1.214
1.215 @@ -941,7 +941,7 @@
1.216 void Assembler::addl(Register dst, Address src) {
1.217 InstructionMark im(this);
1.218 prefix(src, dst);
1.219 - emit_byte(0x03);
1.220 + emit_int8(0x03);
1.221 emit_operand(dst, src);
1.222 }
1.223
1.224 @@ -953,38 +953,40 @@
1.225 void Assembler::addr_nop_4() {
1.226 assert(UseAddressNop, "no CPU support");
1.227 // 4 bytes: NOP DWORD PTR [EAX+0]
1.228 - emit_byte(0x0F);
1.229 - emit_byte(0x1F);
1.230 - emit_byte(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
1.231 - emit_byte(0); // 8-bits offset (1 byte)
1.232 + emit_int8(0x0F);
1.233 + emit_int8(0x1F);
1.234 + emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
1.235 + emit_int8(0); // 8-bits offset (1 byte)
1.236 }
1.237
1.238 void Assembler::addr_nop_5() {
1.239 assert(UseAddressNop, "no CPU support");
1.240 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
1.241 - emit_byte(0x0F);
1.242 - emit_byte(0x1F);
1.243 - emit_byte(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
1.244 - emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1.245 - emit_byte(0); // 8-bits offset (1 byte)
1.246 + emit_int8(0x0F);
1.247 + emit_int8(0x1F);
1.248 + emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
1.249 + emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1.250 + emit_int8(0); // 8-bits offset (1 byte)
1.251 }
1.252
1.253 void Assembler::addr_nop_7() {
1.254 assert(UseAddressNop, "no CPU support");
1.255 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
1.256 - emit_byte(0x0F);
1.257 - emit_byte(0x1F);
1.258 - emit_byte(0x80); // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
1.259 + emit_int8(0x0F);
1.260 + emit_int8(0x1F);
1.261 + emit_int8((unsigned char)0x80);
1.262 + // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
1.263 emit_long(0); // 32-bits offset (4 bytes)
1.264 }
1.265
1.266 void Assembler::addr_nop_8() {
1.267 assert(UseAddressNop, "no CPU support");
1.268 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
1.269 - emit_byte(0x0F);
1.270 - emit_byte(0x1F);
1.271 - emit_byte(0x84); // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
1.272 - emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1.273 + emit_int8(0x0F);
1.274 + emit_int8(0x1F);
1.275 + emit_int8((unsigned char)0x84);
1.276 + // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
1.277 + emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1.278 emit_long(0); // 32-bits offset (4 bytes)
1.279 }
1.280
1.281 @@ -1012,67 +1014,67 @@
1.282 assert(VM_Version::supports_aes(), "");
1.283 InstructionMark im(this);
1.284 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1.285 - emit_byte(0xde);
1.286 + emit_int8((unsigned char)0xDE);
1.287 emit_operand(dst, src);
1.288 }
1.289
1.290 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
1.291 assert(VM_Version::supports_aes(), "");
1.292 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1.293 - emit_byte(0xde);
1.294 - emit_byte(0xC0 | encode);
1.295 + emit_int8((unsigned char)0xDE);
1.296 + emit_int8(0xC0 | encode);
1.297 }
1.298
1.299 void Assembler::aesdeclast(XMMRegister dst, Address src) {
1.300 assert(VM_Version::supports_aes(), "");
1.301 InstructionMark im(this);
1.302 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1.303 - emit_byte(0xdf);
1.304 + emit_int8((unsigned char)0xDF);
1.305 emit_operand(dst, src);
1.306 }
1.307
1.308 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
1.309 assert(VM_Version::supports_aes(), "");
1.310 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1.311 - emit_byte(0xdf);
1.312 - emit_byte(0xC0 | encode);
1.313 + emit_int8((unsigned char)0xDF);
1.314 + emit_int8((unsigned char)(0xC0 | encode));
1.315 }
1.316
1.317 void Assembler::aesenc(XMMRegister dst, Address src) {
1.318 assert(VM_Version::supports_aes(), "");
1.319 InstructionMark im(this);
1.320 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1.321 - emit_byte(0xdc);
1.322 + emit_int8((unsigned char)0xDC);
1.323 emit_operand(dst, src);
1.324 }
1.325
1.326 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1.327 assert(VM_Version::supports_aes(), "");
1.328 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1.329 - emit_byte(0xdc);
1.330 - emit_byte(0xC0 | encode);
1.331 + emit_int8((unsigned char)0xDC);
1.332 + emit_int8(0xC0 | encode);
1.333 }
1.334
1.335 void Assembler::aesenclast(XMMRegister dst, Address src) {
1.336 assert(VM_Version::supports_aes(), "");
1.337 InstructionMark im(this);
1.338 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1.339 - emit_byte(0xdd);
1.340 + emit_int8((unsigned char)0xDD);
1.341 emit_operand(dst, src);
1.342 }
1.343
1.344 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1.345 assert(VM_Version::supports_aes(), "");
1.346 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1.347 - emit_byte(0xdd);
1.348 - emit_byte(0xC0 | encode);
1.349 + emit_int8((unsigned char)0xDD);
1.350 + emit_int8((unsigned char)(0xC0 | encode));
1.351 }
1.352
1.353
1.354 void Assembler::andl(Address dst, int32_t imm32) {
1.355 InstructionMark im(this);
1.356 prefix(dst);
1.357 - emit_byte(0x81);
1.358 + emit_int8((unsigned char)0x81);
1.359 emit_operand(rsp, dst, 4);
1.360 emit_long(imm32);
1.361 }
1.362 @@ -1085,7 +1087,7 @@
1.363 void Assembler::andl(Register dst, Address src) {
1.364 InstructionMark im(this);
1.365 prefix(src, dst);
1.366 - emit_byte(0x23);
1.367 + emit_int8(0x23);
1.368 emit_operand(dst, src);
1.369 }
1.370
1.371 @@ -1096,23 +1098,23 @@
1.372
1.373 void Assembler::bsfl(Register dst, Register src) {
1.374 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1.375 - emit_byte(0x0F);
1.376 - emit_byte(0xBC);
1.377 - emit_byte(0xC0 | encode);
1.378 + emit_int8(0x0F);
1.379 + emit_int8((unsigned char)0xBC);
1.380 + emit_int8((unsigned char)(0xC0 | encode));
1.381 }
1.382
1.383 void Assembler::bsrl(Register dst, Register src) {
1.384 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT");
1.385 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1.386 - emit_byte(0x0F);
1.387 - emit_byte(0xBD);
1.388 - emit_byte(0xC0 | encode);
1.389 + emit_int8(0x0F);
1.390 + emit_int8((unsigned char)0xBD);
1.391 + emit_int8((unsigned char)(0xC0 | encode));
1.392 }
1.393
1.394 void Assembler::bswapl(Register reg) { // bswap
1.395 int encode = prefix_and_encode(reg->encoding());
1.396 - emit_byte(0x0F);
1.397 - emit_byte(0xC8 | encode);
1.398 + emit_int8(0x0F);
1.399 + emit_int8((unsigned char)(0xC8 | encode));
1.400 }
1.401
1.402 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1.403 @@ -1125,36 +1127,36 @@
1.404 assert(offs <= 0, "assembler error");
1.405 InstructionMark im(this);
1.406 // 1110 1000 #32-bit disp
1.407 - emit_byte(0xE8);
1.408 + emit_int8((unsigned char)0xE8);
1.409 emit_data(offs - long_size, rtype, operand);
1.410 } else {
1.411 InstructionMark im(this);
1.412 // 1110 1000 #32-bit disp
1.413 L.add_patch_at(code(), locator());
1.414
1.415 - emit_byte(0xE8);
1.416 + emit_int8((unsigned char)0xE8);
1.417 emit_data(int(0), rtype, operand);
1.418 }
1.419 }
1.420
1.421 void Assembler::call(Register dst) {
1.422 int encode = prefix_and_encode(dst->encoding());
1.423 - emit_byte(0xFF);
1.424 - emit_byte(0xD0 | encode);
1.425 + emit_int8((unsigned char)0xFF);
1.426 + emit_int8((unsigned char)(0xD0 | encode));
1.427 }
1.428
1.429
1.430 void Assembler::call(Address adr) {
1.431 InstructionMark im(this);
1.432 prefix(adr);
1.433 - emit_byte(0xFF);
1.434 + emit_int8((unsigned char)0xFF);
1.435 emit_operand(rdx, adr);
1.436 }
1.437
1.438 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1.439 assert(entry != NULL, "call most probably wrong");
1.440 InstructionMark im(this);
1.441 - emit_byte(0xE8);
1.442 + emit_int8((unsigned char)0xE8);
1.443 intptr_t disp = entry - (pc() + sizeof(int32_t));
1.444 assert(is_simm32(disp), "must be 32bit offset (call2)");
1.445 // Technically, should use call32_operand, but this format is
1.446 @@ -1165,42 +1167,42 @@
1.447 }
1.448
1.449 void Assembler::cdql() {
1.450 - emit_byte(0x99);
1.451 + emit_int8((unsigned char)0x99);
1.452 }
1.453
1.454 void Assembler::cld() {
1.455 - emit_byte(0xfc);
1.456 + emit_int8((unsigned char)0xFC);
1.457 }
1.458
1.459 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1.460 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1.461 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1.462 - emit_byte(0x0F);
1.463 - emit_byte(0x40 | cc);
1.464 - emit_byte(0xC0 | encode);
1.465 + emit_int8(0x0F);
1.466 + emit_int8(0x40 | cc);
1.467 + emit_int8((unsigned char)(0xC0 | encode));
1.468 }
1.469
1.470
1.471 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1.472 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1.473 prefix(src, dst);
1.474 - emit_byte(0x0F);
1.475 - emit_byte(0x40 | cc);
1.476 + emit_int8(0x0F);
1.477 + emit_int8(0x40 | cc);
1.478 emit_operand(dst, src);
1.479 }
1.480
1.481 void Assembler::cmpb(Address dst, int imm8) {
1.482 InstructionMark im(this);
1.483 prefix(dst);
1.484 - emit_byte(0x80);
1.485 + emit_int8((unsigned char)0x80);
1.486 emit_operand(rdi, dst, 1);
1.487 - emit_byte(imm8);
1.488 + emit_int8(imm8);
1.489 }
1.490
1.491 void Assembler::cmpl(Address dst, int32_t imm32) {
1.492 InstructionMark im(this);
1.493 prefix(dst);
1.494 - emit_byte(0x81);
1.495 + emit_int8((unsigned char)0x81);
1.496 emit_operand(rdi, dst, 4);
1.497 emit_long(imm32);
1.498 }
1.499 @@ -1219,15 +1221,15 @@
1.500 void Assembler::cmpl(Register dst, Address src) {
1.501 InstructionMark im(this);
1.502 prefix(src, dst);
1.503 - emit_byte(0x3B);
1.504 + emit_int8((unsigned char)0x3B);
1.505 emit_operand(dst, src);
1.506 }
1.507
1.508 void Assembler::cmpw(Address dst, int imm16) {
1.509 InstructionMark im(this);
1.510 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1.511 - emit_byte(0x66);
1.512 - emit_byte(0x81);
1.513 + emit_int8(0x66);
1.514 + emit_int8((unsigned char)0x81);
1.515 emit_operand(rdi, dst, 2);
1.516 emit_int16(imm16);
1.517 }
1.518 @@ -1238,8 +1240,8 @@
1.519 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1.520 InstructionMark im(this);
1.521 prefix(adr, reg);
1.522 - emit_byte(0x0F);
1.523 - emit_byte(0xB1);
1.524 + emit_int8(0x0F);
1.525 + emit_int8((unsigned char)0xB1);
1.526 emit_operand(reg, adr);
1.527 }
1.528
1.529 @@ -1266,8 +1268,8 @@
1.530 }
1.531
1.532 void Assembler::cpuid() {
1.533 - emit_byte(0x0F);
1.534 - emit_byte(0xA2);
1.535 + emit_int8(0x0F);
1.536 + emit_int8((unsigned char)0xA2);
1.537 }
1.538
1.539 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1.540 @@ -1293,8 +1295,8 @@
1.541 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1.542 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.543 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
1.544 - emit_byte(0x2A);
1.545 - emit_byte(0xC0 | encode);
1.546 + emit_int8(0x2A);
1.547 + emit_int8((unsigned char)(0xC0 | encode));
1.548 }
1.549
1.550 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1.551 @@ -1305,8 +1307,8 @@
1.552 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1.553 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1.554 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
1.555 - emit_byte(0x2A);
1.556 - emit_byte(0xC0 | encode);
1.557 + emit_int8(0x2A);
1.558 + emit_int8((unsigned char)(0xC0 | encode));
1.559 }
1.560
1.561 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1.562 @@ -1328,22 +1330,22 @@
1.563 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1.564 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.565 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2);
1.566 - emit_byte(0x2C);
1.567 - emit_byte(0xC0 | encode);
1.568 + emit_int8(0x2C);
1.569 + emit_int8((unsigned char)(0xC0 | encode));
1.570 }
1.571
1.572 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1.573 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1.574 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3);
1.575 - emit_byte(0x2C);
1.576 - emit_byte(0xC0 | encode);
1.577 + emit_int8(0x2C);
1.578 + emit_int8((unsigned char)(0xC0 | encode));
1.579 }
1.580
1.581 void Assembler::decl(Address dst) {
1.582 // Don't use it directly. Use MacroAssembler::decrement() instead.
1.583 InstructionMark im(this);
1.584 prefix(dst);
1.585 - emit_byte(0xFF);
1.586 + emit_int8((unsigned char)0xFF);
1.587 emit_operand(rcx, dst);
1.588 }
1.589
1.590 @@ -1369,43 +1371,43 @@
1.591
1.592 void Assembler::emms() {
1.593 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1.594 - emit_byte(0x0F);
1.595 - emit_byte(0x77);
1.596 + emit_int8(0x0F);
1.597 + emit_int8(0x77);
1.598 }
1.599
1.600 void Assembler::hlt() {
1.601 - emit_byte(0xF4);
1.602 + emit_int8((unsigned char)0xF4);
1.603 }
1.604
1.605 void Assembler::idivl(Register src) {
1.606 int encode = prefix_and_encode(src->encoding());
1.607 - emit_byte(0xF7);
1.608 - emit_byte(0xF8 | encode);
1.609 + emit_int8((unsigned char)0xF7);
1.610 + emit_int8((unsigned char)(0xF8 | encode));
1.611 }
1.612
1.613 void Assembler::divl(Register src) { // Unsigned
1.614 int encode = prefix_and_encode(src->encoding());
1.615 - emit_byte(0xF7);
1.616 - emit_byte(0xF0 | encode);
1.617 + emit_int8((unsigned char)0xF7);
1.618 + emit_int8((unsigned char)(0xF0 | encode));
1.619 }
1.620
1.621 void Assembler::imull(Register dst, Register src) {
1.622 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1.623 - emit_byte(0x0F);
1.624 - emit_byte(0xAF);
1.625 - emit_byte(0xC0 | encode);
1.626 + emit_int8(0x0F);
1.627 + emit_int8((unsigned char)0xAF);
1.628 + emit_int8((unsigned char)(0xC0 | encode));
1.629 }
1.630
1.631
1.632 void Assembler::imull(Register dst, Register src, int value) {
1.633 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1.634 if (is8bit(value)) {
1.635 - emit_byte(0x6B);
1.636 - emit_byte(0xC0 | encode);
1.637 - emit_byte(value & 0xFF);
1.638 + emit_int8(0x6B);
1.639 + emit_int8((unsigned char)(0xC0 | encode));
1.640 + emit_int8(value & 0xFF);
1.641 } else {
1.642 - emit_byte(0x69);
1.643 - emit_byte(0xC0 | encode);
1.644 + emit_int8(0x69);
1.645 + emit_int8((unsigned char)(0xC0 | encode));
1.646 emit_long(value);
1.647 }
1.648 }
1.649 @@ -1414,7 +1416,7 @@
1.650 // Don't use it directly. Use MacroAssembler::increment() instead.
1.651 InstructionMark im(this);
1.652 prefix(dst);
1.653 - emit_byte(0xFF);
1.654 + emit_int8((unsigned char)0xFF);
1.655 emit_operand(rax, dst);
1.656 }
1.657
1.658 @@ -1430,14 +1432,14 @@
1.659 intptr_t offs = (intptr_t)dst - (intptr_t)pc();
1.660 if (maybe_short && is8bit(offs - short_size)) {
1.661 // 0111 tttn #8-bit disp
1.662 - emit_byte(0x70 | cc);
1.663 - emit_byte((offs - short_size) & 0xFF);
1.664 + emit_int8(0x70 | cc);
1.665 + emit_int8((offs - short_size) & 0xFF);
1.666 } else {
1.667 // 0000 1111 1000 tttn #32-bit disp
1.668 assert(is_simm32(offs - long_size),
1.669 "must be 32bit offset (call4)");
1.670 - emit_byte(0x0F);
1.671 - emit_byte(0x80 | cc);
1.672 + emit_int8(0x0F);
1.673 + emit_int8((unsigned char)(0x80 | cc));
1.674 emit_long(offs - long_size);
1.675 }
1.676 } else {
1.677 @@ -1446,8 +1448,8 @@
1.678 // Note: use jccb() if label to be bound is very close to get
1.679 // an 8-bit displacement
1.680 L.add_patch_at(code(), locator());
1.681 - emit_byte(0x0F);
1.682 - emit_byte(0x80 | cc);
1.683 + emit_int8(0x0F);
1.684 + emit_int8((unsigned char)(0x80 | cc));
1.685 emit_long(0);
1.686 }
1.687 }
1.688 @@ -1466,20 +1468,20 @@
1.689 #endif
1.690 intptr_t offs = (intptr_t)entry - (intptr_t)pc();
1.691 // 0111 tttn #8-bit disp
1.692 - emit_byte(0x70 | cc);
1.693 - emit_byte((offs - short_size) & 0xFF);
1.694 + emit_int8(0x70 | cc);
1.695 + emit_int8((offs - short_size) & 0xFF);
1.696 } else {
1.697 InstructionMark im(this);
1.698 L.add_patch_at(code(), locator());
1.699 - emit_byte(0x70 | cc);
1.700 - emit_byte(0);
1.701 + emit_int8(0x70 | cc);
1.702 + emit_int8(0);
1.703 }
1.704 }
1.705
1.706 void Assembler::jmp(Address adr) {
1.707 InstructionMark im(this);
1.708 prefix(adr);
1.709 - emit_byte(0xFF);
1.710 + emit_int8((unsigned char)0xFF);
1.711 emit_operand(rsp, adr);
1.712 }
1.713
1.714 @@ -1492,10 +1494,10 @@
1.715 const int long_size = 5;
1.716 intptr_t offs = entry - pc();
1.717 if (maybe_short && is8bit(offs - short_size)) {
1.718 - emit_byte(0xEB);
1.719 - emit_byte((offs - short_size) & 0xFF);
1.720 + emit_int8((unsigned char)0xEB);
1.721 + emit_int8((offs - short_size) & 0xFF);
1.722 } else {
1.723 - emit_byte(0xE9);
1.724 + emit_int8((unsigned char)0xE9);
1.725 emit_long(offs - long_size);
1.726 }
1.727 } else {
1.728 @@ -1505,20 +1507,20 @@
1.729 // force an 8-bit displacement.
1.730 InstructionMark im(this);
1.731 L.add_patch_at(code(), locator());
1.732 - emit_byte(0xE9);
1.733 + emit_int8((unsigned char)0xE9);
1.734 emit_long(0);
1.735 }
1.736 }
1.737
1.738 void Assembler::jmp(Register entry) {
1.739 int encode = prefix_and_encode(entry->encoding());
1.740 - emit_byte(0xFF);
1.741 - emit_byte(0xE0 | encode);
1.742 + emit_int8((unsigned char)0xFF);
1.743 + emit_int8((unsigned char)(0xE0 | encode));
1.744 }
1.745
1.746 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
1.747 InstructionMark im(this);
1.748 - emit_byte(0xE9);
1.749 + emit_int8((unsigned char)0xE9);
1.750 assert(dest != NULL, "must have a target");
1.751 intptr_t disp = dest - (pc() + sizeof(int32_t));
1.752 assert(is_simm32(disp), "must be 32bit offset (jmp)");
1.753 @@ -1539,13 +1541,13 @@
1.754 assert(is8bit(dist), "Dispacement too large for a short jmp");
1.755 #endif
1.756 intptr_t offs = entry - pc();
1.757 - emit_byte(0xEB);
1.758 - emit_byte((offs - short_size) & 0xFF);
1.759 + emit_int8((unsigned char)0xEB);
1.760 + emit_int8((offs - short_size) & 0xFF);
1.761 } else {
1.762 InstructionMark im(this);
1.763 L.add_patch_at(code(), locator());
1.764 - emit_byte(0xEB);
1.765 - emit_byte(0);
1.766 + emit_int8((unsigned char)0xEB);
1.767 + emit_int8(0);
1.768 }
1.769 }
1.770
1.771 @@ -1553,46 +1555,46 @@
1.772 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1.773 InstructionMark im(this);
1.774 prefix(src);
1.775 - emit_byte(0x0F);
1.776 - emit_byte(0xAE);
1.777 + emit_int8(0x0F);
1.778 + emit_int8((unsigned char)0xAE);
1.779 emit_operand(as_Register(2), src);
1.780 }
1.781
1.782 void Assembler::leal(Register dst, Address src) {
1.783 InstructionMark im(this);
1.784 #ifdef _LP64
1.785 - emit_byte(0x67); // addr32
1.786 + emit_int8(0x67); // addr32
1.787 prefix(src, dst);
1.788 #endif // LP64
1.789 - emit_byte(0x8D);
1.790 + emit_int8((unsigned char)0x8D);
1.791 emit_operand(dst, src);
1.792 }
1.793
1.794 void Assembler::lfence() {
1.795 - emit_byte(0x0F);
1.796 - emit_byte(0xAE);
1.797 - emit_byte(0xE8);
1.798 + emit_int8(0x0F);
1.799 + emit_int8((unsigned char)0xAE);
1.800 + emit_int8((unsigned char)0xE8);
1.801 }
1.802
1.803 void Assembler::lock() {
1.804 - emit_byte(0xF0);
1.805 + emit_int8((unsigned char)0xF0);
1.806 }
1.807
1.808 void Assembler::lzcntl(Register dst, Register src) {
1.809 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
1.810 - emit_byte(0xF3);
1.811 + emit_int8((unsigned char)0xF3);
1.812 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1.813 - emit_byte(0x0F);
1.814 - emit_byte(0xBD);
1.815 - emit_byte(0xC0 | encode);
1.816 + emit_int8(0x0F);
1.817 + emit_int8((unsigned char)0xBD);
1.818 + emit_int8((unsigned char)(0xC0 | encode));
1.819 }
1.820
1.821 // Emit mfence instruction
1.822 void Assembler::mfence() {
1.823 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
1.824 - emit_byte( 0x0F );
1.825 - emit_byte( 0xAE );
1.826 - emit_byte( 0xF0 );
1.827 + emit_int8(0x0F);
1.828 + emit_int8((unsigned char)0xAE);
1.829 + emit_int8((unsigned char)0xF0);
1.830 }
1.831
1.832 void Assembler::mov(Register dst, Register src) {
1.833 @@ -1612,15 +1614,15 @@
1.834 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
1.835 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1.836 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE);
1.837 - emit_byte(0x16);
1.838 - emit_byte(0xC0 | encode);
1.839 + emit_int8(0x16);
1.840 + emit_int8((unsigned char)(0xC0 | encode));
1.841 }
1.842
1.843 void Assembler::movb(Register dst, Address src) {
1.844 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
1.845 InstructionMark im(this);
1.846 prefix(src, dst, true);
1.847 - emit_byte(0x8A);
1.848 + emit_int8((unsigned char)0x8A);
1.849 emit_operand(dst, src);
1.850 }
1.851
1.852 @@ -1628,9 +1630,9 @@
1.853 void Assembler::movb(Address dst, int imm8) {
1.854 InstructionMark im(this);
1.855 prefix(dst);
1.856 - emit_byte(0xC6);
1.857 + emit_int8((unsigned char)0xC6);
1.858 emit_operand(rax, dst, 1);
1.859 - emit_byte(imm8);
1.860 + emit_int8(imm8);
1.861 }
1.862
1.863
1.864 @@ -1638,30 +1640,30 @@
1.865 assert(src->has_byte_register(), "must have byte register");
1.866 InstructionMark im(this);
1.867 prefix(dst, src, true);
1.868 - emit_byte(0x88);
1.869 + emit_int8((unsigned char)0x88);
1.870 emit_operand(src, dst);
1.871 }
1.872
1.873 void Assembler::movdl(XMMRegister dst, Register src) {
1.874 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.875 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66);
1.876 - emit_byte(0x6E);
1.877 - emit_byte(0xC0 | encode);
1.878 + emit_int8(0x6E);
1.879 + emit_int8((unsigned char)(0xC0 | encode));
1.880 }
1.881
1.882 void Assembler::movdl(Register dst, XMMRegister src) {
1.883 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.884 // swap src/dst to get correct prefix
1.885 int encode = simd_prefix_and_encode(src, dst, VEX_SIMD_66);
1.886 - emit_byte(0x7E);
1.887 - emit_byte(0xC0 | encode);
1.888 + emit_int8(0x7E);
1.889 + emit_int8((unsigned char)(0xC0 | encode));
1.890 }
1.891
1.892 void Assembler::movdl(XMMRegister dst, Address src) {
1.893 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.894 InstructionMark im(this);
1.895 simd_prefix(dst, src, VEX_SIMD_66);
1.896 - emit_byte(0x6E);
1.897 + emit_int8(0x6E);
1.898 emit_operand(dst, src);
1.899 }
1.900
1.901 @@ -1669,7 +1671,7 @@
1.902 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.903 InstructionMark im(this);
1.904 simd_prefix(dst, src, VEX_SIMD_66);
1.905 - emit_byte(0x7E);
1.906 + emit_int8(0x7E);
1.907 emit_operand(src, dst);
1.908 }
1.909
1.910 @@ -1692,7 +1694,7 @@
1.911 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.912 InstructionMark im(this);
1.913 simd_prefix(dst, src, VEX_SIMD_F3);
1.914 - emit_byte(0x7F);
1.915 + emit_int8(0x7F);
1.916 emit_operand(src, dst);
1.917 }
1.918
1.919 @@ -1701,8 +1703,8 @@
1.920 assert(UseAVX, "");
1.921 bool vector256 = true;
1.922 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, vector256);
1.923 - emit_byte(0x6F);
1.924 - emit_byte(0xC0 | encode);
1.925 + emit_int8(0x6F);
1.926 + emit_int8((unsigned char)(0xC0 | encode));
1.927 }
1.928
1.929 void Assembler::vmovdqu(XMMRegister dst, Address src) {
1.930 @@ -1710,7 +1712,7 @@
1.931 InstructionMark im(this);
1.932 bool vector256 = true;
1.933 vex_prefix(dst, xnoreg, src, VEX_SIMD_F3, vector256);
1.934 - emit_byte(0x6F);
1.935 + emit_int8(0x6F);
1.936 emit_operand(dst, src);
1.937 }
1.938
1.939 @@ -1721,7 +1723,7 @@
1.940 // swap src<->dst for encoding
1.941 assert(src != xnoreg, "sanity");
1.942 vex_prefix(src, xnoreg, dst, VEX_SIMD_F3, vector256);
1.943 - emit_byte(0x7F);
1.944 + emit_int8(0x7F);
1.945 emit_operand(src, dst);
1.946 }
1.947
1.948 @@ -1729,27 +1731,27 @@
1.949
1.950 void Assembler::movl(Register dst, int32_t imm32) {
1.951 int encode = prefix_and_encode(dst->encoding());
1.952 - emit_byte(0xB8 | encode);
1.953 + emit_int8((unsigned char)(0xB8 | encode));
1.954 emit_long(imm32);
1.955 }
1.956
1.957 void Assembler::movl(Register dst, Register src) {
1.958 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1.959 - emit_byte(0x8B);
1.960 - emit_byte(0xC0 | encode);
1.961 + emit_int8((unsigned char)0x8B);
1.962 + emit_int8((unsigned char)(0xC0 | encode));
1.963 }
1.964
1.965 void Assembler::movl(Register dst, Address src) {
1.966 InstructionMark im(this);
1.967 prefix(src, dst);
1.968 - emit_byte(0x8B);
1.969 + emit_int8((unsigned char)0x8B);
1.970 emit_operand(dst, src);
1.971 }
1.972
1.973 void Assembler::movl(Address dst, int32_t imm32) {
1.974 InstructionMark im(this);
1.975 prefix(dst);
1.976 - emit_byte(0xC7);
1.977 + emit_int8((unsigned char)0xC7);
1.978 emit_operand(rax, dst, 4);
1.979 emit_long(imm32);
1.980 }
1.981 @@ -1757,7 +1759,7 @@
1.982 void Assembler::movl(Address dst, Register src) {
1.983 InstructionMark im(this);
1.984 prefix(dst, src);
1.985 - emit_byte(0x89);
1.986 + emit_int8((unsigned char)0x89);
1.987 emit_operand(src, dst);
1.988 }
1.989
1.990 @@ -1771,15 +1773,15 @@
1.991
1.992 void Assembler::movq( MMXRegister dst, Address src ) {
1.993 assert( VM_Version::supports_mmx(), "" );
1.994 - emit_byte(0x0F);
1.995 - emit_byte(0x6F);
1.996 + emit_int8(0x0F);
1.997 + emit_int8(0x6F);
1.998 emit_operand(dst, src);
1.999 }
1.1000
1.1001 void Assembler::movq( Address dst, MMXRegister src ) {
1.1002 assert( VM_Version::supports_mmx(), "" );
1.1003 - emit_byte(0x0F);
1.1004 - emit_byte(0x7F);
1.1005 + emit_int8(0x0F);
1.1006 + emit_int8(0x7F);
1.1007 // workaround gcc (3.2.1-7a) bug
1.1008 // In that version of gcc with only an emit_operand(MMX, Address)
1.1009 // gcc will tail jump and try and reverse the parameters completely
1.1010 @@ -1793,7 +1795,7 @@
1.1011 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.1012 InstructionMark im(this);
1.1013 simd_prefix(dst, src, VEX_SIMD_F3);
1.1014 - emit_byte(0x7E);
1.1015 + emit_int8(0x7E);
1.1016 emit_operand(dst, src);
1.1017 }
1.1018
1.1019 @@ -1801,24 +1803,24 @@
1.1020 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.1021 InstructionMark im(this);
1.1022 simd_prefix(dst, src, VEX_SIMD_66);
1.1023 - emit_byte(0xD6);
1.1024 + emit_int8((unsigned char)0xD6);
1.1025 emit_operand(src, dst);
1.1026 }
1.1027
1.1028 void Assembler::movsbl(Register dst, Address src) { // movsxb
1.1029 InstructionMark im(this);
1.1030 prefix(src, dst);
1.1031 - emit_byte(0x0F);
1.1032 - emit_byte(0xBE);
1.1033 + emit_int8(0x0F);
1.1034 + emit_int8((unsigned char)0xBE);
1.1035 emit_operand(dst, src);
1.1036 }
1.1037
1.1038 void Assembler::movsbl(Register dst, Register src) { // movsxb
1.1039 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
1.1040 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
1.1041 - emit_byte(0x0F);
1.1042 - emit_byte(0xBE);
1.1043 - emit_byte(0xC0 | encode);
1.1044 + emit_int8(0x0F);
1.1045 + emit_int8((unsigned char)0xBE);
1.1046 + emit_int8((unsigned char)(0xC0 | encode));
1.1047 }
1.1048
1.1049 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
1.1050 @@ -1835,7 +1837,7 @@
1.1051 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.1052 InstructionMark im(this);
1.1053 simd_prefix(dst, src, VEX_SIMD_F2);
1.1054 - emit_byte(0x11);
1.1055 + emit_int8(0x11);
1.1056 emit_operand(src, dst);
1.1057 }
1.1058
1.1059 @@ -1853,93 +1855,93 @@
1.1060 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1.1061 InstructionMark im(this);
1.1062 simd_prefix(dst, src, VEX_SIMD_F3);
1.1063 - emit_byte(0x11);
1.1064 + emit_int8(0x11);
1.1065 emit_operand(src, dst);
1.1066 }
1.1067
1.1068 void Assembler::movswl(Register dst, Address src) { // movsxw
1.1069 InstructionMark im(this);
1.1070 prefix(src, dst);
1.1071 - emit_byte(0x0F);
1.1072 - emit_byte(0xBF);
1.1073 + emit_int8(0x0F);
1.1074 + emit_int8((unsigned char)0xBF);
1.1075 emit_operand(dst, src);
1.1076 }
1.1077
1.1078 void Assembler::movswl(Register dst, Register src) { // movsxw
1.1079 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1.1080 - emit_byte(0x0F);
1.1081 - emit_byte(0xBF);
1.1082 - emit_byte(0xC0 | encode);
1.1083 + emit_int8(0x0F);
1.1084 + emit_int8((unsigned char)0xBF);
1.1085 + emit_int8((unsigned char)(0xC0 | encode));
1.1086 }
1.1087
1.1088 void Assembler::movw(Address dst, int imm16) {
1.1089 InstructionMark im(this);
1.1090
1.1091 - emit_byte(0x66); // switch to 16-bit mode
1.1092 + emit_int8(0x66); // switch to 16-bit mode
1.1093 prefix(dst);
1.1094 - emit_byte(0xC7);
1.1095 + emit_int8((unsigned char)0xC7);
1.1096 emit_operand(rax, dst, 2);
1.1097 emit_int16(imm16);
1.1098 }
1.1099
1.1100 void Assembler::movw(Register dst, Address src) {
1.1101 InstructionMark im(this);
1.1102 - emit_byte(0x66);
1.1103 + emit_int8(0x66);
1.1104 prefix(src, dst);
1.1105 - emit_byte(0x8B);
1.1106 + emit_int8((unsigned char)0x8B);
1.1107 emit_operand(dst, src);
1.1108 }
1.1109
1.1110 void Assembler::movw(Address dst, Register src) {
1.1111 InstructionMark im(this);
1.1112 - emit_byte(0x66);
1.1113 + emit_int8(0x66);
1.1114 prefix(dst, src);
1.1115 - emit_byte(0x89);
1.1116 + emit_int8((unsigned char)0x89);
1.1117 emit_operand(src, dst);
1.1118 }
1.1119
1.1120 void Assembler::movzbl(Register dst, Address src) { // movzxb
1.1121 InstructionMark im(this);
1.1122 prefix(src, dst);
1.1123 - emit_byte(0x0F);
1.1124 - emit_byte(0xB6);
1.1125 + emit_int8(0x0F);
1.1126 + emit_int8((unsigned char)0xB6);
1.1127 emit_operand(dst, src);
1.1128 }
1.1129
1.1130 void Assembler::movzbl(Register dst, Register src) { // movzxb
1.1131 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
1.1132 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
1.1133 - emit_byte(0x0F);
1.1134 - emit_byte(0xB6);
1.1135 - emit_byte(0xC0 | encode);
1.1136 + emit_int8(0x0F);
1.1137 + emit_int8((unsigned char)0xB6);
1.1138 + emit_int8(0xC0 | encode);
1.1139 }
1.1140
1.1141 void Assembler::movzwl(Register dst, Address src) { // movzxw
1.1142 InstructionMark im(this);
1.1143 prefix(src, dst);
1.1144 - emit_byte(0x0F);
1.1145 - emit_byte(0xB7);
1.1146 + emit_int8(0x0F);
1.1147 + emit_int8((unsigned char)0xB7);
1.1148 emit_operand(dst, src);
1.1149 }
1.1150
1.1151 void Assembler::movzwl(Register dst, Register src) { // movzxw
1.1152 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1.1153 - emit_byte(0x0F);
1.1154 - emit_byte(0xB7);
1.1155 - emit_byte(0xC0 | encode);
1.1156 + emit_int8(0x0F);
1.1157 + emit_int8((unsigned char)0xB7);
1.1158 + emit_int8(0xC0 | encode);
1.1159 }
1.1160
1.1161 void Assembler::mull(Address src) {
1.1162 InstructionMark im(this);
1.1163 prefix(src);
1.1164 - emit_byte(0xF7);
1.1165 + emit_int8((unsigned char)0xF7);
1.1166 emit_operand(rsp, src);
1.1167 }
1.1168
1.1169 void Assembler::mull(Register src) {
1.1170 int encode = prefix_and_encode(src->encoding());
1.1171 - emit_byte(0xF7);
1.1172 - emit_byte(0xE0 | encode);
1.1173 + emit_int8((unsigned char)0xF7);
1.1174 + emit_int8((unsigned char)(0xE0 | encode));
1.1175 }
1.1176
1.1177 void Assembler::mulsd(XMMRegister dst, Address src) {
1.1178 @@ -1964,8 +1966,8 @@
1.1179
1.1180 void Assembler::negl(Register dst) {
1.1181 int encode = prefix_and_encode(dst->encoding());
1.1182 - emit_byte(0xF7);
1.1183 - emit_byte(0xD8 | encode);
1.1184 + emit_int8((unsigned char)0xF7);
1.1185 + emit_int8((unsigned char)(0xD8 | encode));
1.1186 }
1.1187
1.1188 void Assembler::nop(int i) {
1.1189 @@ -1976,7 +1978,7 @@
1.1190 // speed is not an issue so simply use the single byte traditional nop
1.1191 // to do alignment.
1.1192
1.1193 - for (; i > 0 ; i--) emit_byte(0x90);
1.1194 + for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
1.1195 return;
1.1196
1.1197 #endif // ASSERT
1.1198 @@ -2006,33 +2008,35 @@
1.1199 while(i >= 15) {
1.1200 // For Intel don't generate consecutive addess nops (mix with regular nops)
1.1201 i -= 15;
1.1202 - emit_byte(0x66); // size prefix
1.1203 - emit_byte(0x66); // size prefix
1.1204 - emit_byte(0x66); // size prefix
1.1205 + emit_int8(0x66); // size prefix
1.1206 + emit_int8(0x66); // size prefix
1.1207 + emit_int8(0x66); // size prefix
1.1208 addr_nop_8();
1.1209 - emit_byte(0x66); // size prefix
1.1210 - emit_byte(0x66); // size prefix
1.1211 - emit_byte(0x66); // size prefix
1.1212 - emit_byte(0x90); // nop
1.1213 + emit_int8(0x66); // size prefix
1.1214 + emit_int8(0x66); // size prefix
1.1215 + emit_int8(0x66); // size prefix
1.1216 + emit_int8((unsigned char)0x90);
1.1217 + // nop
1.1218 }
1.1219 switch (i) {
1.1220 case 14:
1.1221 - emit_byte(0x66); // size prefix
1.1222 + emit_int8(0x66); // size prefix
1.1223 case 13:
1.1224 - emit_byte(0x66); // size prefix
1.1225 + emit_int8(0x66); // size prefix
1.1226 case 12:
1.1227 addr_nop_8();
1.1228 - emit_byte(0x66); // size prefix
1.1229 - emit_byte(0x66); // size prefix
1.1230 - emit_byte(0x66); // size prefix
1.1231 - emit_byte(0x90); // nop
1.1232 + emit_int8(0x66); // size prefix
1.1233 + emit_int8(0x66); // size prefix
1.1234 + emit_int8(0x66); // size prefix
1.1235 + emit_int8((unsigned char)0x90);
1.1236 + // nop
1.1237 break;
1.1238 case 11:
1.1239 - emit_byte(0x66); // size prefix
1.1240 + emit_int8(0x66); // size prefix
1.1241 case 10:
1.1242 - emit_byte(0x66); // size prefix
1.1243 + emit_int8(0x66); // size prefix
1.1244 case 9:
1.1245 - emit_byte(0x66); // size prefix
1.1246 + emit_int8(0x66); // size prefix
1.1247 case 8:
1.1248 addr_nop_8();
1.1249 break;
1.1250 @@ -2040,7 +2044,7 @@
1.1251 addr_nop_7();
1.1252 break;
1.1253 case 6:
1.1254 - emit_byte(0x66); // size prefix
1.1255 + emit_int8(0x66); // size prefix
1.1256 case 5:
1.1257 addr_nop_5();
1.1258 break;
1.1259 @@ -2049,11 +2053,12 @@
1.1260 break;
1.1261 case 3:
1.1262 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
1.1263 - emit_byte(0x66); // size prefix
1.1264 + emit_int8(0x66); // size prefix
1.1265 case 2:
1.1266 - emit_byte(0x66); // size prefix
1.1267 + emit_int8(0x66); // size prefix
1.1268 case 1:
1.1269 - emit_byte(0x90); // nop
1.1270 + emit_int8((unsigned char)0x90);
1.1271 + // nop
1.1272 break;
1.1273 default:
1.1274 assert(i == 0, " ");
1.1275 @@ -2086,24 +2091,24 @@
1.1276
1.1277 while(i >= 22) {
1.1278 i -= 11;
1.1279 - emit_byte(0x66); // size prefix
1.1280 - emit_byte(0x66); // size prefix
1.1281 - emit_byte(0x66); // size prefix
1.1282 + emit_int8(0x66); // size prefix
1.1283 + emit_int8(0x66); // size prefix
1.1284 + emit_int8(0x66); // size prefix
1.1285 addr_nop_8();
1.1286 }
1.1287 // Generate first nop for size between 21-12
1.1288 switch (i) {
1.1289 case 21:
1.1290 i -= 1;
1.1291 - emit_byte(0x66); // size prefix
1.1292 + emit_int8(0x66); // size prefix
1.1293 case 20:
1.1294 case 19:
1.1295 i -= 1;
1.1296 - emit_byte(0x66); // size prefix
1.1297 + emit_int8(0x66); // size prefix
1.1298 case 18:
1.1299 case 17:
1.1300 i -= 1;
1.1301 - emit_byte(0x66); // size prefix
1.1302 + emit_int8(0x66); // size prefix
1.1303 case 16:
1.1304 case 15:
1.1305 i -= 8;
1.1306 @@ -2116,7 +2121,7 @@
1.1307 break;
1.1308 case 12:
1.1309 i -= 6;
1.1310 - emit_byte(0x66); // size prefix
1.1311 + emit_int8(0x66); // size prefix
1.1312 addr_nop_5();
1.1313 break;
1.1314 default:
1.1315 @@ -2126,11 +2131,11 @@
1.1316 // Generate second nop for size between 11-1
1.1317 switch (i) {
1.1318 case 11:
1.1319 - emit_byte(0x66); // size prefix
1.1320 + emit_int8(0x66); // size prefix
1.1321 case 10:
1.1322 - emit_byte(0x66); // size prefix
1.1323 + emit_int8(0x66); // size prefix
1.1324 case 9:
1.1325 - emit_byte(0x66); // size prefix
1.1326 + emit_int8(0x66); // size prefix
1.1327 case 8:
1.1328 addr_nop_8();
1.1329 break;
1.1330 @@ -2138,7 +2143,7 @@
1.1331 addr_nop_7();
1.1332 break;
1.1333 case 6:
1.1334 - emit_byte(0x66); // size prefix
1.1335 + emit_int8(0x66); // size prefix
1.1336 case 5:
1.1337 addr_nop_5();
1.1338 break;
1.1339 @@ -2147,11 +2152,12 @@
1.1340 break;
1.1341 case 3:
1.1342 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
1.1343 - emit_byte(0x66); // size prefix
1.1344 + emit_int8(0x66); // size prefix
1.1345 case 2:
1.1346 - emit_byte(0x66); // size prefix
1.1347 + emit_int8(0x66); // size prefix
1.1348 case 1:
1.1349 - emit_byte(0x90); // nop
1.1350 + emit_int8((unsigned char)0x90);
1.1351 + // nop
1.1352 break;
1.1353 default:
1.1354 assert(i == 0, " ");
1.1355 @@ -2174,42 +2180,43 @@
1.1356 //
1.1357 while(i > 12) {
1.1358 i -= 4;
1.1359 - emit_byte(0x66); // size prefix
1.1360 - emit_byte(0x66);
1.1361 - emit_byte(0x66);
1.1362 - emit_byte(0x90); // nop
1.1363 + emit_int8(0x66); // size prefix
1.1364 + emit_int8(0x66);
1.1365 + emit_int8(0x66);
1.1366 + emit_int8((unsigned char)0x90);
1.1367 + // nop
1.1368 }
1.1369 // 1 - 12 nops
1.1370 if(i > 8) {
1.1371 if(i > 9) {
1.1372 i -= 1;
1.1373 - emit_byte(0x66);
1.1374 + emit_int8(0x66);
1.1375 }
1.1376 i -= 3;
1.1377 - emit_byte(0x66);
1.1378 - emit_byte(0x66);
1.1379 - emit_byte(0x90);
1.1380 + emit_int8(0x66);
1.1381 + emit_int8(0x66);
1.1382 + emit_int8((unsigned char)0x90);
1.1383 }
1.1384 // 1 - 8 nops
1.1385 if(i > 4) {
1.1386 if(i > 6) {
1.1387 i -= 1;
1.1388 - emit_byte(0x66);
1.1389 + emit_int8(0x66);
1.1390 }
1.1391 i -= 3;
1.1392 - emit_byte(0x66);
1.1393 - emit_byte(0x66);
1.1394 - emit_byte(0x90);
1.1395 + emit_int8(0x66);
1.1396 + emit_int8(0x66);
1.1397 + emit_int8((unsigned char)0x90);
1.1398 }
1.1399 switch (i) {
1.1400 case 4:
1.1401 - emit_byte(0x66);
1.1402 + emit_int8(0x66);
1.1403 case 3:
1.1404 - emit_byte(0x66);
1.1405 + emit_int8(0x66);
1.1406 case 2:
1.1407 - emit_byte(0x66);
1.1408 + emit_int8(0x66);
1.1409 case 1:
1.1410 - emit_byte(0x90);
1.1411 + emit_int8((unsigned char)0x90);
1.1412 break;
1.1413 default:
1.1414 assert(i == 0, " ");
1.1415 @@ -2218,8 +2225,8 @@
1.1416
1.1417 void Assembler::notl(Register dst) {
1.1418 int encode = prefix_and_encode(dst->encoding());
1.1419 - emit_byte(0xF7);
1.1420 - emit_byte(0xD0 | encode );
1.1421 + emit_int8((unsigned char)0xF7);
1.1422 + emit_int8((unsigned char)(0xD0 | encode));
1.1423 }
1.1424
1.1425 void Assembler::orl(Address dst, int32_t imm32) {
1.1426 @@ -2236,7 +2243,7 @@
1.1427 void Assembler::orl(Register dst, Address src) {
1.1428 InstructionMark im(this);
1.1429 prefix(src, dst);
1.1430 - emit_byte(0x0B);
1.1431 + emit_int8(0x0B);
1.1432 emit_operand(dst, src);
1.1433 }
1.1434
1.1435 @@ -2260,61 +2267,61 @@
1.1436 assert(VM_Version::supports_sse4_2(), "");
1.1437 InstructionMark im(this);
1.1438 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A);
1.1439 - emit_byte(0x61);
1.1440 + emit_int8(0x61);
1.1441 emit_operand(dst, src);
1.1442 - emit_byte(imm8);
1.1443 + emit_int8(imm8);
1.1444 }
1.1445
1.1446 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
1.1447 assert(VM_Version::supports_sse4_2(), "");
1.1448 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A);
1.1449 - emit_byte(0x61);
1.1450 - emit_byte(0xC0 | encode);
1.1451 - emit_byte(imm8);
1.1452 + emit_int8(0x61);
1.1453 + emit_int8((unsigned char)(0xC0 | encode));
1.1454 + emit_int8(imm8);
1.1455 }
1.1456
1.1457 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
1.1458 assert(VM_Version::supports_sse4_1(), "");
1.1459 InstructionMark im(this);
1.1460 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1.1461 - emit_byte(0x30);
1.1462 + emit_int8(0x30);
1.1463 emit_operand(dst, src);
1.1464 }
1.1465
1.1466 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
1.1467 assert(VM_Version::supports_sse4_1(), "");
1.1468 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1.1469 - emit_byte(0x30);
1.1470 - emit_byte(0xC0 | encode);
1.1471 + emit_int8(0x30);
1.1472 + emit_int8((unsigned char)(0xC0 | encode));
1.1473 }
1.1474
1.1475 // generic
1.1476 void Assembler::pop(Register dst) {
1.1477 int encode = prefix_and_encode(dst->encoding());
1.1478 - emit_byte(0x58 | encode);
1.1479 + emit_int8(0x58 | encode);
1.1480 }
1.1481
1.1482 void Assembler::popcntl(Register dst, Address src) {
1.1483 assert(VM_Version::supports_popcnt(), "must support");
1.1484 InstructionMark im(this);
1.1485 - emit_byte(0xF3);
1.1486 + emit_int8((unsigned char)0xF3);
1.1487 prefix(src, dst);
1.1488 - emit_byte(0x0F);
1.1489 - emit_byte(0xB8);
1.1490 + emit_int8(0x0F);
1.1491 + emit_int8((unsigned char)0xB8);
1.1492 emit_operand(dst, src);
1.1493 }
1.1494
1.1495 void Assembler::popcntl(Register dst, Register src) {
1.1496 assert(VM_Version::supports_popcnt(), "must support");
1.1497 - emit_byte(0xF3);
1.1498 + emit_int8((unsigned char)0xF3);
1.1499 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1.1500 - emit_byte(0x0F);
1.1501 - emit_byte(0xB8);
1.1502 - emit_byte(0xC0 | encode);
1.1503 + emit_int8(0x0F);
1.1504 + emit_int8((unsigned char)0xB8);
1.1505 + emit_int8((unsigned char)(0xC0 | encode));
1.1506 }
1.1507
1.1508 void Assembler::popf() {
1.1509 - emit_byte(0x9D);
1.1510 + emit_int8((unsigned char)0x9D);
1.1511 }
1.1512
1.1513 #ifndef _LP64 // no 32bit push/pop on amd64
1.1514 @@ -2322,21 +2329,21 @@
1.1515 // NOTE: this will adjust stack by 8byte on 64bits
1.1516 InstructionMark im(this);
1.1517 prefix(dst);
1.1518 - emit_byte(0x8F);
1.1519 + emit_int8((unsigned char)0x8F);
1.1520 emit_operand(rax, dst);
1.1521 }
1.1522 #endif
1.1523
1.1524 void Assembler::prefetch_prefix(Address src) {
1.1525 prefix(src);
1.1526 - emit_byte(0x0F);
1.1527 + emit_int8(0x0F);
1.1528 }
1.1529
1.1530 void Assembler::prefetchnta(Address src) {
1.1531 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
1.1532 InstructionMark im(this);
1.1533 prefetch_prefix(src);
1.1534 - emit_byte(0x18);
1.1535 + emit_int8(0x18);
1.1536 emit_operand(rax, src); // 0, src
1.1537 }
1.1538
1.1539 @@ -2344,7 +2351,7 @@
1.1540 assert(VM_Version::supports_3dnow_prefetch(), "must support");
1.1541 InstructionMark im(this);
1.1542 prefetch_prefix(src);
1.1543 - emit_byte(0x0D);
1.1544 + emit_int8(0x0D);
1.1545 emit_operand(rax, src); // 0, src
1.1546 }
1.1547
1.1548 @@ -2352,7 +2359,7 @@
1.1549 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
1.1550 InstructionMark im(this);
1.1551 prefetch_prefix(src);
1.1552 - emit_byte(0x18);
1.1553 + emit_int8(0x18);
1.1554 emit_operand(rcx, src); // 1, src
1.1555 }
1.1556
1.1557 @@ -2360,7 +2367,7 @@
1.1558 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
1.1559 InstructionMark im(this);
1.1560 prefetch_prefix(src);
1.1561 - emit_byte(0x18);
1.1562 + emit_int8(0x18);
1.1563 emit_operand(rdx, src); // 2, src
1.1564 }
1.1565
1.1566 @@ -2368,7 +2375,7 @@
1.1567 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
1.1568 InstructionMark im(this);
1.1569 prefetch_prefix(src);
1.1570 - emit_byte(0x18);
1.1571 + emit_int8(0x18);
1.1572 emit_operand(rbx, src); // 3, src
1.1573 }
1.1574
1.1575 @@ -2376,26 +2383,26 @@
1.1576 assert(VM_Version::supports_3dnow_prefetch(), "must support");
1.1577 InstructionMark im(this);
1.1578 prefetch_prefix(src);
1.1579 - emit_byte(0x0D);
1.1580 + emit_int8(0x0D);
1.1581 emit_operand(rcx, src); // 1, src
1.1582 }
1.1583
1.1584 void Assembler::prefix(Prefix p) {
1.1585 - a_byte(p);
1.1586 + emit_int8(p);
1.1587 }
1.1588
1.1589 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
1.1590 assert(VM_Version::supports_ssse3(), "");
1.1591 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1.1592 - emit_byte(0x00);
1.1593 - emit_byte(0xC0 | encode);
1.1594 + emit_int8(0x00);
1.1595 + emit_int8((unsigned char)(0xC0 | encode));
1.1596 }
1.1597
1.1598 void Assembler::pshufb(XMMRegister dst, Address src) {
1.1599 assert(VM_Version::supports_ssse3(), "");
1.1600 InstructionMark im(this);
1.1601 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1.1602 - emit_byte(0x00);
1.1603 + emit_int8(0x00);
1.1604 emit_operand(dst, src);
1.1605 }
1.1606
1.1607 @@ -2403,7 +2410,7 @@
1.1608 assert(isByte(mode), "invalid value");
1.1609 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.1610 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_66);
1.1611 - emit_byte(mode & 0xFF);
1.1612 + emit_int8(mode & 0xFF);
1.1613
1.1614 }
1.1615
1.1616 @@ -2413,16 +2420,16 @@
1.1617 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
1.1618 InstructionMark im(this);
1.1619 simd_prefix(dst, src, VEX_SIMD_66);
1.1620 - emit_byte(0x70);
1.1621 + emit_int8(0x70);
1.1622 emit_operand(dst, src);
1.1623 - emit_byte(mode & 0xFF);
1.1624 + emit_int8(mode & 0xFF);
1.1625 }
1.1626
1.1627 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
1.1628 assert(isByte(mode), "invalid value");
1.1629 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.1630 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_F2);
1.1631 - emit_byte(mode & 0xFF);
1.1632 + emit_int8(mode & 0xFF);
1.1633 }
1.1634
1.1635 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
1.1636 @@ -2431,18 +2438,18 @@
1.1637 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
1.1638 InstructionMark im(this);
1.1639 simd_prefix(dst, src, VEX_SIMD_F2);
1.1640 - emit_byte(0x70);
1.1641 + emit_int8(0x70);
1.1642 emit_operand(dst, src);
1.1643 - emit_byte(mode & 0xFF);
1.1644 + emit_int8(mode & 0xFF);
1.1645 }
1.1646
1.1647 void Assembler::psrldq(XMMRegister dst, int shift) {
1.1648 // Shift 128 bit value in xmm register by number of bytes.
1.1649 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.1650 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66);
1.1651 - emit_byte(0x73);
1.1652 - emit_byte(0xC0 | encode);
1.1653 - emit_byte(shift);
1.1654 + emit_int8(0x73);
1.1655 + emit_int8((unsigned char)(0xC0 | encode));
1.1656 + emit_int8(shift);
1.1657 }
1.1658
1.1659 void Assembler::ptest(XMMRegister dst, Address src) {
1.1660 @@ -2450,15 +2457,15 @@
1.1661 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
1.1662 InstructionMark im(this);
1.1663 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1.1664 - emit_byte(0x17);
1.1665 + emit_int8(0x17);
1.1666 emit_operand(dst, src);
1.1667 }
1.1668
1.1669 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
1.1670 assert(VM_Version::supports_sse4_1(), "");
1.1671 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1.1672 - emit_byte(0x17);
1.1673 - emit_byte(0xC0 | encode);
1.1674 + emit_int8(0x17);
1.1675 + emit_int8((unsigned char)(0xC0 | encode));
1.1676 }
1.1677
1.1678 void Assembler::punpcklbw(XMMRegister dst, Address src) {
1.1679 @@ -2491,18 +2498,18 @@
1.1680 void Assembler::push(int32_t imm32) {
1.1681 // in 64bits we push 64bits onto the stack but only
1.1682 // take a 32bit immediate
1.1683 - emit_byte(0x68);
1.1684 + emit_int8(0x68);
1.1685 emit_long(imm32);
1.1686 }
1.1687
1.1688 void Assembler::push(Register src) {
1.1689 int encode = prefix_and_encode(src->encoding());
1.1690
1.1691 - emit_byte(0x50 | encode);
1.1692 + emit_int8(0x50 | encode);
1.1693 }
1.1694
1.1695 void Assembler::pushf() {
1.1696 - emit_byte(0x9C);
1.1697 + emit_int8((unsigned char)0x9C);
1.1698 }
1.1699
1.1700 #ifndef _LP64 // no 32bit push/pop on amd64
1.1701 @@ -2510,7 +2517,7 @@
1.1702 // Note this will push 64bit on 64bit
1.1703 InstructionMark im(this);
1.1704 prefix(src);
1.1705 - emit_byte(0xFF);
1.1706 + emit_int8((unsigned char)0xFF);
1.1707 emit_operand(rsi, src);
1.1708 }
1.1709 #endif
1.1710 @@ -2519,57 +2526,57 @@
1.1711 assert(isShiftCount(imm8), "illegal shift count");
1.1712 int encode = prefix_and_encode(dst->encoding());
1.1713 if (imm8 == 1) {
1.1714 - emit_byte(0xD1);
1.1715 - emit_byte(0xD0 | encode);
1.1716 + emit_int8((unsigned char)0xD1);
1.1717 + emit_int8((unsigned char)(0xD0 | encode));
1.1718 } else {
1.1719 - emit_byte(0xC1);
1.1720 - emit_byte(0xD0 | encode);
1.1721 - emit_byte(imm8);
1.1722 + emit_int8((unsigned char)0xC1);
1.1723 + emit_int8((unsigned char)0xD0 | encode);
1.1724 + emit_int8(imm8);
1.1725 }
1.1726 }
1.1727
1.1728 // copies data from [esi] to [edi] using rcx pointer sized words
1.1729 // generic
1.1730 void Assembler::rep_mov() {
1.1731 - emit_byte(0xF3);
1.1732 + emit_int8((unsigned char)0xF3);
1.1733 // MOVSQ
1.1734 LP64_ONLY(prefix(REX_W));
1.1735 - emit_byte(0xA5);
1.1736 + emit_int8((unsigned char)0xA5);
1.1737 }
1.1738
1.1739 // sets rcx pointer sized words with rax, value at [edi]
1.1740 // generic
1.1741 void Assembler::rep_set() { // rep_set
1.1742 - emit_byte(0xF3);
1.1743 + emit_int8((unsigned char)0xF3);
1.1744 // STOSQ
1.1745 LP64_ONLY(prefix(REX_W));
1.1746 - emit_byte(0xAB);
1.1747 + emit_int8((unsigned char)0xAB);
1.1748 }
1.1749
1.1750 // scans rcx pointer sized words at [edi] for occurance of rax,
1.1751 // generic
1.1752 void Assembler::repne_scan() { // repne_scan
1.1753 - emit_byte(0xF2);
1.1754 + emit_int8((unsigned char)0xF2);
1.1755 // SCASQ
1.1756 LP64_ONLY(prefix(REX_W));
1.1757 - emit_byte(0xAF);
1.1758 + emit_int8((unsigned char)0xAF);
1.1759 }
1.1760
1.1761 #ifdef _LP64
1.1762 // scans rcx 4 byte words at [edi] for occurance of rax,
1.1763 // generic
1.1764 void Assembler::repne_scanl() { // repne_scan
1.1765 - emit_byte(0xF2);
1.1766 + emit_int8((unsigned char)0xF2);
1.1767 // SCASL
1.1768 - emit_byte(0xAF);
1.1769 + emit_int8((unsigned char)0xAF);
1.1770 }
1.1771 #endif
1.1772
1.1773 void Assembler::ret(int imm16) {
1.1774 if (imm16 == 0) {
1.1775 - emit_byte(0xC3);
1.1776 + emit_int8((unsigned char)0xC3);
1.1777 } else {
1.1778 - emit_byte(0xC2);
1.1779 + emit_int8((unsigned char)0xC2);
1.1780 emit_int16(imm16);
1.1781 }
1.1782 }
1.1783 @@ -2579,26 +2586,26 @@
1.1784 // Not supported in 64bit mode
1.1785 ShouldNotReachHere();
1.1786 #endif
1.1787 - emit_byte(0x9E);
1.1788 + emit_int8((unsigned char)0x9E);
1.1789 }
1.1790
1.1791 void Assembler::sarl(Register dst, int imm8) {
1.1792 int encode = prefix_and_encode(dst->encoding());
1.1793 assert(isShiftCount(imm8), "illegal shift count");
1.1794 if (imm8 == 1) {
1.1795 - emit_byte(0xD1);
1.1796 - emit_byte(0xF8 | encode);
1.1797 + emit_int8((unsigned char)0xD1);
1.1798 + emit_int8((unsigned char)(0xF8 | encode));
1.1799 } else {
1.1800 - emit_byte(0xC1);
1.1801 - emit_byte(0xF8 | encode);
1.1802 - emit_byte(imm8);
1.1803 + emit_int8((unsigned char)0xC1);
1.1804 + emit_int8((unsigned char)(0xF8 | encode));
1.1805 + emit_int8(imm8);
1.1806 }
1.1807 }
1.1808
1.1809 void Assembler::sarl(Register dst) {
1.1810 int encode = prefix_and_encode(dst->encoding());
1.1811 - emit_byte(0xD3);
1.1812 - emit_byte(0xF8 | encode);
1.1813 + emit_int8((unsigned char)0xD3);
1.1814 + emit_int8((unsigned char)(0xF8 | encode));
1.1815 }
1.1816
1.1817 void Assembler::sbbl(Address dst, int32_t imm32) {
1.1818 @@ -2616,7 +2623,7 @@
1.1819 void Assembler::sbbl(Register dst, Address src) {
1.1820 InstructionMark im(this);
1.1821 prefix(src, dst);
1.1822 - emit_byte(0x1B);
1.1823 + emit_int8(0x1B);
1.1824 emit_operand(dst, src);
1.1825 }
1.1826
1.1827 @@ -2628,47 +2635,47 @@
1.1828 void Assembler::setb(Condition cc, Register dst) {
1.1829 assert(0 <= cc && cc < 16, "illegal cc");
1.1830 int encode = prefix_and_encode(dst->encoding(), true);
1.1831 - emit_byte(0x0F);
1.1832 - emit_byte(0x90 | cc);
1.1833 - emit_byte(0xC0 | encode);
1.1834 + emit_int8(0x0F);
1.1835 + emit_int8((unsigned char)0x90 | cc);
1.1836 + emit_int8((unsigned char)(0xC0 | encode));
1.1837 }
1.1838
1.1839 void Assembler::shll(Register dst, int imm8) {
1.1840 assert(isShiftCount(imm8), "illegal shift count");
1.1841 int encode = prefix_and_encode(dst->encoding());
1.1842 if (imm8 == 1 ) {
1.1843 - emit_byte(0xD1);
1.1844 - emit_byte(0xE0 | encode);
1.1845 + emit_int8((unsigned char)0xD1);
1.1846 + emit_int8((unsigned char)(0xE0 | encode));
1.1847 } else {
1.1848 - emit_byte(0xC1);
1.1849 - emit_byte(0xE0 | encode);
1.1850 - emit_byte(imm8);
1.1851 + emit_int8((unsigned char)0xC1);
1.1852 + emit_int8((unsigned char)(0xE0 | encode));
1.1853 + emit_int8(imm8);
1.1854 }
1.1855 }
1.1856
1.1857 void Assembler::shll(Register dst) {
1.1858 int encode = prefix_and_encode(dst->encoding());
1.1859 - emit_byte(0xD3);
1.1860 - emit_byte(0xE0 | encode);
1.1861 + emit_int8((unsigned char)0xD3);
1.1862 + emit_int8((unsigned char)(0xE0 | encode));
1.1863 }
1.1864
1.1865 void Assembler::shrl(Register dst, int imm8) {
1.1866 assert(isShiftCount(imm8), "illegal shift count");
1.1867 int encode = prefix_and_encode(dst->encoding());
1.1868 - emit_byte(0xC1);
1.1869 - emit_byte(0xE8 | encode);
1.1870 - emit_byte(imm8);
1.1871 + emit_int8((unsigned char)0xC1);
1.1872 + emit_int8((unsigned char)(0xE8 | encode));
1.1873 + emit_int8(imm8);
1.1874 }
1.1875
1.1876 void Assembler::shrl(Register dst) {
1.1877 int encode = prefix_and_encode(dst->encoding());
1.1878 - emit_byte(0xD3);
1.1879 - emit_byte(0xE8 | encode);
1.1880 + emit_int8((unsigned char)0xD3);
1.1881 + emit_int8((unsigned char)(0xE8 | encode));
1.1882 }
1.1883
1.1884 // copies a single word from [esi] to [edi]
1.1885 void Assembler::smovl() {
1.1886 - emit_byte(0xA5);
1.1887 + emit_int8((unsigned char)0xA5);
1.1888 }
1.1889
1.1890 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
1.1891 @@ -2687,7 +2694,7 @@
1.1892 }
1.1893
1.1894 void Assembler::std() {
1.1895 - emit_byte(0xfd);
1.1896 + emit_int8((unsigned char)0xFD);
1.1897 }
1.1898
1.1899 void Assembler::sqrtss(XMMRegister dst, Address src) {
1.1900 @@ -2699,8 +2706,8 @@
1.1901 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1.1902 InstructionMark im(this);
1.1903 prefix(dst);
1.1904 - emit_byte(0x0F);
1.1905 - emit_byte(0xAE);
1.1906 + emit_int8(0x0F);
1.1907 + emit_int8((unsigned char)0xAE);
1.1908 emit_operand(as_Register(3), dst);
1.1909 }
1.1910
1.1911 @@ -2713,7 +2720,7 @@
1.1912 void Assembler::subl(Address dst, Register src) {
1.1913 InstructionMark im(this);
1.1914 prefix(dst, src);
1.1915 - emit_byte(0x29);
1.1916 + emit_int8(0x29);
1.1917 emit_operand(src, dst);
1.1918 }
1.1919
1.1920 @@ -2731,7 +2738,7 @@
1.1921 void Assembler::subl(Register dst, Address src) {
1.1922 InstructionMark im(this);
1.1923 prefix(src, dst);
1.1924 - emit_byte(0x2B);
1.1925 + emit_int8(0x2B);
1.1926 emit_operand(dst, src);
1.1927 }
1.1928
1.1929 @@ -2772,11 +2779,11 @@
1.1930 // 8bit operands
1.1931 int encode = dst->encoding();
1.1932 if (encode == 0) {
1.1933 - emit_byte(0xA9);
1.1934 + emit_int8((unsigned char)0xA9);
1.1935 } else {
1.1936 encode = prefix_and_encode(encode);
1.1937 - emit_byte(0xF7);
1.1938 - emit_byte(0xC0 | encode);
1.1939 + emit_int8((unsigned char)0xF7);
1.1940 + emit_int8((unsigned char)(0xC0 | encode));
1.1941 }
1.1942 emit_long(imm32);
1.1943 }
1.1944 @@ -2789,7 +2796,7 @@
1.1945 void Assembler::testl(Register dst, Address src) {
1.1946 InstructionMark im(this);
1.1947 prefix(src, dst);
1.1948 - emit_byte(0x85);
1.1949 + emit_int8((unsigned char)0x85);
1.1950 emit_operand(dst, src);
1.1951 }
1.1952
1.1953 @@ -2817,28 +2824,28 @@
1.1954 void Assembler::xaddl(Address dst, Register src) {
1.1955 InstructionMark im(this);
1.1956 prefix(dst, src);
1.1957 - emit_byte(0x0F);
1.1958 - emit_byte(0xC1);
1.1959 + emit_int8(0x0F);
1.1960 + emit_int8((unsigned char)0xC1);
1.1961 emit_operand(src, dst);
1.1962 }
1.1963
1.1964 void Assembler::xchgl(Register dst, Address src) { // xchg
1.1965 InstructionMark im(this);
1.1966 prefix(src, dst);
1.1967 - emit_byte(0x87);
1.1968 + emit_int8((unsigned char)0x87);
1.1969 emit_operand(dst, src);
1.1970 }
1.1971
1.1972 void Assembler::xchgl(Register dst, Register src) {
1.1973 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1.1974 - emit_byte(0x87);
1.1975 - emit_byte(0xc0 | encode);
1.1976 + emit_int8((unsigned char)0x87);
1.1977 + emit_int8((unsigned char)(0xC0 | encode));
1.1978 }
1.1979
1.1980 void Assembler::xgetbv() {
1.1981 - emit_byte(0x0F);
1.1982 - emit_byte(0x01);
1.1983 - emit_byte(0xD0);
1.1984 + emit_int8(0x0F);
1.1985 + emit_int8(0x01);
1.1986 + emit_int8((unsigned char)0xD0);
1.1987 }
1.1988
1.1989 void Assembler::xorl(Register dst, int32_t imm32) {
1.1990 @@ -2849,7 +2856,7 @@
1.1991 void Assembler::xorl(Register dst, Address src) {
1.1992 InstructionMark im(this);
1.1993 prefix(src, dst);
1.1994 - emit_byte(0x33);
1.1995 + emit_int8(0x33);
1.1996 emit_operand(dst, src);
1.1997 }
1.1998
1.1999 @@ -3275,8 +3282,8 @@
1.2000 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
1.2001 assert(VM_Version::supports_sse4_1(), "");
1.2002 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1.2003 - emit_byte(0x40);
1.2004 - emit_byte(0xC0 | encode);
1.2005 + emit_int8(0x40);
1.2006 + emit_int8((unsigned char)(0xC0 | encode));
1.2007 }
1.2008
1.2009 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
1.2010 @@ -3287,8 +3294,8 @@
1.2011 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
1.2012 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.2013 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38);
1.2014 - emit_byte(0x40);
1.2015 - emit_byte(0xC0 | encode);
1.2016 + emit_int8(0x40);
1.2017 + emit_int8((unsigned char)(0xC0 | encode));
1.2018 }
1.2019
1.2020 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
1.2021 @@ -3302,7 +3309,7 @@
1.2022 int dst_enc = dst->encoding();
1.2023 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
1.2024 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector256);
1.2025 - emit_byte(0x40);
1.2026 + emit_int8(0x40);
1.2027 emit_operand(dst, src);
1.2028 }
1.2029
1.2030 @@ -3311,27 +3318,27 @@
1.2031 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.2032 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
1.2033 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66);
1.2034 - emit_byte(0x71);
1.2035 - emit_byte(0xC0 | encode);
1.2036 - emit_byte(shift & 0xFF);
1.2037 + emit_int8(0x71);
1.2038 + emit_int8((unsigned char)(0xC0 | encode));
1.2039 + emit_int8(shift & 0xFF);
1.2040 }
1.2041
1.2042 void Assembler::pslld(XMMRegister dst, int shift) {
1.2043 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.2044 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
1.2045 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66);
1.2046 - emit_byte(0x72);
1.2047 - emit_byte(0xC0 | encode);
1.2048 - emit_byte(shift & 0xFF);
1.2049 + emit_int8(0x72);
1.2050 + emit_int8((unsigned char)(0xC0 | encode));
1.2051 + emit_int8(shift & 0xFF);
1.2052 }
1.2053
1.2054 void Assembler::psllq(XMMRegister dst, int shift) {
1.2055 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.2056 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
1.2057 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66);
1.2058 - emit_byte(0x73);
1.2059 - emit_byte(0xC0 | encode);
1.2060 - emit_byte(shift & 0xFF);
1.2061 + emit_int8(0x73);
1.2062 + emit_int8((unsigned char)(0xC0 | encode));
1.2063 + emit_int8(shift & 0xFF);
1.2064 }
1.2065
1.2066 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
1.2067 @@ -3353,21 +3360,21 @@
1.2068 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.2069 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
1.2070 emit_vex_arith(0x71, xmm6, dst, src, VEX_SIMD_66, vector256);
1.2071 - emit_byte(shift & 0xFF);
1.2072 + emit_int8(shift & 0xFF);
1.2073 }
1.2074
1.2075 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
1.2076 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.2077 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
1.2078 emit_vex_arith(0x72, xmm6, dst, src, VEX_SIMD_66, vector256);
1.2079 - emit_byte(shift & 0xFF);
1.2080 + emit_int8(shift & 0xFF);
1.2081 }
1.2082
1.2083 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
1.2084 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.2085 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
1.2086 emit_vex_arith(0x73, xmm6, dst, src, VEX_SIMD_66, vector256);
1.2087 - emit_byte(shift & 0xFF);
1.2088 + emit_int8(shift & 0xFF);
1.2089 }
1.2090
1.2091 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
1.2092 @@ -3390,18 +3397,18 @@
1.2093 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.2094 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
1.2095 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66);
1.2096 - emit_byte(0x71);
1.2097 - emit_byte(0xC0 | encode);
1.2098 - emit_byte(shift & 0xFF);
1.2099 + emit_int8(0x71);
1.2100 + emit_int8((unsigned char)(0xC0 | encode));
1.2101 + emit_int8(shift & 0xFF);
1.2102 }
1.2103
1.2104 void Assembler::psrld(XMMRegister dst, int shift) {
1.2105 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.2106 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
1.2107 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66);
1.2108 - emit_byte(0x72);
1.2109 - emit_byte(0xC0 | encode);
1.2110 - emit_byte(shift & 0xFF);
1.2111 + emit_int8(0x72);
1.2112 + emit_int8((unsigned char)(0xC0 | encode));
1.2113 + emit_int8(shift & 0xFF);
1.2114 }
1.2115
1.2116 void Assembler::psrlq(XMMRegister dst, int shift) {
1.2117 @@ -3410,9 +3417,9 @@
1.2118 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.2119 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
1.2120 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66);
1.2121 - emit_byte(0x73);
1.2122 - emit_byte(0xC0 | encode);
1.2123 - emit_byte(shift & 0xFF);
1.2124 + emit_int8(0x73);
1.2125 + emit_int8((unsigned char)(0xC0 | encode));
1.2126 + emit_int8(shift & 0xFF);
1.2127 }
1.2128
1.2129 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
1.2130 @@ -3434,21 +3441,21 @@
1.2131 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.2132 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
1.2133 emit_vex_arith(0x71, xmm2, dst, src, VEX_SIMD_66, vector256);
1.2134 - emit_byte(shift & 0xFF);
1.2135 + emit_int8(shift & 0xFF);
1.2136 }
1.2137
1.2138 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
1.2139 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.2140 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
1.2141 emit_vex_arith(0x72, xmm2, dst, src, VEX_SIMD_66, vector256);
1.2142 - emit_byte(shift & 0xFF);
1.2143 + emit_int8(shift & 0xFF);
1.2144 }
1.2145
1.2146 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
1.2147 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.2148 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
1.2149 emit_vex_arith(0x73, xmm2, dst, src, VEX_SIMD_66, vector256);
1.2150 - emit_byte(shift & 0xFF);
1.2151 + emit_int8(shift & 0xFF);
1.2152 }
1.2153
1.2154 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
1.2155 @@ -3471,18 +3478,18 @@
1.2156 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.2157 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
1.2158 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66);
1.2159 - emit_byte(0x71);
1.2160 - emit_byte(0xC0 | encode);
1.2161 - emit_byte(shift & 0xFF);
1.2162 + emit_int8(0x71);
1.2163 + emit_int8((unsigned char)(0xC0 | encode));
1.2164 + emit_int8(shift & 0xFF);
1.2165 }
1.2166
1.2167 void Assembler::psrad(XMMRegister dst, int shift) {
1.2168 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.2169 // XMM4 is for /4 encoding: 66 0F 72 /4 ib
1.2170 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66);
1.2171 - emit_byte(0x72);
1.2172 - emit_byte(0xC0 | encode);
1.2173 - emit_byte(shift & 0xFF);
1.2174 + emit_int8(0x72);
1.2175 + emit_int8((unsigned char)(0xC0 | encode));
1.2176 + emit_int8(shift & 0xFF);
1.2177 }
1.2178
1.2179 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
1.2180 @@ -3499,14 +3506,14 @@
1.2181 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.2182 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
1.2183 emit_vex_arith(0x71, xmm4, dst, src, VEX_SIMD_66, vector256);
1.2184 - emit_byte(shift & 0xFF);
1.2185 + emit_int8(shift & 0xFF);
1.2186 }
1.2187
1.2188 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
1.2189 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.2190 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
1.2191 emit_vex_arith(0x72, xmm4, dst, src, VEX_SIMD_66, vector256);
1.2192 - emit_byte(shift & 0xFF);
1.2193 + emit_int8(shift & 0xFF);
1.2194 }
1.2195
1.2196 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
1.2197 @@ -3571,11 +3578,11 @@
1.2198 assert(VM_Version::supports_avx(), "");
1.2199 bool vector256 = true;
1.2200 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A);
1.2201 - emit_byte(0x18);
1.2202 - emit_byte(0xC0 | encode);
1.2203 + emit_int8(0x18);
1.2204 + emit_int8((unsigned char)(0xC0 | encode));
1.2205 // 0x00 - insert into lower 128 bits
1.2206 // 0x01 - insert into upper 128 bits
1.2207 - emit_byte(0x01);
1.2208 + emit_int8(0x01);
1.2209 }
1.2210
1.2211 void Assembler::vinsertf128h(XMMRegister dst, Address src) {
1.2212 @@ -3586,10 +3593,10 @@
1.2213 int dst_enc = dst->encoding();
1.2214 // swap src<->dst for encoding
1.2215 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
1.2216 - emit_byte(0x18);
1.2217 + emit_int8(0x18);
1.2218 emit_operand(dst, src);
1.2219 // 0x01 - insert into upper 128 bits
1.2220 - emit_byte(0x01);
1.2221 + emit_int8(0x01);
1.2222 }
1.2223
1.2224 void Assembler::vextractf128h(Address dst, XMMRegister src) {
1.2225 @@ -3599,21 +3606,21 @@
1.2226 assert(src != xnoreg, "sanity");
1.2227 int src_enc = src->encoding();
1.2228 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
1.2229 - emit_byte(0x19);
1.2230 + emit_int8(0x19);
1.2231 emit_operand(src, dst);
1.2232 // 0x01 - extract from upper 128 bits
1.2233 - emit_byte(0x01);
1.2234 + emit_int8(0x01);
1.2235 }
1.2236
1.2237 void Assembler::vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1.2238 assert(VM_Version::supports_avx2(), "");
1.2239 bool vector256 = true;
1.2240 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A);
1.2241 - emit_byte(0x38);
1.2242 - emit_byte(0xC0 | encode);
1.2243 + emit_int8(0x38);
1.2244 + emit_int8((unsigned char)(0xC0 | encode));
1.2245 // 0x00 - insert into lower 128 bits
1.2246 // 0x01 - insert into upper 128 bits
1.2247 - emit_byte(0x01);
1.2248 + emit_int8(0x01);
1.2249 }
1.2250
1.2251 void Assembler::vinserti128h(XMMRegister dst, Address src) {
1.2252 @@ -3624,10 +3631,10 @@
1.2253 int dst_enc = dst->encoding();
1.2254 // swap src<->dst for encoding
1.2255 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
1.2256 - emit_byte(0x38);
1.2257 + emit_int8(0x38);
1.2258 emit_operand(dst, src);
1.2259 // 0x01 - insert into upper 128 bits
1.2260 - emit_byte(0x01);
1.2261 + emit_int8(0x01);
1.2262 }
1.2263
1.2264 void Assembler::vextracti128h(Address dst, XMMRegister src) {
1.2265 @@ -3637,16 +3644,16 @@
1.2266 assert(src != xnoreg, "sanity");
1.2267 int src_enc = src->encoding();
1.2268 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
1.2269 - emit_byte(0x39);
1.2270 + emit_int8(0x39);
1.2271 emit_operand(src, dst);
1.2272 // 0x01 - extract from upper 128 bits
1.2273 - emit_byte(0x01);
1.2274 + emit_int8(0x01);
1.2275 }
1.2276
1.2277 void Assembler::vzeroupper() {
1.2278 assert(VM_Version::supports_avx(), "");
1.2279 (void)vex_prefix_and_encode(xmm0, xmm0, xmm0, VEX_SIMD_NONE);
1.2280 - emit_byte(0x77);
1.2281 + emit_int8(0x77);
1.2282 }
1.2283
1.2284
1.2285 @@ -3656,15 +3663,15 @@
1.2286 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
1.2287 // NO PREFIX AS NEVER 64BIT
1.2288 InstructionMark im(this);
1.2289 - emit_byte(0x81);
1.2290 - emit_byte(0xF8 | src1->encoding());
1.2291 + emit_int8((unsigned char)0x81);
1.2292 + emit_int8((unsigned char)(0xF8 | src1->encoding()));
1.2293 emit_data(imm32, rspec, 0);
1.2294 }
1.2295
1.2296 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
1.2297 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
1.2298 InstructionMark im(this);
1.2299 - emit_byte(0x81);
1.2300 + emit_int8((unsigned char)0x81);
1.2301 emit_operand(rdi, src1);
1.2302 emit_data(imm32, rspec, 0);
1.2303 }
1.2304 @@ -3674,14 +3681,14 @@
1.2305 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
1.2306 void Assembler::cmpxchg8(Address adr) {
1.2307 InstructionMark im(this);
1.2308 - emit_byte(0x0F);
1.2309 - emit_byte(0xc7);
1.2310 + emit_int8(0x0F);
1.2311 + emit_int8((unsigned char)0xC7);
1.2312 emit_operand(rcx, adr);
1.2313 }
1.2314
1.2315 void Assembler::decl(Register dst) {
1.2316 // Don't use it directly. Use MacroAssembler::decrementl() instead.
1.2317 - emit_byte(0x48 | dst->encoding());
1.2318 + emit_int8(0x48 | dst->encoding());
1.2319 }
1.2320
1.2321 #endif // _LP64
1.2322 @@ -3689,8 +3696,8 @@
1.2323 // 64bit typically doesn't use the x87 but needs to for the trig funcs
1.2324
1.2325 void Assembler::fabs() {
1.2326 - emit_byte(0xD9);
1.2327 - emit_byte(0xE1);
1.2328 + emit_int8((unsigned char)0xD9);
1.2329 + emit_int8((unsigned char)0xE1);
1.2330 }
1.2331
1.2332 void Assembler::fadd(int i) {
1.2333 @@ -3699,13 +3706,13 @@
1.2334
1.2335 void Assembler::fadd_d(Address src) {
1.2336 InstructionMark im(this);
1.2337 - emit_byte(0xDC);
1.2338 + emit_int8((unsigned char)0xDC);
1.2339 emit_operand32(rax, src);
1.2340 }
1.2341
1.2342 void Assembler::fadd_s(Address src) {
1.2343 InstructionMark im(this);
1.2344 - emit_byte(0xD8);
1.2345 + emit_int8((unsigned char)0xD8);
1.2346 emit_operand32(rax, src);
1.2347 }
1.2348
1.2349 @@ -3718,8 +3725,8 @@
1.2350 }
1.2351
1.2352 void Assembler::fchs() {
1.2353 - emit_byte(0xD9);
1.2354 - emit_byte(0xE0);
1.2355 + emit_int8((unsigned char)0xD9);
1.2356 + emit_int8((unsigned char)0xE0);
1.2357 }
1.2358
1.2359 void Assembler::fcom(int i) {
1.2360 @@ -3732,29 +3739,29 @@
1.2361
1.2362 void Assembler::fcomp_d(Address src) {
1.2363 InstructionMark im(this);
1.2364 - emit_byte(0xDC);
1.2365 + emit_int8((unsigned char)0xDC);
1.2366 emit_operand32(rbx, src);
1.2367 }
1.2368
1.2369 void Assembler::fcomp_s(Address src) {
1.2370 InstructionMark im(this);
1.2371 - emit_byte(0xD8);
1.2372 + emit_int8((unsigned char)0xD8);
1.2373 emit_operand32(rbx, src);
1.2374 }
1.2375
1.2376 void Assembler::fcompp() {
1.2377 - emit_byte(0xDE);
1.2378 - emit_byte(0xD9);
1.2379 + emit_int8((unsigned char)0xDE);
1.2380 + emit_int8((unsigned char)0xD9);
1.2381 }
1.2382
1.2383 void Assembler::fcos() {
1.2384 - emit_byte(0xD9);
1.2385 - emit_byte(0xFF);
1.2386 + emit_int8((unsigned char)0xD9);
1.2387 + emit_int8((unsigned char)0xFF);
1.2388 }
1.2389
1.2390 void Assembler::fdecstp() {
1.2391 - emit_byte(0xD9);
1.2392 - emit_byte(0xF6);
1.2393 + emit_int8((unsigned char)0xD9);
1.2394 + emit_int8((unsigned char)0xF6);
1.2395 }
1.2396
1.2397 void Assembler::fdiv(int i) {
1.2398 @@ -3763,13 +3770,13 @@
1.2399
1.2400 void Assembler::fdiv_d(Address src) {
1.2401 InstructionMark im(this);
1.2402 - emit_byte(0xDC);
1.2403 + emit_int8((unsigned char)0xDC);
1.2404 emit_operand32(rsi, src);
1.2405 }
1.2406
1.2407 void Assembler::fdiv_s(Address src) {
1.2408 InstructionMark im(this);
1.2409 - emit_byte(0xD8);
1.2410 + emit_int8((unsigned char)0xD8);
1.2411 emit_operand32(rsi, src);
1.2412 }
1.2413
1.2414 @@ -3790,13 +3797,13 @@
1.2415
1.2416 void Assembler::fdivr_d(Address src) {
1.2417 InstructionMark im(this);
1.2418 - emit_byte(0xDC);
1.2419 + emit_int8((unsigned char)0xDC);
1.2420 emit_operand32(rdi, src);
1.2421 }
1.2422
1.2423 void Assembler::fdivr_s(Address src) {
1.2424 InstructionMark im(this);
1.2425 - emit_byte(0xD8);
1.2426 + emit_int8((unsigned char)0xD8);
1.2427 emit_operand32(rdi, src);
1.2428 }
1.2429
1.2430 @@ -3814,59 +3821,59 @@
1.2431
1.2432 void Assembler::fild_d(Address adr) {
1.2433 InstructionMark im(this);
1.2434 - emit_byte(0xDF);
1.2435 + emit_int8((unsigned char)0xDF);
1.2436 emit_operand32(rbp, adr);
1.2437 }
1.2438
1.2439 void Assembler::fild_s(Address adr) {
1.2440 InstructionMark im(this);
1.2441 - emit_byte(0xDB);
1.2442 + emit_int8((unsigned char)0xDB);
1.2443 emit_operand32(rax, adr);
1.2444 }
1.2445
1.2446 void Assembler::fincstp() {
1.2447 - emit_byte(0xD9);
1.2448 - emit_byte(0xF7);
1.2449 + emit_int8((unsigned char)0xD9);
1.2450 + emit_int8((unsigned char)0xF7);
1.2451 }
1.2452
1.2453 void Assembler::finit() {
1.2454 - emit_byte(0x9B);
1.2455 - emit_byte(0xDB);
1.2456 - emit_byte(0xE3);
1.2457 + emit_int8((unsigned char)0x9B);
1.2458 + emit_int8((unsigned char)0xDB);
1.2459 + emit_int8((unsigned char)0xE3);
1.2460 }
1.2461
1.2462 void Assembler::fist_s(Address adr) {
1.2463 InstructionMark im(this);
1.2464 - emit_byte(0xDB);
1.2465 + emit_int8((unsigned char)0xDB);
1.2466 emit_operand32(rdx, adr);
1.2467 }
1.2468
1.2469 void Assembler::fistp_d(Address adr) {
1.2470 InstructionMark im(this);
1.2471 - emit_byte(0xDF);
1.2472 + emit_int8((unsigned char)0xDF);
1.2473 emit_operand32(rdi, adr);
1.2474 }
1.2475
1.2476 void Assembler::fistp_s(Address adr) {
1.2477 InstructionMark im(this);
1.2478 - emit_byte(0xDB);
1.2479 + emit_int8((unsigned char)0xDB);
1.2480 emit_operand32(rbx, adr);
1.2481 }
1.2482
1.2483 void Assembler::fld1() {
1.2484 - emit_byte(0xD9);
1.2485 - emit_byte(0xE8);
1.2486 + emit_int8((unsigned char)0xD9);
1.2487 + emit_int8((unsigned char)0xE8);
1.2488 }
1.2489
1.2490 void Assembler::fld_d(Address adr) {
1.2491 InstructionMark im(this);
1.2492 - emit_byte(0xDD);
1.2493 + emit_int8((unsigned char)0xDD);
1.2494 emit_operand32(rax, adr);
1.2495 }
1.2496
1.2497 void Assembler::fld_s(Address adr) {
1.2498 InstructionMark im(this);
1.2499 - emit_byte(0xD9);
1.2500 + emit_int8((unsigned char)0xD9);
1.2501 emit_operand32(rax, adr);
1.2502 }
1.2503
1.2504 @@ -3877,35 +3884,35 @@
1.2505
1.2506 void Assembler::fld_x(Address adr) {
1.2507 InstructionMark im(this);
1.2508 - emit_byte(0xDB);
1.2509 + emit_int8((unsigned char)0xDB);
1.2510 emit_operand32(rbp, adr);
1.2511 }
1.2512
1.2513 void Assembler::fldcw(Address src) {
1.2514 InstructionMark im(this);
1.2515 - emit_byte(0xd9);
1.2516 + emit_int8((unsigned char)0xD9);
1.2517 emit_operand32(rbp, src);
1.2518 }
1.2519
1.2520 void Assembler::fldenv(Address src) {
1.2521 InstructionMark im(this);
1.2522 - emit_byte(0xD9);
1.2523 + emit_int8((unsigned char)0xD9);
1.2524 emit_operand32(rsp, src);
1.2525 }
1.2526
1.2527 void Assembler::fldlg2() {
1.2528 - emit_byte(0xD9);
1.2529 - emit_byte(0xEC);
1.2530 + emit_int8((unsigned char)0xD9);
1.2531 + emit_int8((unsigned char)0xEC);
1.2532 }
1.2533
1.2534 void Assembler::fldln2() {
1.2535 - emit_byte(0xD9);
1.2536 - emit_byte(0xED);
1.2537 + emit_int8((unsigned char)0xD9);
1.2538 + emit_int8((unsigned char)0xED);
1.2539 }
1.2540
1.2541 void Assembler::fldz() {
1.2542 - emit_byte(0xD9);
1.2543 - emit_byte(0xEE);
1.2544 + emit_int8((unsigned char)0xD9);
1.2545 + emit_int8((unsigned char)0xEE);
1.2546 }
1.2547
1.2548 void Assembler::flog() {
1.2549 @@ -3926,13 +3933,13 @@
1.2550
1.2551 void Assembler::fmul_d(Address src) {
1.2552 InstructionMark im(this);
1.2553 - emit_byte(0xDC);
1.2554 + emit_int8((unsigned char)0xDC);
1.2555 emit_operand32(rcx, src);
1.2556 }
1.2557
1.2558 void Assembler::fmul_s(Address src) {
1.2559 InstructionMark im(this);
1.2560 - emit_byte(0xD8);
1.2561 + emit_int8((unsigned char)0xD8);
1.2562 emit_operand32(rcx, src);
1.2563 }
1.2564
1.2565 @@ -3946,63 +3953,63 @@
1.2566
1.2567 void Assembler::fnsave(Address dst) {
1.2568 InstructionMark im(this);
1.2569 - emit_byte(0xDD);
1.2570 + emit_int8((unsigned char)0xDD);
1.2571 emit_operand32(rsi, dst);
1.2572 }
1.2573
1.2574 void Assembler::fnstcw(Address src) {
1.2575 InstructionMark im(this);
1.2576 - emit_byte(0x9B);
1.2577 - emit_byte(0xD9);
1.2578 + emit_int8((unsigned char)0x9B);
1.2579 + emit_int8((unsigned char)0xD9);
1.2580 emit_operand32(rdi, src);
1.2581 }
1.2582
1.2583 void Assembler::fnstsw_ax() {
1.2584 - emit_byte(0xdF);
1.2585 - emit_byte(0xE0);
1.2586 + emit_int8((unsigned char)0xDF);
1.2587 + emit_int8((unsigned char)0xE0);
1.2588 }
1.2589
1.2590 void Assembler::fprem() {
1.2591 - emit_byte(0xD9);
1.2592 - emit_byte(0xF8);
1.2593 + emit_int8((unsigned char)0xD9);
1.2594 + emit_int8((unsigned char)0xF8);
1.2595 }
1.2596
1.2597 void Assembler::fprem1() {
1.2598 - emit_byte(0xD9);
1.2599 - emit_byte(0xF5);
1.2600 + emit_int8((unsigned char)0xD9);
1.2601 + emit_int8((unsigned char)0xF5);
1.2602 }
1.2603
1.2604 void Assembler::frstor(Address src) {
1.2605 InstructionMark im(this);
1.2606 - emit_byte(0xDD);
1.2607 + emit_int8((unsigned char)0xDD);
1.2608 emit_operand32(rsp, src);
1.2609 }
1.2610
1.2611 void Assembler::fsin() {
1.2612 - emit_byte(0xD9);
1.2613 - emit_byte(0xFE);
1.2614 + emit_int8((unsigned char)0xD9);
1.2615 + emit_int8((unsigned char)0xFE);
1.2616 }
1.2617
1.2618 void Assembler::fsqrt() {
1.2619 - emit_byte(0xD9);
1.2620 - emit_byte(0xFA);
1.2621 + emit_int8((unsigned char)0xD9);
1.2622 + emit_int8((unsigned char)0xFA);
1.2623 }
1.2624
1.2625 void Assembler::fst_d(Address adr) {
1.2626 InstructionMark im(this);
1.2627 - emit_byte(0xDD);
1.2628 + emit_int8((unsigned char)0xDD);
1.2629 emit_operand32(rdx, adr);
1.2630 }
1.2631
1.2632 void Assembler::fst_s(Address adr) {
1.2633 InstructionMark im(this);
1.2634 - emit_byte(0xD9);
1.2635 + emit_int8((unsigned char)0xD9);
1.2636 emit_operand32(rdx, adr);
1.2637 }
1.2638
1.2639 void Assembler::fstp_d(Address adr) {
1.2640 InstructionMark im(this);
1.2641 - emit_byte(0xDD);
1.2642 + emit_int8((unsigned char)0xDD);
1.2643 emit_operand32(rbx, adr);
1.2644 }
1.2645
1.2646 @@ -4012,13 +4019,13 @@
1.2647
1.2648 void Assembler::fstp_s(Address adr) {
1.2649 InstructionMark im(this);
1.2650 - emit_byte(0xD9);
1.2651 + emit_int8((unsigned char)0xD9);
1.2652 emit_operand32(rbx, adr);
1.2653 }
1.2654
1.2655 void Assembler::fstp_x(Address adr) {
1.2656 InstructionMark im(this);
1.2657 - emit_byte(0xDB);
1.2658 + emit_int8((unsigned char)0xDB);
1.2659 emit_operand32(rdi, adr);
1.2660 }
1.2661
1.2662 @@ -4028,13 +4035,13 @@
1.2663
1.2664 void Assembler::fsub_d(Address src) {
1.2665 InstructionMark im(this);
1.2666 - emit_byte(0xDC);
1.2667 + emit_int8((unsigned char)0xDC);
1.2668 emit_operand32(rsp, src);
1.2669 }
1.2670
1.2671 void Assembler::fsub_s(Address src) {
1.2672 InstructionMark im(this);
1.2673 - emit_byte(0xD8);
1.2674 + emit_int8((unsigned char)0xD8);
1.2675 emit_operand32(rsp, src);
1.2676 }
1.2677
1.2678 @@ -4052,13 +4059,13 @@
1.2679
1.2680 void Assembler::fsubr_d(Address src) {
1.2681 InstructionMark im(this);
1.2682 - emit_byte(0xDC);
1.2683 + emit_int8((unsigned char)0xDC);
1.2684 emit_operand32(rbp, src);
1.2685 }
1.2686
1.2687 void Assembler::fsubr_s(Address src) {
1.2688 InstructionMark im(this);
1.2689 - emit_byte(0xD8);
1.2690 + emit_int8((unsigned char)0xD8);
1.2691 emit_operand32(rbp, src);
1.2692 }
1.2693
1.2694 @@ -4071,15 +4078,15 @@
1.2695 }
1.2696
1.2697 void Assembler::ftan() {
1.2698 - emit_byte(0xD9);
1.2699 - emit_byte(0xF2);
1.2700 - emit_byte(0xDD);
1.2701 - emit_byte(0xD8);
1.2702 + emit_int8((unsigned char)0xD9);
1.2703 + emit_int8((unsigned char)0xF2);
1.2704 + emit_int8((unsigned char)0xDD);
1.2705 + emit_int8((unsigned char)0xD8);
1.2706 }
1.2707
1.2708 void Assembler::ftst() {
1.2709 - emit_byte(0xD9);
1.2710 - emit_byte(0xE4);
1.2711 + emit_int8((unsigned char)0xD9);
1.2712 + emit_int8((unsigned char)0xE4);
1.2713 }
1.2714
1.2715 void Assembler::fucomi(int i) {
1.2716 @@ -4095,7 +4102,7 @@
1.2717 }
1.2718
1.2719 void Assembler::fwait() {
1.2720 - emit_byte(0x9B);
1.2721 + emit_int8((unsigned char)0x9B);
1.2722 }
1.2723
1.2724 void Assembler::fxch(int i) {
1.2725 @@ -4103,23 +4110,23 @@
1.2726 }
1.2727
1.2728 void Assembler::fyl2x() {
1.2729 - emit_byte(0xD9);
1.2730 - emit_byte(0xF1);
1.2731 + emit_int8((unsigned char)0xD9);
1.2732 + emit_int8((unsigned char)0xF1);
1.2733 }
1.2734
1.2735 void Assembler::frndint() {
1.2736 - emit_byte(0xD9);
1.2737 - emit_byte(0xFC);
1.2738 + emit_int8((unsigned char)0xD9);
1.2739 + emit_int8((unsigned char)0xFC);
1.2740 }
1.2741
1.2742 void Assembler::f2xm1() {
1.2743 - emit_byte(0xD9);
1.2744 - emit_byte(0xF0);
1.2745 + emit_int8((unsigned char)0xD9);
1.2746 + emit_int8((unsigned char)0xF0);
1.2747 }
1.2748
1.2749 void Assembler::fldl2e() {
1.2750 - emit_byte(0xD9);
1.2751 - emit_byte(0xEA);
1.2752 + emit_int8((unsigned char)0xD9);
1.2753 + emit_int8((unsigned char)0xEA);
1.2754 }
1.2755
1.2756 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
1.2757 @@ -4130,7 +4137,7 @@
1.2758 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
1.2759 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
1.2760 if (pre > 0) {
1.2761 - emit_byte(simd_pre[pre]);
1.2762 + emit_int8(simd_pre[pre]);
1.2763 }
1.2764 if (rex_w) {
1.2765 prefixq(adr, xreg);
1.2766 @@ -4138,25 +4145,25 @@
1.2767 prefix(adr, xreg);
1.2768 }
1.2769 if (opc > 0) {
1.2770 - emit_byte(0x0F);
1.2771 + emit_int8(0x0F);
1.2772 int opc2 = simd_opc[opc];
1.2773 if (opc2 > 0) {
1.2774 - emit_byte(opc2);
1.2775 + emit_int8(opc2);
1.2776 }
1.2777 }
1.2778 }
1.2779
1.2780 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
1.2781 if (pre > 0) {
1.2782 - emit_byte(simd_pre[pre]);
1.2783 + emit_int8(simd_pre[pre]);
1.2784 }
1.2785 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) :
1.2786 prefix_and_encode(dst_enc, src_enc);
1.2787 if (opc > 0) {
1.2788 - emit_byte(0x0F);
1.2789 + emit_int8(0x0F);
1.2790 int opc2 = simd_opc[opc];
1.2791 if (opc2 > 0) {
1.2792 - emit_byte(opc2);
1.2793 + emit_int8(opc2);
1.2794 }
1.2795 }
1.2796 return encode;
1.2797 @@ -4170,11 +4177,11 @@
1.2798 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
1.2799 byte1 = (~byte1) & 0xE0;
1.2800 byte1 |= opc;
1.2801 - a_byte(byte1);
1.2802 + emit_int8(byte1);
1.2803
1.2804 int byte2 = ((~nds_enc) & 0xf) << 3;
1.2805 byte2 |= (vex_w ? VEX_W : 0) | (vector256 ? 4 : 0) | pre;
1.2806 - emit_byte(byte2);
1.2807 + emit_int8(byte2);
1.2808 } else {
1.2809 prefix(VEX_2bytes);
1.2810
1.2811 @@ -4182,7 +4189,7 @@
1.2812 byte1 = (~byte1) & 0x80;
1.2813 byte1 |= ((~nds_enc) & 0xf) << 3;
1.2814 byte1 |= (vector256 ? 4 : 0) | pre;
1.2815 - emit_byte(byte1);
1.2816 + emit_int8(byte1);
1.2817 }
1.2818 }
1.2819
1.2820 @@ -4228,28 +4235,28 @@
1.2821 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre) {
1.2822 InstructionMark im(this);
1.2823 simd_prefix(dst, dst, src, pre);
1.2824 - emit_byte(opcode);
1.2825 + emit_int8(opcode);
1.2826 emit_operand(dst, src);
1.2827 }
1.2828
1.2829 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre) {
1.2830 int encode = simd_prefix_and_encode(dst, dst, src, pre);
1.2831 - emit_byte(opcode);
1.2832 - emit_byte(0xC0 | encode);
1.2833 + emit_int8(opcode);
1.2834 + emit_int8((unsigned char)(0xC0 | encode));
1.2835 }
1.2836
1.2837 // Versions with no second source register (non-destructive source).
1.2838 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre) {
1.2839 InstructionMark im(this);
1.2840 simd_prefix(dst, xnoreg, src, pre);
1.2841 - emit_byte(opcode);
1.2842 + emit_int8(opcode);
1.2843 emit_operand(dst, src);
1.2844 }
1.2845
1.2846 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre) {
1.2847 int encode = simd_prefix_and_encode(dst, xnoreg, src, pre);
1.2848 - emit_byte(opcode);
1.2849 - emit_byte(0xC0 | encode);
1.2850 + emit_int8(opcode);
1.2851 + emit_int8((unsigned char)(0xC0 | encode));
1.2852 }
1.2853
1.2854 // 3-operands AVX instructions
1.2855 @@ -4257,22 +4264,22 @@
1.2856 Address src, VexSimdPrefix pre, bool vector256) {
1.2857 InstructionMark im(this);
1.2858 vex_prefix(dst, nds, src, pre, vector256);
1.2859 - emit_byte(opcode);
1.2860 + emit_int8(opcode);
1.2861 emit_operand(dst, src);
1.2862 }
1.2863
1.2864 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds,
1.2865 XMMRegister src, VexSimdPrefix pre, bool vector256) {
1.2866 int encode = vex_prefix_and_encode(dst, nds, src, pre, vector256);
1.2867 - emit_byte(opcode);
1.2868 - emit_byte(0xC0 | encode);
1.2869 + emit_int8(opcode);
1.2870 + emit_int8((unsigned char)(0xC0 | encode));
1.2871 }
1.2872
1.2873 #ifndef _LP64
1.2874
1.2875 void Assembler::incl(Register dst) {
1.2876 // Don't use it directly. Use MacroAssembler::incrementl() instead.
1.2877 - emit_byte(0x40 | dst->encoding());
1.2878 + emit_int8(0x40 | dst->encoding());
1.2879 }
1.2880
1.2881 void Assembler::lea(Register dst, Address src) {
1.2882 @@ -4281,7 +4288,7 @@
1.2883
1.2884 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
1.2885 InstructionMark im(this);
1.2886 - emit_byte(0xC7);
1.2887 + emit_int8((unsigned char)0xC7);
1.2888 emit_operand(rax, dst);
1.2889 emit_data((int)imm32, rspec, 0);
1.2890 }
1.2891 @@ -4289,49 +4296,49 @@
1.2892 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
1.2893 InstructionMark im(this);
1.2894 int encode = prefix_and_encode(dst->encoding());
1.2895 - emit_byte(0xB8 | encode);
1.2896 + emit_int8((unsigned char)(0xB8 | encode));
1.2897 emit_data((int)imm32, rspec, 0);
1.2898 }
1.2899
1.2900 void Assembler::popa() { // 32bit
1.2901 - emit_byte(0x61);
1.2902 + emit_int8(0x61);
1.2903 }
1.2904
1.2905 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
1.2906 InstructionMark im(this);
1.2907 - emit_byte(0x68);
1.2908 + emit_int8(0x68);
1.2909 emit_data(imm32, rspec, 0);
1.2910 }
1.2911
1.2912 void Assembler::pusha() { // 32bit
1.2913 - emit_byte(0x60);
1.2914 + emit_int8(0x60);
1.2915 }
1.2916
1.2917 void Assembler::set_byte_if_not_zero(Register dst) {
1.2918 - emit_byte(0x0F);
1.2919 - emit_byte(0x95);
1.2920 - emit_byte(0xE0 | dst->encoding());
1.2921 + emit_int8(0x0F);
1.2922 + emit_int8((unsigned char)0x95);
1.2923 + emit_int8((unsigned char)(0xE0 | dst->encoding()));
1.2924 }
1.2925
1.2926 void Assembler::shldl(Register dst, Register src) {
1.2927 - emit_byte(0x0F);
1.2928 - emit_byte(0xA5);
1.2929 - emit_byte(0xC0 | src->encoding() << 3 | dst->encoding());
1.2930 + emit_int8(0x0F);
1.2931 + emit_int8((unsigned char)0xA5);
1.2932 + emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
1.2933 }
1.2934
1.2935 void Assembler::shrdl(Register dst, Register src) {
1.2936 - emit_byte(0x0F);
1.2937 - emit_byte(0xAD);
1.2938 - emit_byte(0xC0 | src->encoding() << 3 | dst->encoding());
1.2939 + emit_int8(0x0F);
1.2940 + emit_int8((unsigned char)0xAD);
1.2941 + emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
1.2942 }
1.2943
1.2944 #else // LP64
1.2945
1.2946 void Assembler::set_byte_if_not_zero(Register dst) {
1.2947 int enc = prefix_and_encode(dst->encoding(), true);
1.2948 - emit_byte(0x0F);
1.2949 - emit_byte(0x95);
1.2950 - emit_byte(0xE0 | enc);
1.2951 + emit_int8(0x0F);
1.2952 + emit_int8((unsigned char)0x95);
1.2953 + emit_int8((unsigned char)(0xE0 | enc));
1.2954 }
1.2955
1.2956 // 64bit only pieces of the assembler
1.2957 @@ -4669,7 +4676,7 @@
1.2958 void Assembler::adcq(Register dst, Address src) {
1.2959 InstructionMark im(this);
1.2960 prefixq(src, dst);
1.2961 - emit_byte(0x13);
1.2962 + emit_int8(0x13);
1.2963 emit_operand(dst, src);
1.2964 }
1.2965
1.2966 @@ -4687,7 +4694,7 @@
1.2967 void Assembler::addq(Address dst, Register src) {
1.2968 InstructionMark im(this);
1.2969 prefixq(dst, src);
1.2970 - emit_byte(0x01);
1.2971 + emit_int8(0x01);
1.2972 emit_operand(src, dst);
1.2973 }
1.2974
1.2975 @@ -4699,7 +4706,7 @@
1.2976 void Assembler::addq(Register dst, Address src) {
1.2977 InstructionMark im(this);
1.2978 prefixq(src, dst);
1.2979 - emit_byte(0x03);
1.2980 + emit_int8(0x03);
1.2981 emit_operand(dst, src);
1.2982 }
1.2983
1.2984 @@ -4711,7 +4718,7 @@
1.2985 void Assembler::andq(Address dst, int32_t imm32) {
1.2986 InstructionMark im(this);
1.2987 prefixq(dst);
1.2988 - emit_byte(0x81);
1.2989 + emit_int8((unsigned char)0x81);
1.2990 emit_operand(rsp, dst, 4);
1.2991 emit_long(imm32);
1.2992 }
1.2993 @@ -4724,7 +4731,7 @@
1.2994 void Assembler::andq(Register dst, Address src) {
1.2995 InstructionMark im(this);
1.2996 prefixq(src, dst);
1.2997 - emit_byte(0x23);
1.2998 + emit_int8(0x23);
1.2999 emit_operand(dst, src);
1.3000 }
1.3001
1.3002 @@ -4735,56 +4742,56 @@
1.3003
1.3004 void Assembler::bsfq(Register dst, Register src) {
1.3005 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
1.3006 - emit_byte(0x0F);
1.3007 - emit_byte(0xBC);
1.3008 - emit_byte(0xC0 | encode);
1.3009 + emit_int8(0x0F);
1.3010 + emit_int8((unsigned char)0xBC);
1.3011 + emit_int8((unsigned char)(0xC0 | encode));
1.3012 }
1.3013
1.3014 void Assembler::bsrq(Register dst, Register src) {
1.3015 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT");
1.3016 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
1.3017 - emit_byte(0x0F);
1.3018 - emit_byte(0xBD);
1.3019 - emit_byte(0xC0 | encode);
1.3020 + emit_int8(0x0F);
1.3021 + emit_int8((unsigned char)0xBD);
1.3022 + emit_int8((unsigned char)(0xC0 | encode));
1.3023 }
1.3024
1.3025 void Assembler::bswapq(Register reg) {
1.3026 int encode = prefixq_and_encode(reg->encoding());
1.3027 - emit_byte(0x0F);
1.3028 - emit_byte(0xC8 | encode);
1.3029 + emit_int8(0x0F);
1.3030 + emit_int8((unsigned char)(0xC8 | encode));
1.3031 }
1.3032
1.3033 void Assembler::cdqq() {
1.3034 prefix(REX_W);
1.3035 - emit_byte(0x99);
1.3036 + emit_int8((unsigned char)0x99);
1.3037 }
1.3038
1.3039 void Assembler::clflush(Address adr) {
1.3040 prefix(adr);
1.3041 - emit_byte(0x0F);
1.3042 - emit_byte(0xAE);
1.3043 + emit_int8(0x0F);
1.3044 + emit_int8((unsigned char)0xAE);
1.3045 emit_operand(rdi, adr);
1.3046 }
1.3047
1.3048 void Assembler::cmovq(Condition cc, Register dst, Register src) {
1.3049 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
1.3050 - emit_byte(0x0F);
1.3051 - emit_byte(0x40 | cc);
1.3052 - emit_byte(0xC0 | encode);
1.3053 + emit_int8(0x0F);
1.3054 + emit_int8(0x40 | cc);
1.3055 + emit_int8((unsigned char)(0xC0 | encode));
1.3056 }
1.3057
1.3058 void Assembler::cmovq(Condition cc, Register dst, Address src) {
1.3059 InstructionMark im(this);
1.3060 prefixq(src, dst);
1.3061 - emit_byte(0x0F);
1.3062 - emit_byte(0x40 | cc);
1.3063 + emit_int8(0x0F);
1.3064 + emit_int8(0x40 | cc);
1.3065 emit_operand(dst, src);
1.3066 }
1.3067
1.3068 void Assembler::cmpq(Address dst, int32_t imm32) {
1.3069 InstructionMark im(this);
1.3070 prefixq(dst);
1.3071 - emit_byte(0x81);
1.3072 + emit_int8((unsigned char)0x81);
1.3073 emit_operand(rdi, dst, 4);
1.3074 emit_long(imm32);
1.3075 }
1.3076 @@ -4797,7 +4804,7 @@
1.3077 void Assembler::cmpq(Address dst, Register src) {
1.3078 InstructionMark im(this);
1.3079 prefixq(dst, src);
1.3080 - emit_byte(0x3B);
1.3081 + emit_int8(0x3B);
1.3082 emit_operand(src, dst);
1.3083 }
1.3084
1.3085 @@ -4809,122 +4816,122 @@
1.3086 void Assembler::cmpq(Register dst, Address src) {
1.3087 InstructionMark im(this);
1.3088 prefixq(src, dst);
1.3089 - emit_byte(0x3B);
1.3090 + emit_int8(0x3B);
1.3091 emit_operand(dst, src);
1.3092 }
1.3093
1.3094 void Assembler::cmpxchgq(Register reg, Address adr) {
1.3095 InstructionMark im(this);
1.3096 prefixq(adr, reg);
1.3097 - emit_byte(0x0F);
1.3098 - emit_byte(0xB1);
1.3099 + emit_int8(0x0F);
1.3100 + emit_int8((unsigned char)0xB1);
1.3101 emit_operand(reg, adr);
1.3102 }
1.3103
1.3104 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
1.3105 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.3106 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F2);
1.3107 - emit_byte(0x2A);
1.3108 - emit_byte(0xC0 | encode);
1.3109 + emit_int8(0x2A);
1.3110 + emit_int8((unsigned char)(0xC0 | encode));
1.3111 }
1.3112
1.3113 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
1.3114 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.3115 InstructionMark im(this);
1.3116 simd_prefix_q(dst, dst, src, VEX_SIMD_F2);
1.3117 - emit_byte(0x2A);
1.3118 + emit_int8(0x2A);
1.3119 emit_operand(dst, src);
1.3120 }
1.3121
1.3122 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
1.3123 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1.3124 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F3);
1.3125 - emit_byte(0x2A);
1.3126 - emit_byte(0xC0 | encode);
1.3127 + emit_int8(0x2A);
1.3128 + emit_int8((unsigned char)(0xC0 | encode));
1.3129 }
1.3130
1.3131 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
1.3132 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1.3133 InstructionMark im(this);
1.3134 simd_prefix_q(dst, dst, src, VEX_SIMD_F3);
1.3135 - emit_byte(0x2A);
1.3136 + emit_int8(0x2A);
1.3137 emit_operand(dst, src);
1.3138 }
1.3139
1.3140 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
1.3141 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.3142 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F2);
1.3143 - emit_byte(0x2C);
1.3144 - emit_byte(0xC0 | encode);
1.3145 + emit_int8(0x2C);
1.3146 + emit_int8((unsigned char)(0xC0 | encode));
1.3147 }
1.3148
1.3149 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
1.3150 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1.3151 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F3);
1.3152 - emit_byte(0x2C);
1.3153 - emit_byte(0xC0 | encode);
1.3154 + emit_int8(0x2C);
1.3155 + emit_int8((unsigned char)(0xC0 | encode));
1.3156 }
1.3157
1.3158 void Assembler::decl(Register dst) {
1.3159 // Don't use it directly. Use MacroAssembler::decrementl() instead.
1.3160 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
1.3161 int encode = prefix_and_encode(dst->encoding());
1.3162 - emit_byte(0xFF);
1.3163 - emit_byte(0xC8 | encode);
1.3164 + emit_int8((unsigned char)0xFF);
1.3165 + emit_int8((unsigned char)(0xC8 | encode));
1.3166 }
1.3167
1.3168 void Assembler::decq(Register dst) {
1.3169 // Don't use it directly. Use MacroAssembler::decrementq() instead.
1.3170 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
1.3171 int encode = prefixq_and_encode(dst->encoding());
1.3172 - emit_byte(0xFF);
1.3173 - emit_byte(0xC8 | encode);
1.3174 + emit_int8((unsigned char)0xFF);
1.3175 + emit_int8(0xC8 | encode);
1.3176 }
1.3177
1.3178 void Assembler::decq(Address dst) {
1.3179 // Don't use it directly. Use MacroAssembler::decrementq() instead.
1.3180 InstructionMark im(this);
1.3181 prefixq(dst);
1.3182 - emit_byte(0xFF);
1.3183 + emit_int8((unsigned char)0xFF);
1.3184 emit_operand(rcx, dst);
1.3185 }
1.3186
1.3187 void Assembler::fxrstor(Address src) {
1.3188 prefixq(src);
1.3189 - emit_byte(0x0F);
1.3190 - emit_byte(0xAE);
1.3191 + emit_int8(0x0F);
1.3192 + emit_int8((unsigned char)0xAE);
1.3193 emit_operand(as_Register(1), src);
1.3194 }
1.3195
1.3196 void Assembler::fxsave(Address dst) {
1.3197 prefixq(dst);
1.3198 - emit_byte(0x0F);
1.3199 - emit_byte(0xAE);
1.3200 + emit_int8(0x0F);
1.3201 + emit_int8((unsigned char)0xAE);
1.3202 emit_operand(as_Register(0), dst);
1.3203 }
1.3204
1.3205 void Assembler::idivq(Register src) {
1.3206 int encode = prefixq_and_encode(src->encoding());
1.3207 - emit_byte(0xF7);
1.3208 - emit_byte(0xF8 | encode);
1.3209 + emit_int8((unsigned char)0xF7);
1.3210 + emit_int8((unsigned char)(0xF8 | encode));
1.3211 }
1.3212
1.3213 void Assembler::imulq(Register dst, Register src) {
1.3214 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
1.3215 - emit_byte(0x0F);
1.3216 - emit_byte(0xAF);
1.3217 - emit_byte(0xC0 | encode);
1.3218 + emit_int8(0x0F);
1.3219 + emit_int8((unsigned char)0xAF);
1.3220 + emit_int8((unsigned char)(0xC0 | encode));
1.3221 }
1.3222
1.3223 void Assembler::imulq(Register dst, Register src, int value) {
1.3224 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
1.3225 if (is8bit(value)) {
1.3226 - emit_byte(0x6B);
1.3227 - emit_byte(0xC0 | encode);
1.3228 - emit_byte(value & 0xFF);
1.3229 + emit_int8(0x6B);
1.3230 + emit_int8((unsigned char)(0xC0 | encode));
1.3231 + emit_int8(value & 0xFF);
1.3232 } else {
1.3233 - emit_byte(0x69);
1.3234 - emit_byte(0xC0 | encode);
1.3235 + emit_int8(0x69);
1.3236 + emit_int8((unsigned char)(0xC0 | encode));
1.3237 emit_long(value);
1.3238 }
1.3239 }
1.3240 @@ -4933,23 +4940,23 @@
1.3241 // Don't use it directly. Use MacroAssembler::incrementl() instead.
1.3242 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
1.3243 int encode = prefix_and_encode(dst->encoding());
1.3244 - emit_byte(0xFF);
1.3245 - emit_byte(0xC0 | encode);
1.3246 + emit_int8((unsigned char)0xFF);
1.3247 + emit_int8((unsigned char)(0xC0 | encode));
1.3248 }
1.3249
1.3250 void Assembler::incq(Register dst) {
1.3251 // Don't use it directly. Use MacroAssembler::incrementq() instead.
1.3252 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
1.3253 int encode = prefixq_and_encode(dst->encoding());
1.3254 - emit_byte(0xFF);
1.3255 - emit_byte(0xC0 | encode);
1.3256 + emit_int8((unsigned char)0xFF);
1.3257 + emit_int8((unsigned char)(0xC0 | encode));
1.3258 }
1.3259
1.3260 void Assembler::incq(Address dst) {
1.3261 // Don't use it directly. Use MacroAssembler::incrementq() instead.
1.3262 InstructionMark im(this);
1.3263 prefixq(dst);
1.3264 - emit_byte(0xFF);
1.3265 + emit_int8((unsigned char)0xFF);
1.3266 emit_operand(rax, dst);
1.3267 }
1.3268
1.3269 @@ -4960,35 +4967,35 @@
1.3270 void Assembler::leaq(Register dst, Address src) {
1.3271 InstructionMark im(this);
1.3272 prefixq(src, dst);
1.3273 - emit_byte(0x8D);
1.3274 + emit_int8((unsigned char)0x8D);
1.3275 emit_operand(dst, src);
1.3276 }
1.3277
1.3278 void Assembler::mov64(Register dst, int64_t imm64) {
1.3279 InstructionMark im(this);
1.3280 int encode = prefixq_and_encode(dst->encoding());
1.3281 - emit_byte(0xB8 | encode);
1.3282 + emit_int8((unsigned char)(0xB8 | encode));
1.3283 emit_int64(imm64);
1.3284 }
1.3285
1.3286 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
1.3287 InstructionMark im(this);
1.3288 int encode = prefixq_and_encode(dst->encoding());
1.3289 - emit_byte(0xB8 | encode);
1.3290 + emit_int8(0xB8 | encode);
1.3291 emit_data64(imm64, rspec);
1.3292 }
1.3293
1.3294 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
1.3295 InstructionMark im(this);
1.3296 int encode = prefix_and_encode(dst->encoding());
1.3297 - emit_byte(0xB8 | encode);
1.3298 + emit_int8((unsigned char)(0xB8 | encode));
1.3299 emit_data((int)imm32, rspec, narrow_oop_operand);
1.3300 }
1.3301
1.3302 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
1.3303 InstructionMark im(this);
1.3304 prefix(dst);
1.3305 - emit_byte(0xC7);
1.3306 + emit_int8((unsigned char)0xC7);
1.3307 emit_operand(rax, dst, 4);
1.3308 emit_data((int)imm32, rspec, narrow_oop_operand);
1.3309 }
1.3310 @@ -4996,34 +5003,34 @@
1.3311 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
1.3312 InstructionMark im(this);
1.3313 int encode = prefix_and_encode(src1->encoding());
1.3314 - emit_byte(0x81);
1.3315 - emit_byte(0xF8 | encode);
1.3316 + emit_int8((unsigned char)0x81);
1.3317 + emit_int8((unsigned char)(0xF8 | encode));
1.3318 emit_data((int)imm32, rspec, narrow_oop_operand);
1.3319 }
1.3320
1.3321 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
1.3322 InstructionMark im(this);
1.3323 prefix(src1);
1.3324 - emit_byte(0x81);
1.3325 + emit_int8((unsigned char)0x81);
1.3326 emit_operand(rax, src1, 4);
1.3327 emit_data((int)imm32, rspec, narrow_oop_operand);
1.3328 }
1.3329
1.3330 void Assembler::lzcntq(Register dst, Register src) {
1.3331 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
1.3332 - emit_byte(0xF3);
1.3333 + emit_int8((unsigned char)0xF3);
1.3334 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
1.3335 - emit_byte(0x0F);
1.3336 - emit_byte(0xBD);
1.3337 - emit_byte(0xC0 | encode);
1.3338 + emit_int8(0x0F);
1.3339 + emit_int8((unsigned char)0xBD);
1.3340 + emit_int8((unsigned char)(0xC0 | encode));
1.3341 }
1.3342
1.3343 void Assembler::movdq(XMMRegister dst, Register src) {
1.3344 // table D-1 says MMX/SSE2
1.3345 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.3346 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_66);
1.3347 - emit_byte(0x6E);
1.3348 - emit_byte(0xC0 | encode);
1.3349 + emit_int8(0x6E);
1.3350 + emit_int8((unsigned char)(0xC0 | encode));
1.3351 }
1.3352
1.3353 void Assembler::movdq(Register dst, XMMRegister src) {
1.3354 @@ -5031,43 +5038,43 @@
1.3355 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.3356 // swap src/dst to get correct prefix
1.3357 int encode = simd_prefix_and_encode_q(src, dst, VEX_SIMD_66);
1.3358 - emit_byte(0x7E);
1.3359 - emit_byte(0xC0 | encode);
1.3360 + emit_int8(0x7E);
1.3361 + emit_int8((unsigned char)(0xC0 | encode));
1.3362 }
1.3363
1.3364 void Assembler::movq(Register dst, Register src) {
1.3365 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
1.3366 - emit_byte(0x8B);
1.3367 - emit_byte(0xC0 | encode);
1.3368 + emit_int8((unsigned char)0x8B);
1.3369 + emit_int8((unsigned char)(0xC0 | encode));
1.3370 }
1.3371
1.3372 void Assembler::movq(Register dst, Address src) {
1.3373 InstructionMark im(this);
1.3374 prefixq(src, dst);
1.3375 - emit_byte(0x8B);
1.3376 + emit_int8((unsigned char)0x8B);
1.3377 emit_operand(dst, src);
1.3378 }
1.3379
1.3380 void Assembler::movq(Address dst, Register src) {
1.3381 InstructionMark im(this);
1.3382 prefixq(dst, src);
1.3383 - emit_byte(0x89);
1.3384 + emit_int8((unsigned char)0x89);
1.3385 emit_operand(src, dst);
1.3386 }
1.3387
1.3388 void Assembler::movsbq(Register dst, Address src) {
1.3389 InstructionMark im(this);
1.3390 prefixq(src, dst);
1.3391 - emit_byte(0x0F);
1.3392 - emit_byte(0xBE);
1.3393 + emit_int8(0x0F);
1.3394 + emit_int8((unsigned char)0xBE);
1.3395 emit_operand(dst, src);
1.3396 }
1.3397
1.3398 void Assembler::movsbq(Register dst, Register src) {
1.3399 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
1.3400 - emit_byte(0x0F);
1.3401 - emit_byte(0xBE);
1.3402 - emit_byte(0xC0 | encode);
1.3403 + emit_int8(0x0F);
1.3404 + emit_int8((unsigned char)0xBE);
1.3405 + emit_int8((unsigned char)(0xC0 | encode));
1.3406 }
1.3407
1.3408 void Assembler::movslq(Register dst, int32_t imm32) {
1.3409 @@ -5077,7 +5084,7 @@
1.3410 ShouldNotReachHere();
1.3411 InstructionMark im(this);
1.3412 int encode = prefixq_and_encode(dst->encoding());
1.3413 - emit_byte(0xC7 | encode);
1.3414 + emit_int8((unsigned char)(0xC7 | encode));
1.3415 emit_long(imm32);
1.3416 }
1.3417
1.3418 @@ -5085,7 +5092,7 @@
1.3419 assert(is_simm32(imm32), "lost bits");
1.3420 InstructionMark im(this);
1.3421 prefixq(dst);
1.3422 - emit_byte(0xC7);
1.3423 + emit_int8((unsigned char)0xC7);
1.3424 emit_operand(rax, dst, 4);
1.3425 emit_long(imm32);
1.3426 }
1.3427 @@ -5093,77 +5100,77 @@
1.3428 void Assembler::movslq(Register dst, Address src) {
1.3429 InstructionMark im(this);
1.3430 prefixq(src, dst);
1.3431 - emit_byte(0x63);
1.3432 + emit_int8(0x63);
1.3433 emit_operand(dst, src);
1.3434 }
1.3435
1.3436 void Assembler::movslq(Register dst, Register src) {
1.3437 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
1.3438 - emit_byte(0x63);
1.3439 - emit_byte(0xC0 | encode);
1.3440 + emit_int8(0x63);
1.3441 + emit_int8((unsigned char)(0xC0 | encode));
1.3442 }
1.3443
1.3444 void Assembler::movswq(Register dst, Address src) {
1.3445 InstructionMark im(this);
1.3446 prefixq(src, dst);
1.3447 - emit_byte(0x0F);
1.3448 - emit_byte(0xBF);
1.3449 + emit_int8(0x0F);
1.3450 + emit_int8((unsigned char)0xBF);
1.3451 emit_operand(dst, src);
1.3452 }
1.3453
1.3454 void Assembler::movswq(Register dst, Register src) {
1.3455 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
1.3456 - emit_byte(0x0F);
1.3457 - emit_byte(0xBF);
1.3458 - emit_byte(0xC0 | encode);
1.3459 + emit_int8((unsigned char)0x0F);
1.3460 + emit_int8((unsigned char)0xBF);
1.3461 + emit_int8((unsigned char)(0xC0 | encode));
1.3462 }
1.3463
1.3464 void Assembler::movzbq(Register dst, Address src) {
1.3465 InstructionMark im(this);
1.3466 prefixq(src, dst);
1.3467 - emit_byte(0x0F);
1.3468 - emit_byte(0xB6);
1.3469 + emit_int8((unsigned char)0x0F);
1.3470 + emit_int8((unsigned char)0xB6);
1.3471 emit_operand(dst, src);
1.3472 }
1.3473
1.3474 void Assembler::movzbq(Register dst, Register src) {
1.3475 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
1.3476 - emit_byte(0x0F);
1.3477 - emit_byte(0xB6);
1.3478 - emit_byte(0xC0 | encode);
1.3479 + emit_int8(0x0F);
1.3480 + emit_int8((unsigned char)0xB6);
1.3481 + emit_int8(0xC0 | encode);
1.3482 }
1.3483
1.3484 void Assembler::movzwq(Register dst, Address src) {
1.3485 InstructionMark im(this);
1.3486 prefixq(src, dst);
1.3487 - emit_byte(0x0F);
1.3488 - emit_byte(0xB7);
1.3489 + emit_int8((unsigned char)0x0F);
1.3490 + emit_int8((unsigned char)0xB7);
1.3491 emit_operand(dst, src);
1.3492 }
1.3493
1.3494 void Assembler::movzwq(Register dst, Register src) {
1.3495 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
1.3496 - emit_byte(0x0F);
1.3497 - emit_byte(0xB7);
1.3498 - emit_byte(0xC0 | encode);
1.3499 + emit_int8((unsigned char)0x0F);
1.3500 + emit_int8((unsigned char)0xB7);
1.3501 + emit_int8((unsigned char)(0xC0 | encode));
1.3502 }
1.3503
1.3504 void Assembler::negq(Register dst) {
1.3505 int encode = prefixq_and_encode(dst->encoding());
1.3506 - emit_byte(0xF7);
1.3507 - emit_byte(0xD8 | encode);
1.3508 + emit_int8((unsigned char)0xF7);
1.3509 + emit_int8((unsigned char)(0xD8 | encode));
1.3510 }
1.3511
1.3512 void Assembler::notq(Register dst) {
1.3513 int encode = prefixq_and_encode(dst->encoding());
1.3514 - emit_byte(0xF7);
1.3515 - emit_byte(0xD0 | encode);
1.3516 + emit_int8((unsigned char)0xF7);
1.3517 + emit_int8((unsigned char)(0xD0 | encode));
1.3518 }
1.3519
1.3520 void Assembler::orq(Address dst, int32_t imm32) {
1.3521 InstructionMark im(this);
1.3522 prefixq(dst);
1.3523 - emit_byte(0x81);
1.3524 + emit_int8((unsigned char)0x81);
1.3525 emit_operand(rcx, dst, 4);
1.3526 emit_long(imm32);
1.3527 }
1.3528 @@ -5176,7 +5183,7 @@
1.3529 void Assembler::orq(Register dst, Address src) {
1.3530 InstructionMark im(this);
1.3531 prefixq(src, dst);
1.3532 - emit_byte(0x0B);
1.3533 + emit_int8(0x0B);
1.3534 emit_operand(dst, src);
1.3535 }
1.3536
1.3537 @@ -5209,26 +5216,26 @@
1.3538 void Assembler::popcntq(Register dst, Address src) {
1.3539 assert(VM_Version::supports_popcnt(), "must support");
1.3540 InstructionMark im(this);
1.3541 - emit_byte(0xF3);
1.3542 + emit_int8((unsigned char)0xF3);
1.3543 prefixq(src, dst);
1.3544 - emit_byte(0x0F);
1.3545 - emit_byte(0xB8);
1.3546 + emit_int8((unsigned char)0x0F);
1.3547 + emit_int8((unsigned char)0xB8);
1.3548 emit_operand(dst, src);
1.3549 }
1.3550
1.3551 void Assembler::popcntq(Register dst, Register src) {
1.3552 assert(VM_Version::supports_popcnt(), "must support");
1.3553 - emit_byte(0xF3);
1.3554 + emit_int8((unsigned char)0xF3);
1.3555 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
1.3556 - emit_byte(0x0F);
1.3557 - emit_byte(0xB8);
1.3558 - emit_byte(0xC0 | encode);
1.3559 + emit_int8((unsigned char)0x0F);
1.3560 + emit_int8((unsigned char)0xB8);
1.3561 + emit_int8((unsigned char)(0xC0 | encode));
1.3562 }
1.3563
1.3564 void Assembler::popq(Address dst) {
1.3565 InstructionMark im(this);
1.3566 prefixq(dst);
1.3567 - emit_byte(0x8F);
1.3568 + emit_int8((unsigned char)0x8F);
1.3569 emit_operand(rax, dst);
1.3570 }
1.3571
1.3572 @@ -5260,7 +5267,7 @@
1.3573 void Assembler::pushq(Address src) {
1.3574 InstructionMark im(this);
1.3575 prefixq(src);
1.3576 - emit_byte(0xFF);
1.3577 + emit_int8((unsigned char)0xFF);
1.3578 emit_operand(rsi, src);
1.3579 }
1.3580
1.3581 @@ -5268,31 +5275,31 @@
1.3582 assert(isShiftCount(imm8 >> 1), "illegal shift count");
1.3583 int encode = prefixq_and_encode(dst->encoding());
1.3584 if (imm8 == 1) {
1.3585 - emit_byte(0xD1);
1.3586 - emit_byte(0xD0 | encode);
1.3587 + emit_int8((unsigned char)0xD1);
1.3588 + emit_int8((unsigned char)(0xD0 | encode));
1.3589 } else {
1.3590 - emit_byte(0xC1);
1.3591 - emit_byte(0xD0 | encode);
1.3592 - emit_byte(imm8);
1.3593 + emit_int8((unsigned char)0xC1);
1.3594 + emit_int8((unsigned char)(0xD0 | encode));
1.3595 + emit_int8(imm8);
1.3596 }
1.3597 }
1.3598 void Assembler::sarq(Register dst, int imm8) {
1.3599 assert(isShiftCount(imm8 >> 1), "illegal shift count");
1.3600 int encode = prefixq_and_encode(dst->encoding());
1.3601 if (imm8 == 1) {
1.3602 - emit_byte(0xD1);
1.3603 - emit_byte(0xF8 | encode);
1.3604 + emit_int8((unsigned char)0xD1);
1.3605 + emit_int8((unsigned char)(0xF8 | encode));
1.3606 } else {
1.3607 - emit_byte(0xC1);
1.3608 - emit_byte(0xF8 | encode);
1.3609 - emit_byte(imm8);
1.3610 + emit_int8((unsigned char)0xC1);
1.3611 + emit_int8((unsigned char)(0xF8 | encode));
1.3612 + emit_int8(imm8);
1.3613 }
1.3614 }
1.3615
1.3616 void Assembler::sarq(Register dst) {
1.3617 int encode = prefixq_and_encode(dst->encoding());
1.3618 - emit_byte(0xD3);
1.3619 - emit_byte(0xF8 | encode);
1.3620 + emit_int8((unsigned char)0xD3);
1.3621 + emit_int8((unsigned char)(0xF8 | encode));
1.3622 }
1.3623
1.3624 void Assembler::sbbq(Address dst, int32_t imm32) {
1.3625 @@ -5309,7 +5316,7 @@
1.3626 void Assembler::sbbq(Register dst, Address src) {
1.3627 InstructionMark im(this);
1.3628 prefixq(src, dst);
1.3629 - emit_byte(0x1B);
1.3630 + emit_int8(0x1B);
1.3631 emit_operand(dst, src);
1.3632 }
1.3633
1.3634 @@ -5322,33 +5329,33 @@
1.3635 assert(isShiftCount(imm8 >> 1), "illegal shift count");
1.3636 int encode = prefixq_and_encode(dst->encoding());
1.3637 if (imm8 == 1) {
1.3638 - emit_byte(0xD1);
1.3639 - emit_byte(0xE0 | encode);
1.3640 + emit_int8((unsigned char)0xD1);
1.3641 + emit_int8((unsigned char)(0xE0 | encode));
1.3642 } else {
1.3643 - emit_byte(0xC1);
1.3644 - emit_byte(0xE0 | encode);
1.3645 - emit_byte(imm8);
1.3646 + emit_int8((unsigned char)0xC1);
1.3647 + emit_int8((unsigned char)(0xE0 | encode));
1.3648 + emit_int8(imm8);
1.3649 }
1.3650 }
1.3651
1.3652 void Assembler::shlq(Register dst) {
1.3653 int encode = prefixq_and_encode(dst->encoding());
1.3654 - emit_byte(0xD3);
1.3655 - emit_byte(0xE0 | encode);
1.3656 + emit_int8((unsigned char)0xD3);
1.3657 + emit_int8((unsigned char)(0xE0 | encode));
1.3658 }
1.3659
1.3660 void Assembler::shrq(Register dst, int imm8) {
1.3661 assert(isShiftCount(imm8 >> 1), "illegal shift count");
1.3662 int encode = prefixq_and_encode(dst->encoding());
1.3663 - emit_byte(0xC1);
1.3664 - emit_byte(0xE8 | encode);
1.3665 - emit_byte(imm8);
1.3666 + emit_int8((unsigned char)0xC1);
1.3667 + emit_int8((unsigned char)(0xE8 | encode));
1.3668 + emit_int8(imm8);
1.3669 }
1.3670
1.3671 void Assembler::shrq(Register dst) {
1.3672 int encode = prefixq_and_encode(dst->encoding());
1.3673 - emit_byte(0xD3);
1.3674 - emit_byte(0xE8 | encode);
1.3675 + emit_int8((unsigned char)0xD3);
1.3676 + emit_int8(0xE8 | encode);
1.3677 }
1.3678
1.3679 void Assembler::subq(Address dst, int32_t imm32) {
1.3680 @@ -5360,7 +5367,7 @@
1.3681 void Assembler::subq(Address dst, Register src) {
1.3682 InstructionMark im(this);
1.3683 prefixq(dst, src);
1.3684 - emit_byte(0x29);
1.3685 + emit_int8(0x29);
1.3686 emit_operand(src, dst);
1.3687 }
1.3688
1.3689 @@ -5378,7 +5385,7 @@
1.3690 void Assembler::subq(Register dst, Address src) {
1.3691 InstructionMark im(this);
1.3692 prefixq(src, dst);
1.3693 - emit_byte(0x2B);
1.3694 + emit_int8(0x2B);
1.3695 emit_operand(dst, src);
1.3696 }
1.3697
1.3698 @@ -5394,11 +5401,11 @@
1.3699 int encode = dst->encoding();
1.3700 if (encode == 0) {
1.3701 prefix(REX_W);
1.3702 - emit_byte(0xA9);
1.3703 + emit_int8((unsigned char)0xA9);
1.3704 } else {
1.3705 encode = prefixq_and_encode(encode);
1.3706 - emit_byte(0xF7);
1.3707 - emit_byte(0xC0 | encode);
1.3708 + emit_int8((unsigned char)0xF7);
1.3709 + emit_int8((unsigned char)(0xC0 | encode));
1.3710 }
1.3711 emit_long(imm32);
1.3712 }
1.3713 @@ -5411,22 +5418,22 @@
1.3714 void Assembler::xaddq(Address dst, Register src) {
1.3715 InstructionMark im(this);
1.3716 prefixq(dst, src);
1.3717 - emit_byte(0x0F);
1.3718 - emit_byte(0xC1);
1.3719 + emit_int8(0x0F);
1.3720 + emit_int8((unsigned char)0xC1);
1.3721 emit_operand(src, dst);
1.3722 }
1.3723
1.3724 void Assembler::xchgq(Register dst, Address src) {
1.3725 InstructionMark im(this);
1.3726 prefixq(src, dst);
1.3727 - emit_byte(0x87);
1.3728 + emit_int8((unsigned char)0x87);
1.3729 emit_operand(dst, src);
1.3730 }
1.3731
1.3732 void Assembler::xchgq(Register dst, Register src) {
1.3733 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
1.3734 - emit_byte(0x87);
1.3735 - emit_byte(0xc0 | encode);
1.3736 + emit_int8((unsigned char)0x87);
1.3737 + emit_int8((unsigned char)(0xc0 | encode));
1.3738 }
1.3739
1.3740 void Assembler::xorq(Register dst, Register src) {
1.3741 @@ -5437,7 +5444,7 @@
1.3742 void Assembler::xorq(Register dst, Address src) {
1.3743 InstructionMark im(this);
1.3744 prefixq(src, dst);
1.3745 - emit_byte(0x33);
1.3746 + emit_int8(0x33);
1.3747 emit_operand(dst, src);
1.3748 }
1.3749
