src/cpu/sparc/vm/assembler_sparc.inline.hpp

changeset 2950
cba7b5c2d53f
parent 2441
c17b998c5926
child 3037
3d42f82cd811
     1.1 --- a/src/cpu/sparc/vm/assembler_sparc.inline.hpp	Thu Jun 02 13:36:11 2011 -0700
     1.2 +++ b/src/cpu/sparc/vm/assembler_sparc.inline.hpp	Fri Jun 03 22:31:43 2011 -0700
     1.3 @@ -255,7 +255,11 @@
     1.4  inline void Assembler::stf(    FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2) { emit_long( op(ldst_op) | fd(d, w) | alt_op3(stf_op3, w) | rs1(s1) | rs2(s2) ); }
     1.5  inline void Assembler::stf(    FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a) { emit_data( op(ldst_op) | fd(d, w) | alt_op3(stf_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
     1.6  
     1.7 -inline void Assembler::stf(    FloatRegisterImpl::Width w, FloatRegister d, const Address& a, int offset) { relocate(a.rspec(offset)); stf(w, d, a.base(), a.disp() + offset); }
     1.8 +inline void Assembler::stf(    FloatRegisterImpl::Width w, FloatRegister d, const Address& a, int offset) {
     1.9 +  relocate(a.rspec(offset));
    1.10 +  if (a.has_index()) { assert(offset == 0, ""); stf(w, d, a.base(), a.index()        ); }
    1.11 +  else               {                          stf(w, d, a.base(), a.disp() + offset); }
    1.12 +}
    1.13  
    1.14  inline void Assembler::stfsr(  Register s1, Register s2) { v9_dep();   emit_long( op(ldst_op) |             op3(stfsr_op3) | rs1(s1) | rs2(s2) ); }
    1.15  inline void Assembler::stfsr(  Register s1, int simm13a) { v9_dep();   emit_data( op(ldst_op) |             op3(stfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

mercurial