1.1 --- a/src/share/vm/opto/macro.cpp Wed Apr 18 12:37:42 2018 -0700 1.2 +++ b/src/share/vm/opto/macro.cpp Mon Apr 23 02:05:50 2018 -0700 1.3 @@ -1,5 +1,5 @@ 1.4 /* 1.5 - * Copyright (c) 2005, 2015, Oracle and/or its affiliates. All rights reserved. 1.6 + * Copyright (c) 2005, 2018, Oracle and/or its affiliates. All rights reserved. 1.7 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 1.8 * 1.9 * This code is free software; you can redistribute it and/or modify it 1.10 @@ -1775,7 +1775,7 @@ 1.11 i_o = pf_phi_abio; 1.12 } else if( UseTLAB && AllocatePrefetchStyle == 3 ) { 1.13 // Insert a prefetch for each allocation. 1.14 - // This code is used for Sparc with BIS. 1.15 + // This code is used to generate 1 prefetch instruction per cache line. 1.16 Node *pf_region = new (C) RegionNode(3); 1.17 Node *pf_phi_rawmem = new (C) PhiNode( pf_region, Type::MEMORY, 1.18 TypeRawPtr::BOTTOM ); 1.19 @@ -1791,6 +1791,8 @@ 1.20 transform_later(cache_adr); 1.21 cache_adr = new (C) CastP2XNode(needgc_false, cache_adr); 1.22 transform_later(cache_adr); 1.23 + // Address is aligned to execute prefetch to the beginning of cache line size 1.24 + // (it is important when BIS instruction is used on SPARC as prefetch). 1.25 Node* mask = _igvn.MakeConX(~(intptr_t)(step_size-1)); 1.26 cache_adr = new (C) AndXNode(cache_adr, mask); 1.27 transform_later(cache_adr);