1.1 --- a/src/cpu/sparc/vm/vm_version_sparc.cpp Wed Apr 18 12:37:42 2018 -0700
1.2 +++ b/src/cpu/sparc/vm/vm_version_sparc.cpp Mon Apr 23 02:05:50 2018 -0700
1.3 @@ -1,5 +1,5 @@
1.4 /*
1.5 - * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
1.6 + * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
1.7 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
1.8 *
1.9 * This code is free software; you can redistribute it and/or modify it
1.10 @@ -140,10 +140,17 @@
1.11 if (is_niagara_plus()) {
1.12 if (has_blk_init() && (cache_line_size > 0) && UseTLAB &&
1.13 FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
1.14 - // Use BIS instruction for TLAB allocation prefetch.
1.15 - FLAG_SET_ERGO(intx, AllocatePrefetchInstr, 1);
1.16 - if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
1.17 - FLAG_SET_ERGO(intx, AllocatePrefetchStyle, 3);
1.18 + if (!has_sparc5_instr()) {
1.19 + // Use BIS instruction for TLAB allocation prefetch
1.20 + // on Niagara plus processors other than those based on CoreS4.
1.21 + FLAG_SET_DEFAULT(AllocatePrefetchInstr, 1);
1.22 + } else {
1.23 + // On CoreS4 processors use prefetch instruction
1.24 + // to avoid partial RAW issue, also use prefetch style 3.
1.25 + FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
1.26 + if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
1.27 + FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3);
1.28 + }
1.29 }
1.30 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
1.31 // Use smaller prefetch distance with BIS
1.32 @@ -165,6 +172,11 @@
1.33 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
1.34 }
1.35 if (AllocatePrefetchInstr == 1) {
1.36 +
1.37 + // Use allocation prefetch style 3 because BIS instructions
1.38 + // require aligned memory addresses.
1.39 + FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3);
1.40 +
1.41 // Need a space at the end of TLAB for BIS since it
1.42 // will fault when accessing memory outside of heap.
1.43
