1.1 --- a/src/share/vm/opto/loopnode.cpp Tue Jan 10 18:05:38 2012 -0800
1.2 +++ b/src/share/vm/opto/loopnode.cpp Thu Jan 12 12:28:59 2012 -0800
1.3 @@ -3278,16 +3278,7 @@
1.4 #ifdef ASSERT
1.5 if (legal->is_Start() && !early->is_Root()) {
1.6 // Bad graph. Print idom path and fail.
1.7 - tty->print_cr( "Bad graph detected in build_loop_late");
1.8 - tty->print("n: ");n->dump(); tty->cr();
1.9 - tty->print("early: ");early->dump(); tty->cr();
1.10 - int ct = 0;
1.11 - Node *dbg_legal = LCA;
1.12 - while(!dbg_legal->is_Start() && ct < 100) {
1.13 - tty->print("idom[%d] ",ct); dbg_legal->dump(); tty->cr();
1.14 - ct++;
1.15 - dbg_legal = idom(dbg_legal);
1.16 - }
1.17 + dump_bad_graph(n, early, LCA);
1.18 assert(false, "Bad graph detected in build_loop_late");
1.19 }
1.20 #endif
1.21 @@ -3337,6 +3328,88 @@
1.22 chosen_loop->_body.push(n);// Collect inner loops
1.23 }
1.24
1.25 +#ifdef ASSERT
1.26 +void PhaseIdealLoop::dump_bad_graph(Node* n, Node* early, Node* LCA) {
1.27 + tty->print_cr( "Bad graph detected in build_loop_late");
1.28 + tty->print("n: "); n->dump();
1.29 + tty->print("early(n): "); early->dump();
1.30 + if (n->in(0) != NULL && !n->in(0)->is_top() &&
1.31 + n->in(0) != early && !n->in(0)->is_Root()) {
1.32 + tty->print("n->in(0): "); n->in(0)->dump();
1.33 + }
1.34 + for (uint i = 1; i < n->req(); i++) {
1.35 + Node* in1 = n->in(i);
1.36 + if (in1 != NULL && in1 != n && !in1->is_top()) {
1.37 + tty->print("n->in(%d): ", i); in1->dump();
1.38 + Node* in1_early = get_ctrl(in1);
1.39 + tty->print("early(n->in(%d)): ", i); in1_early->dump();
1.40 + if (in1->in(0) != NULL && !in1->in(0)->is_top() &&
1.41 + in1->in(0) != in1_early && !in1->in(0)->is_Root()) {
1.42 + tty->print("n->in(%d)->in(0): ", i); in1->in(0)->dump();
1.43 + }
1.44 + for (uint j = 1; j < in1->req(); j++) {
1.45 + Node* in2 = in1->in(j);
1.46 + if (in2 != NULL && in2 != n && in2 != in1 && !in2->is_top()) {
1.47 + tty->print("n->in(%d)->in(%d): ", i, j); in2->dump();
1.48 + Node* in2_early = get_ctrl(in2);
1.49 + tty->print("early(n->in(%d)->in(%d)): ", i, j); in2_early->dump();
1.50 + if (in2->in(0) != NULL && !in2->in(0)->is_top() &&
1.51 + in2->in(0) != in2_early && !in2->in(0)->is_Root()) {
1.52 + tty->print("n->in(%d)->in(%d)->in(0): ", i, j); in2->in(0)->dump();
1.53 + }
1.54 + }
1.55 + }
1.56 + }
1.57 + }
1.58 + tty->cr();
1.59 + tty->print("LCA(n): "); LCA->dump();
1.60 + for (uint i = 0; i < n->outcnt(); i++) {
1.61 + Node* u1 = n->raw_out(i);
1.62 + if (u1 == n)
1.63 + continue;
1.64 + tty->print("n->out(%d): ", i); u1->dump();
1.65 + if (u1->is_CFG()) {
1.66 + for (uint j = 0; j < u1->outcnt(); j++) {
1.67 + Node* u2 = u1->raw_out(j);
1.68 + if (u2 != u1 && u2 != n && u2->is_CFG()) {
1.69 + tty->print("n->out(%d)->out(%d): ", i, j); u2->dump();
1.70 + }
1.71 + }
1.72 + } else {
1.73 + Node* u1_later = get_ctrl(u1);
1.74 + tty->print("later(n->out(%d)): ", i); u1_later->dump();
1.75 + if (u1->in(0) != NULL && !u1->in(0)->is_top() &&
1.76 + u1->in(0) != u1_later && !u1->in(0)->is_Root()) {
1.77 + tty->print("n->out(%d)->in(0): ", i); u1->in(0)->dump();
1.78 + }
1.79 + for (uint j = 0; j < u1->outcnt(); j++) {
1.80 + Node* u2 = u1->raw_out(j);
1.81 + if (u2 == n || u2 == u1)
1.82 + continue;
1.83 + tty->print("n->out(%d)->out(%d): ", i, j); u2->dump();
1.84 + if (!u2->is_CFG()) {
1.85 + Node* u2_later = get_ctrl(u2);
1.86 + tty->print("later(n->out(%d)->out(%d)): ", i, j); u2_later->dump();
1.87 + if (u2->in(0) != NULL && !u2->in(0)->is_top() &&
1.88 + u2->in(0) != u2_later && !u2->in(0)->is_Root()) {
1.89 + tty->print("n->out(%d)->in(0): ", i); u2->in(0)->dump();
1.90 + }
1.91 + }
1.92 + }
1.93 + }
1.94 + }
1.95 + tty->cr();
1.96 + int ct = 0;
1.97 + Node *dbg_legal = LCA;
1.98 + while(!dbg_legal->is_Start() && ct < 100) {
1.99 + tty->print("idom[%d] ",ct); dbg_legal->dump();
1.100 + ct++;
1.101 + dbg_legal = idom(dbg_legal);
1.102 + }
1.103 + tty->cr();
1.104 +}
1.105 +#endif
1.106 +
1.107 #ifndef PRODUCT
1.108 //------------------------------dump-------------------------------------------
1.109 void PhaseIdealLoop::dump( ) const {
