src/cpu/ppc/vm/assembler_ppc.inline.hpp

changeset 9713
c4567d28f31f
parent 9687
846245a33793
child 9730
42118db355f5
     1.1 --- a/src/cpu/ppc/vm/assembler_ppc.inline.hpp	Mon Jun 17 17:20:10 2019 +0100
     1.2 +++ b/src/cpu/ppc/vm/assembler_ppc.inline.hpp	Tue Jun 18 09:33:34 2019 -0400
     1.3 @@ -789,7 +789,8 @@
     1.4  inline void Assembler::vsbox(       VectorRegister d, VectorRegister a)                   { emit_int32( VSBOX_OPCODE        | vrt(d) | vra(a)         ); }
     1.5  
     1.6  // SHA (introduced with Power 8)
     1.7 -// Not yet implemented.
     1.8 +inline void Assembler::vshasigmad(VectorRegister d, VectorRegister a, bool st, int six) { emit_int32( VSHASIGMAD_OPCODE | vrt(d) | vra(a) | vst(st) | vsix(six)); }
     1.9 +inline void Assembler::vshasigmaw(VectorRegister d, VectorRegister a, bool st, int six) { emit_int32( VSHASIGMAW_OPCODE | vrt(d) | vra(a) | vst(st) | vsix(six)); }
    1.10  
    1.11  // Vector Binary Polynomial Multiplication (introduced with Power 8)
    1.12  inline void Assembler::vpmsumb(  VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VPMSUMB_OPCODE | vrt(d) | vra(a) | vrb(b)); }
    1.13 @@ -887,6 +888,22 @@
    1.14  inline void Assembler::lvsl(  VectorRegister d, Register s2) { emit_int32( LVSL_OPCODE   | vrt(d) | rb(s2)); }
    1.15  inline void Assembler::lvsr(  VectorRegister d, Register s2) { emit_int32( LVSR_OPCODE   | vrt(d) | rb(s2)); }
    1.16  
    1.17 +inline void Assembler::load_perm(VectorRegister perm, Register addr) {
    1.18 +#if defined(VM_LITTLE_ENDIAN)
    1.19 +  lvsr(perm, addr);
    1.20 +#else
    1.21 +  lvsl(perm, addr);
    1.22 +#endif
    1.23 +}
    1.24 +
    1.25 +inline void Assembler::vec_perm(VectorRegister first_dest, VectorRegister second, VectorRegister perm) {
    1.26 +#if defined(VM_LITTLE_ENDIAN)
    1.27 +  vperm(first_dest, second, first_dest, perm);
    1.28 +#else
    1.29 +  vperm(first_dest, first_dest, second, perm);
    1.30 +#endif
    1.31 +}
    1.32 +
    1.33  inline void Assembler::load_const(Register d, void* x, Register tmp) {
    1.34     load_const(d, (long)x, tmp);
    1.35  }

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