1.1 --- a/src/cpu/sparc/vm/sparc.ad Wed May 21 10:45:07 2008 -0700
1.2 +++ b/src/cpu/sparc/vm/sparc.ad Wed May 21 13:46:23 2008 -0700
1.3 @@ -5486,10 +5486,9 @@
1.4 ins_pipe(iload_mem);
1.5 %}
1.6
1.7 -// Load Klass Pointer
1.8 -instruct loadKlassComp(iRegP dst, memory mem) %{
1.9 - match(Set dst (LoadKlass mem));
1.10 - predicate(n->in(MemNode::Address)->bottom_type()->is_ptr_to_narrowoop());
1.11 +// Load narrow Klass Pointer
1.12 +instruct loadNKlass(iRegN dst, memory mem) %{
1.13 + match(Set dst (LoadNKlass mem));
1.14 ins_cost(MEMORY_REF_COST);
1.15
1.16 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
1.17 @@ -5503,9 +5502,6 @@
1.18 } else {
1.19 __ lduw(base, $mem$$disp, dst);
1.20 }
1.21 - // klass oop never null but this is generated for nonheader klass loads
1.22 - // too which can be null.
1.23 - __ decode_heap_oop(dst);
1.24 %}
1.25 ins_pipe(iload_mem);
1.26 %}
1.27 @@ -5609,22 +5605,24 @@
1.28 ins_pipe(loadConP_poll);
1.29 %}
1.30
1.31 +instruct loadConN0(iRegN dst, immN0 src) %{
1.32 + match(Set dst src);
1.33 +
1.34 + size(4);
1.35 + format %{ "CLR $dst\t! compressed NULL ptr" %}
1.36 + ins_encode( SetNull( dst ) );
1.37 + ins_pipe(ialu_imm);
1.38 +%}
1.39 +
1.40 instruct loadConN(iRegN dst, immN src) %{
1.41 match(Set dst src);
1.42 - ins_cost(DEFAULT_COST * 2);
1.43 - format %{ "SET $src,$dst\t!ptr" %}
1.44 + ins_cost(DEFAULT_COST * 3/2);
1.45 + format %{ "SET $src,$dst\t! compressed ptr" %}
1.46 ins_encode %{
1.47 - address con = (address)$src$$constant;
1.48 Register dst = $dst$$Register;
1.49 - if (con == NULL) {
1.50 - __ mov(G0, dst);
1.51 - } else {
1.52 - __ set_oop((jobject)$src$$constant, dst);
1.53 - __ encode_heap_oop(dst);
1.54 - }
1.55 - %}
1.56 - ins_pipe(loadConP);
1.57 -
1.58 + __ set_narrow_oop((jobject)$src$$constant, dst);
1.59 + %}
1.60 + ins_pipe(ialu_hi_lo_reg);
1.61 %}
1.62
1.63 instruct loadConL(iRegL dst, immL src, o7RegL tmp) %{
1.64 @@ -6258,6 +6256,34 @@
1.65 ins_pipe(ialu_imm);
1.66 %}
1.67
1.68 +// Conditional move for RegN. Only cmov(reg,reg).
1.69 +instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
1.70 + match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
1.71 + ins_cost(150);
1.72 + format %{ "MOV$cmp $pcc,$src,$dst" %}
1.73 + ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
1.74 + ins_pipe(ialu_reg);
1.75 +%}
1.76 +
1.77 +// This instruction also works with CmpN so we don't need cmovNN_reg.
1.78 +instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
1.79 + match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
1.80 + ins_cost(150);
1.81 + size(4);
1.82 + format %{ "MOV$cmp $icc,$src,$dst" %}
1.83 + ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
1.84 + ins_pipe(ialu_reg);
1.85 +%}
1.86 +
1.87 +instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
1.88 + match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
1.89 + ins_cost(150);
1.90 + size(4);
1.91 + format %{ "MOV$cmp $fcc,$src,$dst" %}
1.92 + ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
1.93 + ins_pipe(ialu_reg);
1.94 +%}
1.95 +
1.96 // Conditional move
1.97 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
1.98 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
1.99 @@ -6275,6 +6301,7 @@
1.100 ins_pipe(ialu_imm);
1.101 %}
1.102
1.103 +// This instruction also works with CmpN so we don't need cmovPN_reg.
1.104 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
1.105 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
1.106 ins_cost(150);
1.107 @@ -8265,6 +8292,27 @@
1.108 ins_pipe(ialu_cconly_reg_imm);
1.109 %}
1.110
1.111 +// Compare Narrow oops
1.112 +instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
1.113 + match(Set icc (CmpN op1 op2));
1.114 +
1.115 + size(4);
1.116 + format %{ "CMP $op1,$op2\t! compressed ptr" %}
1.117 + opcode(Assembler::subcc_op3, Assembler::arith_op);
1.118 + ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
1.119 + ins_pipe(ialu_cconly_reg_reg);
1.120 +%}
1.121 +
1.122 +instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
1.123 + match(Set icc (CmpN op1 op2));
1.124 +
1.125 + size(4);
1.126 + format %{ "CMP $op1,$op2\t! compressed ptr" %}
1.127 + opcode(Assembler::subcc_op3, Assembler::arith_op);
1.128 + ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
1.129 + ins_pipe(ialu_cconly_reg_imm);
1.130 +%}
1.131 +
1.132 //----------Max and Min--------------------------------------------------------
1.133 // Min Instructions
1.134 // Conditional move for min
1.135 @@ -8595,6 +8643,14 @@
1.136 ins_pipe(ialu_imm);
1.137 %}
1.138
1.139 +instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
1.140 + match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
1.141 + ins_cost(150);
1.142 + format %{ "MOV$cmp $xcc,$src,$dst" %}
1.143 + ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
1.144 + ins_pipe(ialu_reg);
1.145 +%}
1.146 +
1.147 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
1.148 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
1.149 ins_cost(150);
1.150 @@ -8826,16 +8882,6 @@
1.151 %}
1.152
1.153
1.154 -instruct compP_iRegN_immN0(flagsRegP pcc, iRegN op1, immN0 op2 ) %{
1.155 - match(Set pcc (CmpN op1 op2));
1.156 -
1.157 - size(4);
1.158 - format %{ "CMP $op1,$op2\t! ptr" %}
1.159 - opcode(Assembler::subcc_op3, Assembler::arith_op);
1.160 - ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
1.161 - ins_pipe(ialu_cconly_reg_imm);
1.162 -%}
1.163 -
1.164 // ============================================================================
1.165 // inlined locking and unlocking
1.166
