1.1 --- a/src/cpu/x86/vm/c1_LIRAssembler_x86.cpp Tue Jul 02 07:51:31 2013 +0200
1.2 +++ b/src/cpu/x86/vm/c1_LIRAssembler_x86.cpp Tue Jul 02 20:42:12 2013 -0400
1.3 @@ -1,5 +1,5 @@
1.4 /*
1.5 - * Copyright (c) 2000, 2012, Oracle and/or its affiliates. All rights reserved.
1.6 + * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved.
1.7 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
1.8 *
1.9 * This code is free software; you can redistribute it and/or modify it
1.10 @@ -3512,6 +3512,22 @@
1.11 __ bind(*stub->continuation());
1.12 }
1.13
1.14 +void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
1.15 + assert(op->crc()->is_single_cpu(), "crc must be register");
1.16 + assert(op->val()->is_single_cpu(), "byte value must be register");
1.17 + assert(op->result_opr()->is_single_cpu(), "result must be register");
1.18 + Register crc = op->crc()->as_register();
1.19 + Register val = op->val()->as_register();
1.20 + Register res = op->result_opr()->as_register();
1.21 +
1.22 + assert_different_registers(val, crc, res);
1.23 +
1.24 + __ lea(res, ExternalAddress(StubRoutines::crc_table_addr()));
1.25 + __ notl(crc); // ~crc
1.26 + __ update_byte_crc32(crc, val, res);
1.27 + __ notl(crc); // ~crc
1.28 + __ mov(res, crc);
1.29 +}
1.30
1.31 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
1.32 Register obj = op->obj_opr()->as_register(); // may not be an oop
