Mercurial > jdk8-mips64-public > hotspot / file diff

     1.1 --- a/src/cpu/x86/vm/assembler_x86.cpp	Tue Jul 02 07:51:31 2013 +0200
     1.2 +++ b/src/cpu/x86/vm/assembler_x86.cpp	Tue Jul 02 20:42:12 2013 -0400
     1.3 @@ -1,5 +1,5 @@
     1.4  /*
     1.5 - * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
     1.6 + * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
     1.7   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
     1.8   *
     1.9   * This code is free software; you can redistribute it and/or modify it
    1.10 @@ -1673,6 +1673,11 @@
    1.11    emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66);
    1.12  }
    1.13  
    1.14 +void Assembler::movdqa(XMMRegister dst, Address src) {
    1.15 +  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
    1.16 +  emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66);
    1.17 +}
    1.18 +
    1.19  void Assembler::movdqu(XMMRegister dst, Address src) {
    1.20    NOT_LP64(assert(VM_Version::supports_sse2(), ""));
    1.21    emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3);
    1.22 @@ -2286,6 +2291,38 @@
    1.23    emit_int8(imm8);
    1.24  }
    1.25  
    1.26 +void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
    1.27 +  assert(VM_Version::supports_sse4_1(), "");
    1.28 +  int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, false);
    1.29 +  emit_int8(0x16);
    1.30 +  emit_int8((unsigned char)(0xC0 | encode));
    1.31 +  emit_int8(imm8);
    1.32 +}
    1.33 +
    1.34 +void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
    1.35 +  assert(VM_Version::supports_sse4_1(), "");
    1.36 +  int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, true);
    1.37 +  emit_int8(0x16);
    1.38 +  emit_int8((unsigned char)(0xC0 | encode));
    1.39 +  emit_int8(imm8);
    1.40 +}
    1.41 +
    1.42 +void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
    1.43 +  assert(VM_Version::supports_sse4_1(), "");
    1.44 +  int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, false);
    1.45 +  emit_int8(0x22);
    1.46 +  emit_int8((unsigned char)(0xC0 | encode));
    1.47 +  emit_int8(imm8);
    1.48 +}
    1.49 +
    1.50 +void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
    1.51 +  assert(VM_Version::supports_sse4_1(), "");
    1.52 +  int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, true);
    1.53 +  emit_int8(0x22);
    1.54 +  emit_int8((unsigned char)(0xC0 | encode));
    1.55 +  emit_int8(imm8);
    1.56 +}
    1.57 +
    1.58  void Assembler::pmovzxbw(XMMRegister dst, Address src) {
    1.59    assert(VM_Version::supports_sse4_1(), "");
    1.60    InstructionMark im(this);
    1.61 @@ -3691,6 +3728,16 @@
    1.62    emit_int8((unsigned char)(0xC0 | encode));
    1.63  }
    1.64  
    1.65 +// Carry-Less Multiplication Quadword
    1.66 +void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) {
    1.67 +  assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), "");
    1.68 +  bool vector256 = false;
    1.69 +  int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A);
    1.70 +  emit_int8(0x44);
    1.71 +  emit_int8((unsigned char)(0xC0 | encode));
    1.72 +  emit_int8((unsigned char)mask);
    1.73 +}
    1.74 +
    1.75  void Assembler::vzeroupper() {
    1.76    assert(VM_Version::supports_avx(), "");
    1.77    (void)vex_prefix_and_encode(xmm0, xmm0, xmm0, VEX_SIMD_NONE);