1.1 --- a/src/share/vm/c1/c1_LIR.hpp Tue Jul 24 13:22:11 2018 +0800
1.2 +++ b/src/share/vm/c1/c1_LIR.hpp Tue Jul 24 14:29:09 2018 +0800
1.3 @@ -458,7 +458,7 @@
1.4 // for compatibility with RInfo
1.5 int fpu () const { return lo_reg_half(); }
1.6 #endif // X86
1.7 -#if defined(SPARC) || defined(ARM) || defined(PPC) || defined(MIPS64)
1.8 +#if defined(SPARC) || defined(ARM) || defined(PPC) || defined(MIPS)
1.9 FloatRegister as_float_reg () const;
1.10 FloatRegister as_double_reg () const;
1.11 #endif
1.12 @@ -534,7 +534,7 @@
1.13 , _type(type)
1.14 , _disp(0) { verify(); }
1.15
1.16 -#ifndef MIPS64
1.17 +#ifndef MIPS
1.18 LIR_Address(LIR_Opr base, intx disp, BasicType type):
1.19 #else
1.20 LIR_Address(LIR_Opr base, int disp, BasicType type):
1.21 @@ -669,7 +669,7 @@
1.22 LIR_OprDesc::cpu_register |
1.23 LIR_OprDesc::double_size); }
1.24 #endif // PPC
1.25 -#ifdef MIPS64
1.26 +#ifdef MIPS
1.27 static LIR_Opr double_fpu(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
1.28 (reg << LIR_OprDesc::reg2_shift) |
1.29 LIR_OprDesc::double_type |
1.30 @@ -941,7 +941,7 @@
1.31 , lir_return
1.32 , lir_leal
1.33 , lir_neg
1.34 -#ifndef MIPS64
1.35 +#ifndef MIPS
1.36 , lir_branch
1.37 , lir_cond_float_branch
1.38 #endif
1.39 @@ -958,7 +958,7 @@
1.40 , lir_unwind
1.41 , end_op1
1.42 , begin_op2
1.43 -#ifdef MIPS64
1.44 +#ifdef MIPS
1.45 , lir_branch
1.46 , lir_cond_float_branch
1.47 , lir_null_check_for_branch
1.48 @@ -998,7 +998,7 @@
1.49 , lir_xchg
1.50 , end_op2
1.51 , begin_op3
1.52 -#ifdef MIPS64
1.53 +#ifdef MIPS
1.54 , lir_frem
1.55 #endif
1.56 , lir_idiv
1.57 @@ -1450,7 +1450,7 @@
1.58 };
1.59
1.60
1.61 -#ifndef MIPS64
1.62 +#ifndef MIPS
1.63 class LIR_OpBranch: public LIR_Op {
1.64 friend class LIR_OpVisitState;
1.65
1.66 @@ -1544,7 +1544,7 @@
1.67 };
1.68
1.69
1.70 -#ifndef MIPS64
1.71 +#ifndef MIPS
1.72 // LIR_OpAllocObj
1.73 class LIR_OpAllocObj : public LIR_Op1 {
1.74 friend class LIR_OpVisitState;
1.75 @@ -1708,7 +1708,7 @@
1.76 void print_instr(outputStream* out) const PRODUCT_RETURN;
1.77 };
1.78
1.79 -#ifndef MIPS64
1.80 +#ifndef MIPS
1.81 // LIR_Op2
1.82 class LIR_Op2: public LIR_Op {
1.83 friend class LIR_OpVisitState;
1.84 @@ -1948,7 +1948,7 @@
1.85 };
1.86 #endif
1.87
1.88 -#ifndef MIPS64
1.89 +#ifndef MIPS
1.90 class LIR_OpAllocArray : public LIR_Op {
1.91 friend class LIR_OpVisitState;
1.92
1.93 @@ -2425,7 +2425,7 @@
1.94 void push(LIR_Opr opr) { append(new LIR_Op1(lir_push, opr)); }
1.95 void pop(LIR_Opr reg) { append(new LIR_Op1(lir_pop, reg)); }
1.96
1.97 -#ifndef MIPS64
1.98 +#ifndef MIPS
1.99 void cmp(LIR_Condition condition, LIR_Opr left, LIR_Opr right, CodeEmitInfo* info = NULL) {
1.100 append(new LIR_Op2(lir_cmp, condition, left, right, info));
1.101 }
1.102 @@ -2468,7 +2468,7 @@
1.103 }
1.104
1.105 #endif
1.106 -#ifndef MIPS64
1.107 +#ifndef MIPS
1.108 void cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1.109 LIR_Opr t1, LIR_Opr t2, LIR_Opr result = LIR_OprFact::illegalOpr);
1.110 void cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1.111 @@ -2512,7 +2512,7 @@
1.112 void volatile_store_mem_reg(LIR_Opr src, LIR_Address* address, CodeEmitInfo* info, LIR_PatchCode patch_code = lir_patch_none);
1.113 void volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code);
1.114
1.115 -#ifdef MIPS64
1.116 +#ifdef MIPS
1.117 void frem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info = NULL);
1.118 #endif
1.119
1.120 @@ -2521,7 +2521,7 @@
1.121 void irem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info);
1.122 void irem(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info);
1.123
1.124 -#ifndef MIPS64
1.125 +#ifndef MIPS
1.126 void allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4, int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub);
1.127 void allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, BasicType type, LIR_Opr klass, CodeStub* stub);
1.128 #else
1.129 @@ -2531,20 +2531,20 @@
1.130
1.131 // jump is an unconditional branch
1.132 void jump(BlockBegin* block) {
1.133 -#ifndef MIPS64
1.134 +#ifndef MIPS
1.135 append(new LIR_OpBranch(lir_cond_always, T_ILLEGAL, block));
1.136 #else
1.137 append(new LIR_OpBranch(lir_cond_always, LIR_OprFact::illegalOpr,LIR_OprFact::illegalOpr,T_ILLEGAL, block));
1.138 #endif
1.139 }
1.140 void jump(CodeStub* stub) {
1.141 -#ifndef MIPS64
1.142 +#ifndef MIPS
1.143 append(new LIR_OpBranch(lir_cond_always, T_ILLEGAL, stub));
1.144 #else
1.145 append(new LIR_OpBranch(lir_cond_always, LIR_OprFact::illegalOpr, LIR_OprFact::illegalOpr,T_ILLEGAL, stub));
1.146 #endif
1.147 }
1.148 -#ifndef MIPS64
1.149 +#ifndef MIPS
1.150 void branch(LIR_Condition cond, BasicType type, Label* lbl) { append(new LIR_OpBranch(cond, type, lbl)); }
1.151 void branch(LIR_Condition cond, BasicType type, BlockBegin* block) {
1.152 assert(type != T_FLOAT && type != T_DOUBLE, "no fp comparisons");
