1.1 --- a/src/cpu/x86/vm/x86.ad Mon Oct 22 16:56:03 2012 -0700
1.2 +++ b/src/cpu/x86/vm/x86.ad Tue Oct 23 13:06:37 2012 -0700
1.3 @@ -4102,9 +4102,158 @@
1.4
1.5 // ----------------------- LogicalRightShift -----------------------------------
1.6
1.7 -// Shorts/Chars vector logical right shift produces incorrect Java result
1.8 +// Shorts vector logical right shift produces incorrect Java result
1.9 // for negative data because java code convert short value into int with
1.10 -// sign extension before a shift.
1.11 +// sign extension before a shift. But char vectors are fine since chars are
1.12 +// unsigned values.
1.13 +
1.14 +instruct vsrl2S(vecS dst, vecS shift) %{
1.15 + predicate(n->as_Vector()->length() == 2);
1.16 + match(Set dst (URShiftVS dst shift));
1.17 + format %{ "psrlw $dst,$shift\t! logical right shift packed2S" %}
1.18 + ins_encode %{
1.19 + __ psrlw($dst$$XMMRegister, $shift$$XMMRegister);
1.20 + %}
1.21 + ins_pipe( pipe_slow );
1.22 +%}
1.23 +
1.24 +instruct vsrl2S_imm(vecS dst, immI8 shift) %{
1.25 + predicate(n->as_Vector()->length() == 2);
1.26 + match(Set dst (URShiftVS dst shift));
1.27 + format %{ "psrlw $dst,$shift\t! logical right shift packed2S" %}
1.28 + ins_encode %{
1.29 + __ psrlw($dst$$XMMRegister, (int)$shift$$constant);
1.30 + %}
1.31 + ins_pipe( pipe_slow );
1.32 +%}
1.33 +
1.34 +instruct vsrl2S_reg(vecS dst, vecS src, vecS shift) %{
1.35 + predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
1.36 + match(Set dst (URShiftVS src shift));
1.37 + format %{ "vpsrlw $dst,$src,$shift\t! logical right shift packed2S" %}
1.38 + ins_encode %{
1.39 + bool vector256 = false;
1.40 + __ vpsrlw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
1.41 + %}
1.42 + ins_pipe( pipe_slow );
1.43 +%}
1.44 +
1.45 +instruct vsrl2S_reg_imm(vecS dst, vecS src, immI8 shift) %{
1.46 + predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
1.47 + match(Set dst (URShiftVS src shift));
1.48 + format %{ "vpsrlw $dst,$src,$shift\t! logical right shift packed2S" %}
1.49 + ins_encode %{
1.50 + bool vector256 = false;
1.51 + __ vpsrlw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
1.52 + %}
1.53 + ins_pipe( pipe_slow );
1.54 +%}
1.55 +
1.56 +instruct vsrl4S(vecD dst, vecS shift) %{
1.57 + predicate(n->as_Vector()->length() == 4);
1.58 + match(Set dst (URShiftVS dst shift));
1.59 + format %{ "psrlw $dst,$shift\t! logical right shift packed4S" %}
1.60 + ins_encode %{
1.61 + __ psrlw($dst$$XMMRegister, $shift$$XMMRegister);
1.62 + %}
1.63 + ins_pipe( pipe_slow );
1.64 +%}
1.65 +
1.66 +instruct vsrl4S_imm(vecD dst, immI8 shift) %{
1.67 + predicate(n->as_Vector()->length() == 4);
1.68 + match(Set dst (URShiftVS dst shift));
1.69 + format %{ "psrlw $dst,$shift\t! logical right shift packed4S" %}
1.70 + ins_encode %{
1.71 + __ psrlw($dst$$XMMRegister, (int)$shift$$constant);
1.72 + %}
1.73 + ins_pipe( pipe_slow );
1.74 +%}
1.75 +
1.76 +instruct vsrl4S_reg(vecD dst, vecD src, vecS shift) %{
1.77 + predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
1.78 + match(Set dst (URShiftVS src shift));
1.79 + format %{ "vpsrlw $dst,$src,$shift\t! logical right shift packed4S" %}
1.80 + ins_encode %{
1.81 + bool vector256 = false;
1.82 + __ vpsrlw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
1.83 + %}
1.84 + ins_pipe( pipe_slow );
1.85 +%}
1.86 +
1.87 +instruct vsrl4S_reg_imm(vecD dst, vecD src, immI8 shift) %{
1.88 + predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
1.89 + match(Set dst (URShiftVS src shift));
1.90 + format %{ "vpsrlw $dst,$src,$shift\t! logical right shift packed4S" %}
1.91 + ins_encode %{
1.92 + bool vector256 = false;
1.93 + __ vpsrlw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
1.94 + %}
1.95 + ins_pipe( pipe_slow );
1.96 +%}
1.97 +
1.98 +instruct vsrl8S(vecX dst, vecS shift) %{
1.99 + predicate(n->as_Vector()->length() == 8);
1.100 + match(Set dst (URShiftVS dst shift));
1.101 + format %{ "psrlw $dst,$shift\t! logical right shift packed8S" %}
1.102 + ins_encode %{
1.103 + __ psrlw($dst$$XMMRegister, $shift$$XMMRegister);
1.104 + %}
1.105 + ins_pipe( pipe_slow );
1.106 +%}
1.107 +
1.108 +instruct vsrl8S_imm(vecX dst, immI8 shift) %{
1.109 + predicate(n->as_Vector()->length() == 8);
1.110 + match(Set dst (URShiftVS dst shift));
1.111 + format %{ "psrlw $dst,$shift\t! logical right shift packed8S" %}
1.112 + ins_encode %{
1.113 + __ psrlw($dst$$XMMRegister, (int)$shift$$constant);
1.114 + %}
1.115 + ins_pipe( pipe_slow );
1.116 +%}
1.117 +
1.118 +instruct vsrl8S_reg(vecX dst, vecX src, vecS shift) %{
1.119 + predicate(UseAVX > 0 && n->as_Vector()->length() == 8);
1.120 + match(Set dst (URShiftVS src shift));
1.121 + format %{ "vpsrlw $dst,$src,$shift\t! logical right shift packed8S" %}
1.122 + ins_encode %{
1.123 + bool vector256 = false;
1.124 + __ vpsrlw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
1.125 + %}
1.126 + ins_pipe( pipe_slow );
1.127 +%}
1.128 +
1.129 +instruct vsrl8S_reg_imm(vecX dst, vecX src, immI8 shift) %{
1.130 + predicate(UseAVX > 0 && n->as_Vector()->length() == 8);
1.131 + match(Set dst (URShiftVS src shift));
1.132 + format %{ "vpsrlw $dst,$src,$shift\t! logical right shift packed8S" %}
1.133 + ins_encode %{
1.134 + bool vector256 = false;
1.135 + __ vpsrlw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
1.136 + %}
1.137 + ins_pipe( pipe_slow );
1.138 +%}
1.139 +
1.140 +instruct vsrl16S_reg(vecY dst, vecY src, vecS shift) %{
1.141 + predicate(UseAVX > 1 && n->as_Vector()->length() == 16);
1.142 + match(Set dst (URShiftVS src shift));
1.143 + format %{ "vpsrlw $dst,$src,$shift\t! logical right shift packed16S" %}
1.144 + ins_encode %{
1.145 + bool vector256 = true;
1.146 + __ vpsrlw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
1.147 + %}
1.148 + ins_pipe( pipe_slow );
1.149 +%}
1.150 +
1.151 +instruct vsrl16S_reg_imm(vecY dst, vecY src, immI8 shift) %{
1.152 + predicate(UseAVX > 1 && n->as_Vector()->length() == 16);
1.153 + match(Set dst (URShiftVS src shift));
1.154 + format %{ "vpsrlw $dst,$src,$shift\t! logical right shift packed16S" %}
1.155 + ins_encode %{
1.156 + bool vector256 = true;
1.157 + __ vpsrlw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
1.158 + %}
1.159 + ins_pipe( pipe_slow );
1.160 +%}
1.161
1.162 // Integers vector logical right shift
1.163 instruct vsrl2I(vecD dst, vecS shift) %{
