1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/src/cpu/x86/vm/register_x86.hpp Sat Dec 01 00:00:00 2007 +0000
1.3 @@ -0,0 +1,221 @@
1.4 +/*
1.5 + * Copyright 2000-2007 Sun Microsystems, Inc. All Rights Reserved.
1.6 + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
1.7 + *
1.8 + * This code is free software; you can redistribute it and/or modify it
1.9 + * under the terms of the GNU General Public License version 2 only, as
1.10 + * published by the Free Software Foundation.
1.11 + *
1.12 + * This code is distributed in the hope that it will be useful, but WITHOUT
1.13 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1.14 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1.15 + * version 2 for more details (a copy is included in the LICENSE file that
1.16 + * accompanied this code).
1.17 + *
1.18 + * You should have received a copy of the GNU General Public License version
1.19 + * 2 along with this work; if not, write to the Free Software Foundation,
1.20 + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
1.21 + *
1.22 + * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
1.23 + * CA 95054 USA or visit www.sun.com if you need additional information or
1.24 + * have any questions.
1.25 + *
1.26 + */
1.27 +
1.28 +class VMRegImpl;
1.29 +typedef VMRegImpl* VMReg;
1.30 +
1.31 +// Use Register as shortcut
1.32 +class RegisterImpl;
1.33 +typedef RegisterImpl* Register;
1.34 +
1.35 +
1.36 +// The implementation of integer registers for the ia32 architecture
1.37 +inline Register as_Register(int encoding) {
1.38 + return (Register)(intptr_t) encoding;
1.39 +}
1.40 +
1.41 +class RegisterImpl: public AbstractRegisterImpl {
1.42 + public:
1.43 + enum {
1.44 +#ifndef AMD64
1.45 + number_of_registers = 8,
1.46 + number_of_byte_registers = 4
1.47 +#else
1.48 + number_of_registers = 16,
1.49 + number_of_byte_registers = 16
1.50 +#endif // AMD64
1.51 + };
1.52 +
1.53 + // derived registers, offsets, and addresses
1.54 + Register successor() const { return as_Register(encoding() + 1); }
1.55 +
1.56 + // construction
1.57 + inline friend Register as_Register(int encoding);
1.58 +
1.59 + VMReg as_VMReg();
1.60 +
1.61 + // accessors
1.62 + int encoding() const { assert(is_valid(), "invalid register"); return (intptr_t)this; }
1.63 + bool is_valid() const { return 0 <= (intptr_t)this && (intptr_t)this < number_of_registers; }
1.64 + bool has_byte_register() const { return 0 <= (intptr_t)this && (intptr_t)this < number_of_byte_registers; }
1.65 + const char* name() const;
1.66 +};
1.67 +
1.68 +// The integer registers of the ia32/amd64 architecture
1.69 +
1.70 +CONSTANT_REGISTER_DECLARATION(Register, noreg, (-1));
1.71 +
1.72 +
1.73 +CONSTANT_REGISTER_DECLARATION(Register, rax, (0));
1.74 +CONSTANT_REGISTER_DECLARATION(Register, rcx, (1));
1.75 +CONSTANT_REGISTER_DECLARATION(Register, rdx, (2));
1.76 +CONSTANT_REGISTER_DECLARATION(Register, rbx, (3));
1.77 +CONSTANT_REGISTER_DECLARATION(Register, rsp, (4));
1.78 +CONSTANT_REGISTER_DECLARATION(Register, rbp, (5));
1.79 +CONSTANT_REGISTER_DECLARATION(Register, rsi, (6));
1.80 +CONSTANT_REGISTER_DECLARATION(Register, rdi, (7));
1.81 +#ifdef AMD64
1.82 +CONSTANT_REGISTER_DECLARATION(Register, r8, (8));
1.83 +CONSTANT_REGISTER_DECLARATION(Register, r9, (9));
1.84 +CONSTANT_REGISTER_DECLARATION(Register, r10, (10));
1.85 +CONSTANT_REGISTER_DECLARATION(Register, r11, (11));
1.86 +CONSTANT_REGISTER_DECLARATION(Register, r12, (12));
1.87 +CONSTANT_REGISTER_DECLARATION(Register, r13, (13));
1.88 +CONSTANT_REGISTER_DECLARATION(Register, r14, (14));
1.89 +CONSTANT_REGISTER_DECLARATION(Register, r15, (15));
1.90 +#endif // AMD64
1.91 +
1.92 +// Use FloatRegister as shortcut
1.93 +class FloatRegisterImpl;
1.94 +typedef FloatRegisterImpl* FloatRegister;
1.95 +
1.96 +inline FloatRegister as_FloatRegister(int encoding) {
1.97 + return (FloatRegister)(intptr_t) encoding;
1.98 +}
1.99 +
1.100 +// The implementation of floating point registers for the ia32 architecture
1.101 +class FloatRegisterImpl: public AbstractRegisterImpl {
1.102 + public:
1.103 + enum {
1.104 + number_of_registers = 8
1.105 + };
1.106 +
1.107 + // construction
1.108 + inline friend FloatRegister as_FloatRegister(int encoding);
1.109 +
1.110 + VMReg as_VMReg();
1.111 +
1.112 + // derived registers, offsets, and addresses
1.113 + FloatRegister successor() const { return as_FloatRegister(encoding() + 1); }
1.114 +
1.115 + // accessors
1.116 + int encoding() const { assert(is_valid(), "invalid register"); return (intptr_t)this; }
1.117 + bool is_valid() const { return 0 <= (intptr_t)this && (intptr_t)this < number_of_registers; }
1.118 + const char* name() const;
1.119 +
1.120 +};
1.121 +
1.122 +// Use XMMRegister as shortcut
1.123 +class XMMRegisterImpl;
1.124 +typedef XMMRegisterImpl* XMMRegister;
1.125 +
1.126 +// Use MMXRegister as shortcut
1.127 +class MMXRegisterImpl;
1.128 +typedef MMXRegisterImpl* MMXRegister;
1.129 +
1.130 +inline XMMRegister as_XMMRegister(int encoding) {
1.131 + return (XMMRegister)(intptr_t)encoding;
1.132 +}
1.133 +
1.134 +inline MMXRegister as_MMXRegister(int encoding) {
1.135 + return (MMXRegister)(intptr_t)encoding;
1.136 +}
1.137 +
1.138 +// The implementation of XMM registers for the IA32 architecture
1.139 +class XMMRegisterImpl: public AbstractRegisterImpl {
1.140 + public:
1.141 + enum {
1.142 +#ifndef AMD64
1.143 + number_of_registers = 8
1.144 +#else
1.145 + number_of_registers = 16
1.146 +#endif // AMD64
1.147 + };
1.148 +
1.149 + // construction
1.150 + friend XMMRegister as_XMMRegister(int encoding);
1.151 +
1.152 + VMReg as_VMReg();
1.153 +
1.154 + // derived registers, offsets, and addresses
1.155 + XMMRegister successor() const { return as_XMMRegister(encoding() + 1); }
1.156 +
1.157 + // accessors
1.158 + int encoding() const { assert(is_valid(), "invalid register"); return (intptr_t)this; }
1.159 + bool is_valid() const { return 0 <= (intptr_t)this && (intptr_t)this < number_of_registers; }
1.160 + const char* name() const;
1.161 +};
1.162 +
1.163 +
1.164 +// The XMM registers, for P3 and up chips
1.165 +CONSTANT_REGISTER_DECLARATION(XMMRegister, xnoreg , (-1));
1.166 +CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm0 , ( 0));
1.167 +CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm1 , ( 1));
1.168 +CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm2 , ( 2));
1.169 +CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm3 , ( 3));
1.170 +CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm4 , ( 4));
1.171 +CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm5 , ( 5));
1.172 +CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm6 , ( 6));
1.173 +CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm7 , ( 7));
1.174 +#ifdef AMD64
1.175 +CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm8, (8));
1.176 +CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm9, (9));
1.177 +CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm10, (10));
1.178 +CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm11, (11));
1.179 +CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm12, (12));
1.180 +CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm13, (13));
1.181 +CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm14, (14));
1.182 +CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm15, (15));
1.183 +#endif // AMD64
1.184 +
1.185 +// Only used by the 32bit stubGenerator. These can't be described by vmreg and hence
1.186 +// can't be described in oopMaps and therefore can't be used by the compilers (at least
1.187 +// were deopt might wan't to see them).
1.188 +
1.189 +// The MMX registers, for P3 and up chips
1.190 +CONSTANT_REGISTER_DECLARATION(MMXRegister, mnoreg , (-1));
1.191 +CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx0 , ( 0));
1.192 +CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx1 , ( 1));
1.193 +CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx2 , ( 2));
1.194 +CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx3 , ( 3));
1.195 +CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx4 , ( 4));
1.196 +CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx5 , ( 5));
1.197 +CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx6 , ( 6));
1.198 +CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx7 , ( 7));
1.199 +
1.200 +
1.201 +// Need to know the total number of registers of all sorts for SharedInfo.
1.202 +// Define a class that exports it.
1.203 +class ConcreteRegisterImpl : public AbstractRegisterImpl {
1.204 + public:
1.205 + enum {
1.206 + // A big enough number for C2: all the registers plus flags
1.207 + // This number must be large enough to cover REG_COUNT (defined by c2) registers.
1.208 + // There is no requirement that any ordering here matches any ordering c2 gives
1.209 + // it's optoregs.
1.210 +
1.211 + number_of_registers = RegisterImpl::number_of_registers +
1.212 +#ifdef AMD64
1.213 + RegisterImpl::number_of_registers + // "H" half of a 64bit register
1.214 +#endif // AMD64
1.215 + 2 * FloatRegisterImpl::number_of_registers +
1.216 + 2 * XMMRegisterImpl::number_of_registers +
1.217 + 1 // eflags
1.218 + };
1.219 +
1.220 + static const int max_gpr;
1.221 + static const int max_fpr;
1.222 + static const int max_xmm;
1.223 +
1.224 +};
