Mercurial > jdk8-mips64-public > hotspot / file diff

     1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/src/cpu/x86/vm/icache_x86.hpp	Sat Dec 01 00:00:00 2007 +0000
     1.3 @@ -0,0 +1,55 @@
     1.4 +/*
     1.5 + * Copyright 1997-2004 Sun Microsystems, Inc.  All Rights Reserved.
     1.6 + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
     1.7 + *
     1.8 + * This code is free software; you can redistribute it and/or modify it
     1.9 + * under the terms of the GNU General Public License version 2 only, as
    1.10 + * published by the Free Software Foundation.
    1.11 + *
    1.12 + * This code is distributed in the hope that it will be useful, but WITHOUT
    1.13 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
    1.14 + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
    1.15 + * version 2 for more details (a copy is included in the LICENSE file that
    1.16 + * accompanied this code).
    1.17 + *
    1.18 + * You should have received a copy of the GNU General Public License version
    1.19 + * 2 along with this work; if not, write to the Free Software Foundation,
    1.20 + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
    1.21 + *
    1.22 + * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
    1.23 + * CA 95054 USA or visit www.sun.com if you need additional information or
    1.24 + * have any questions.
    1.25 + *
    1.26 + */
    1.27 +
    1.28 +// Interface for updating the instruction cache.  Whenever the VM modifies
    1.29 +// code, part of the processor instruction cache potentially has to be flushed.
    1.30 +
    1.31 +// On the x86, this is a no-op -- the I-cache is guaranteed to be consistent
    1.32 +// after the next jump, and the VM never modifies instructions directly ahead
    1.33 +// of the instruction fetch path.
    1.34 +
    1.35 +// [phh] It's not clear that the above comment is correct, because on an MP
    1.36 +// system where the dcaches are not snooped, only the thread doing the invalidate
    1.37 +// will see the update.  Even in the snooped case, a memory fence would be
    1.38 +// necessary if stores weren't ordered.  Fortunately, they are on all known
    1.39 +// x86 implementations.
    1.40 +
    1.41 +class ICache : public AbstractICache {
    1.42 + public:
    1.43 +#ifdef AMD64
    1.44 +  enum {
    1.45 +    stub_size      = 64, // Size of the icache flush stub in bytes
    1.46 +    line_size      = 32, // Icache line size in bytes
    1.47 +    log2_line_size = 5   // log2(line_size)
    1.48 +  };
    1.49 +
    1.50 +  // Use default implementation
    1.51 +#else
    1.52 +  enum {
    1.53 +    stub_size      = 16,                 // Size of the icache flush stub in bytes
    1.54 +    line_size      = BytesPerWord,      // conservative
    1.55 +    log2_line_size = LogBytesPerWord    // log2(line_size)
    1.56 +  };
    1.57 +#endif // AMD64
    1.58 +};