1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/src/cpu/sparc/vm/register_sparc.hpp Sat Dec 01 00:00:00 2007 +0000
1.3 @@ -0,0 +1,442 @@
1.4 +/*
1.5 + * Copyright 2000-2007 Sun Microsystems, Inc. All Rights Reserved.
1.6 + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
1.7 + *
1.8 + * This code is free software; you can redistribute it and/or modify it
1.9 + * under the terms of the GNU General Public License version 2 only, as
1.10 + * published by the Free Software Foundation.
1.11 + *
1.12 + * This code is distributed in the hope that it will be useful, but WITHOUT
1.13 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1.14 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1.15 + * version 2 for more details (a copy is included in the LICENSE file that
1.16 + * accompanied this code).
1.17 + *
1.18 + * You should have received a copy of the GNU General Public License version
1.19 + * 2 along with this work; if not, write to the Free Software Foundation,
1.20 + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
1.21 + *
1.22 + * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
1.23 + * CA 95054 USA or visit www.sun.com if you need additional information or
1.24 + * have any questions.
1.25 + *
1.26 + */
1.27 +
1.28 +// forward declaration
1.29 +class Address;
1.30 +class VMRegImpl;
1.31 +typedef VMRegImpl* VMReg;
1.32 +
1.33 +
1.34 +// Use Register as shortcut
1.35 +class RegisterImpl;
1.36 +typedef RegisterImpl* Register;
1.37 +
1.38 +
1.39 +inline Register as_Register(int encoding) {
1.40 + return (Register)(intptr_t) encoding;
1.41 +}
1.42 +
1.43 +// The implementation of integer registers for the SPARC architecture
1.44 +class RegisterImpl: public AbstractRegisterImpl {
1.45 + public:
1.46 + enum {
1.47 + log_set_size = 3, // the number of bits to encode the set register number
1.48 + number_of_sets = 4, // the number of registers sets (in, local, out, global)
1.49 + number_of_registers = number_of_sets << log_set_size,
1.50 +
1.51 + iset_no = 3, ibase = iset_no << log_set_size, // the in register set
1.52 + lset_no = 2, lbase = lset_no << log_set_size, // the local register set
1.53 + oset_no = 1, obase = oset_no << log_set_size, // the output register set
1.54 + gset_no = 0, gbase = gset_no << log_set_size // the global register set
1.55 + };
1.56 +
1.57 +
1.58 + friend Register as_Register(int encoding);
1.59 + // set specific construction
1.60 + friend Register as_iRegister(int number);
1.61 + friend Register as_lRegister(int number);
1.62 + friend Register as_oRegister(int number);
1.63 + friend Register as_gRegister(int number);
1.64 +
1.65 + VMReg as_VMReg();
1.66 +
1.67 + // accessors
1.68 + int encoding() const { assert(is_valid(), "invalid register"); return value(); }
1.69 + const char* name() const;
1.70 +
1.71 + // testers
1.72 + bool is_valid() const { return (0 <= (value()&0x7F) && (value()&0x7F) < number_of_registers); }
1.73 + bool is_even() const { return (encoding() & 1) == 0; }
1.74 + bool is_in() const { return (encoding() >> log_set_size) == iset_no; }
1.75 + bool is_local() const { return (encoding() >> log_set_size) == lset_no; }
1.76 + bool is_out() const { return (encoding() >> log_set_size) == oset_no; }
1.77 + bool is_global() const { return (encoding() >> log_set_size) == gset_no; }
1.78 +
1.79 + // derived registers, offsets, and addresses
1.80 + Register successor() const { return as_Register(encoding() + 1); }
1.81 +
1.82 + int input_number() const {
1.83 + assert(is_in(), "must be input register");
1.84 + return encoding() - ibase;
1.85 + }
1.86 +
1.87 + Register after_save() const {
1.88 + assert(is_out() || is_global(), "register not visible after save");
1.89 + return is_out() ? as_Register(encoding() + (ibase - obase)) : (const Register)this;
1.90 + }
1.91 +
1.92 + Register after_restore() const {
1.93 + assert(is_in() || is_global(), "register not visible after restore");
1.94 + return is_in() ? as_Register(encoding() + (obase - ibase)) : (const Register)this;
1.95 + }
1.96 +
1.97 + int sp_offset_in_saved_window() const {
1.98 + assert(is_in() || is_local(), "only i and l registers are saved in frame");
1.99 + return encoding() - lbase;
1.100 + }
1.101 +
1.102 + inline Address address_in_saved_window() const; // implemented in assembler_sparc.hpp
1.103 +};
1.104 +
1.105 +
1.106 +// set specific construction
1.107 +inline Register as_iRegister(int number) { return as_Register(RegisterImpl::ibase + number); }
1.108 +inline Register as_lRegister(int number) { return as_Register(RegisterImpl::lbase + number); }
1.109 +inline Register as_oRegister(int number) { return as_Register(RegisterImpl::obase + number); }
1.110 +inline Register as_gRegister(int number) { return as_Register(RegisterImpl::gbase + number); }
1.111 +
1.112 +// The integer registers of the SPARC architecture
1.113 +
1.114 +CONSTANT_REGISTER_DECLARATION(Register, noreg , (-1));
1.115 +
1.116 +CONSTANT_REGISTER_DECLARATION(Register, G0 , (RegisterImpl::gbase + 0));
1.117 +CONSTANT_REGISTER_DECLARATION(Register, G1 , (RegisterImpl::gbase + 1));
1.118 +CONSTANT_REGISTER_DECLARATION(Register, G2 , (RegisterImpl::gbase + 2));
1.119 +CONSTANT_REGISTER_DECLARATION(Register, G3 , (RegisterImpl::gbase + 3));
1.120 +CONSTANT_REGISTER_DECLARATION(Register, G4 , (RegisterImpl::gbase + 4));
1.121 +CONSTANT_REGISTER_DECLARATION(Register, G5 , (RegisterImpl::gbase + 5));
1.122 +CONSTANT_REGISTER_DECLARATION(Register, G6 , (RegisterImpl::gbase + 6));
1.123 +CONSTANT_REGISTER_DECLARATION(Register, G7 , (RegisterImpl::gbase + 7));
1.124 +
1.125 +CONSTANT_REGISTER_DECLARATION(Register, O0 , (RegisterImpl::obase + 0));
1.126 +CONSTANT_REGISTER_DECLARATION(Register, O1 , (RegisterImpl::obase + 1));
1.127 +CONSTANT_REGISTER_DECLARATION(Register, O2 , (RegisterImpl::obase + 2));
1.128 +CONSTANT_REGISTER_DECLARATION(Register, O3 , (RegisterImpl::obase + 3));
1.129 +CONSTANT_REGISTER_DECLARATION(Register, O4 , (RegisterImpl::obase + 4));
1.130 +CONSTANT_REGISTER_DECLARATION(Register, O5 , (RegisterImpl::obase + 5));
1.131 +CONSTANT_REGISTER_DECLARATION(Register, O6 , (RegisterImpl::obase + 6));
1.132 +CONSTANT_REGISTER_DECLARATION(Register, O7 , (RegisterImpl::obase + 7));
1.133 +
1.134 +CONSTANT_REGISTER_DECLARATION(Register, L0 , (RegisterImpl::lbase + 0));
1.135 +CONSTANT_REGISTER_DECLARATION(Register, L1 , (RegisterImpl::lbase + 1));
1.136 +CONSTANT_REGISTER_DECLARATION(Register, L2 , (RegisterImpl::lbase + 2));
1.137 +CONSTANT_REGISTER_DECLARATION(Register, L3 , (RegisterImpl::lbase + 3));
1.138 +CONSTANT_REGISTER_DECLARATION(Register, L4 , (RegisterImpl::lbase + 4));
1.139 +CONSTANT_REGISTER_DECLARATION(Register, L5 , (RegisterImpl::lbase + 5));
1.140 +CONSTANT_REGISTER_DECLARATION(Register, L6 , (RegisterImpl::lbase + 6));
1.141 +CONSTANT_REGISTER_DECLARATION(Register, L7 , (RegisterImpl::lbase + 7));
1.142 +
1.143 +CONSTANT_REGISTER_DECLARATION(Register, I0 , (RegisterImpl::ibase + 0));
1.144 +CONSTANT_REGISTER_DECLARATION(Register, I1 , (RegisterImpl::ibase + 1));
1.145 +CONSTANT_REGISTER_DECLARATION(Register, I2 , (RegisterImpl::ibase + 2));
1.146 +CONSTANT_REGISTER_DECLARATION(Register, I3 , (RegisterImpl::ibase + 3));
1.147 +CONSTANT_REGISTER_DECLARATION(Register, I4 , (RegisterImpl::ibase + 4));
1.148 +CONSTANT_REGISTER_DECLARATION(Register, I5 , (RegisterImpl::ibase + 5));
1.149 +CONSTANT_REGISTER_DECLARATION(Register, I6 , (RegisterImpl::ibase + 6));
1.150 +CONSTANT_REGISTER_DECLARATION(Register, I7 , (RegisterImpl::ibase + 7));
1.151 +
1.152 +CONSTANT_REGISTER_DECLARATION(Register, FP , (RegisterImpl::ibase + 6));
1.153 +CONSTANT_REGISTER_DECLARATION(Register, SP , (RegisterImpl::obase + 6));
1.154 +
1.155 +//
1.156 +// Because sparc has so many registers, #define'ing values for the is
1.157 +// beneficial in code size and the cost of some of the dangers of
1.158 +// defines. We don't use them on Intel because win32 uses asm
1.159 +// directives which use the same names for registers as Hotspot does,
1.160 +// so #defines would screw up the inline assembly. If a particular
1.161 +// file has a problem with these defines then it's possible to turn
1.162 +// them off in that file by defining DONT_USE_REGISTER_DEFINES.
1.163 +// register_definition_sparc.cpp does that so that it's able to
1.164 +// provide real definitions of these registers for use in debuggers
1.165 +// and such.
1.166 +//
1.167 +
1.168 +#ifndef DONT_USE_REGISTER_DEFINES
1.169 +#define noreg ((Register)(noreg_RegisterEnumValue))
1.170 +
1.171 +#define G0 ((Register)(G0_RegisterEnumValue))
1.172 +#define G1 ((Register)(G1_RegisterEnumValue))
1.173 +#define G2 ((Register)(G2_RegisterEnumValue))
1.174 +#define G3 ((Register)(G3_RegisterEnumValue))
1.175 +#define G4 ((Register)(G4_RegisterEnumValue))
1.176 +#define G5 ((Register)(G5_RegisterEnumValue))
1.177 +#define G6 ((Register)(G6_RegisterEnumValue))
1.178 +#define G7 ((Register)(G7_RegisterEnumValue))
1.179 +
1.180 +#define O0 ((Register)(O0_RegisterEnumValue))
1.181 +#define O1 ((Register)(O1_RegisterEnumValue))
1.182 +#define O2 ((Register)(O2_RegisterEnumValue))
1.183 +#define O3 ((Register)(O3_RegisterEnumValue))
1.184 +#define O4 ((Register)(O4_RegisterEnumValue))
1.185 +#define O5 ((Register)(O5_RegisterEnumValue))
1.186 +#define O6 ((Register)(O6_RegisterEnumValue))
1.187 +#define O7 ((Register)(O7_RegisterEnumValue))
1.188 +
1.189 +#define L0 ((Register)(L0_RegisterEnumValue))
1.190 +#define L1 ((Register)(L1_RegisterEnumValue))
1.191 +#define L2 ((Register)(L2_RegisterEnumValue))
1.192 +#define L3 ((Register)(L3_RegisterEnumValue))
1.193 +#define L4 ((Register)(L4_RegisterEnumValue))
1.194 +#define L5 ((Register)(L5_RegisterEnumValue))
1.195 +#define L6 ((Register)(L6_RegisterEnumValue))
1.196 +#define L7 ((Register)(L7_RegisterEnumValue))
1.197 +
1.198 +#define I0 ((Register)(I0_RegisterEnumValue))
1.199 +#define I1 ((Register)(I1_RegisterEnumValue))
1.200 +#define I2 ((Register)(I2_RegisterEnumValue))
1.201 +#define I3 ((Register)(I3_RegisterEnumValue))
1.202 +#define I4 ((Register)(I4_RegisterEnumValue))
1.203 +#define I5 ((Register)(I5_RegisterEnumValue))
1.204 +#define I6 ((Register)(I6_RegisterEnumValue))
1.205 +#define I7 ((Register)(I7_RegisterEnumValue))
1.206 +
1.207 +#define FP ((Register)(FP_RegisterEnumValue))
1.208 +#define SP ((Register)(SP_RegisterEnumValue))
1.209 +#endif // DONT_USE_REGISTER_DEFINES
1.210 +
1.211 +// Use FloatRegister as shortcut
1.212 +class FloatRegisterImpl;
1.213 +typedef FloatRegisterImpl* FloatRegister;
1.214 +
1.215 +
1.216 +// construction
1.217 +inline FloatRegister as_FloatRegister(int encoding) {
1.218 + return (FloatRegister)(intptr_t)encoding;
1.219 +}
1.220 +
1.221 +// The implementation of float registers for the SPARC architecture
1.222 +
1.223 +class FloatRegisterImpl: public AbstractRegisterImpl {
1.224 + public:
1.225 + enum {
1.226 + number_of_registers = 64
1.227 + };
1.228 +
1.229 + enum Width {
1.230 + S = 1, D = 2, Q = 3
1.231 + };
1.232 +
1.233 + // construction
1.234 + VMReg as_VMReg( );
1.235 +
1.236 + // accessors
1.237 + int encoding() const { assert(is_valid(), "invalid register"); return value(); }
1.238 +
1.239 + public:
1.240 + int encoding(Width w) const {
1.241 + const int c = encoding();
1.242 + switch (w) {
1.243 + case S:
1.244 + assert(c < 32, "bad single float register");
1.245 + return c;
1.246 +
1.247 + case D:
1.248 + assert(c < 64 && (c & 1) == 0, "bad double float register");
1.249 + assert(c < 32 || VM_Version::v9_instructions_work(), "V9 float work only on V9 platform");
1.250 + return (c & 0x1e) | ((c & 0x20) >> 5);
1.251 +
1.252 + case Q:
1.253 + assert(c < 64 && (c & 3) == 0, "bad quad float register");
1.254 + assert(c < 32 || VM_Version::v9_instructions_work(), "V9 float work only on V9 platform");
1.255 + return (c & 0x1c) | ((c & 0x20) >> 5);
1.256 + }
1.257 + ShouldNotReachHere();
1.258 + return -1;
1.259 + }
1.260 +
1.261 + bool is_valid() const { return 0 <= value() && value() < number_of_registers; }
1.262 + const char* name() const;
1.263 +
1.264 + FloatRegister successor() const { return as_FloatRegister(encoding() + 1); }
1.265 +};
1.266 +
1.267 +
1.268 +// The float registers of the SPARC architecture
1.269 +
1.270 +CONSTANT_REGISTER_DECLARATION(FloatRegister, fnoreg , (-1));
1.271 +
1.272 +CONSTANT_REGISTER_DECLARATION(FloatRegister, F0 , ( 0));
1.273 +CONSTANT_REGISTER_DECLARATION(FloatRegister, F1 , ( 1));
1.274 +CONSTANT_REGISTER_DECLARATION(FloatRegister, F2 , ( 2));
1.275 +CONSTANT_REGISTER_DECLARATION(FloatRegister, F3 , ( 3));
1.276 +CONSTANT_REGISTER_DECLARATION(FloatRegister, F4 , ( 4));
1.277 +CONSTANT_REGISTER_DECLARATION(FloatRegister, F5 , ( 5));
1.278 +CONSTANT_REGISTER_DECLARATION(FloatRegister, F6 , ( 6));
1.279 +CONSTANT_REGISTER_DECLARATION(FloatRegister, F7 , ( 7));
1.280 +CONSTANT_REGISTER_DECLARATION(FloatRegister, F8 , ( 8));
1.281 +CONSTANT_REGISTER_DECLARATION(FloatRegister, F9 , ( 9));
1.282 +CONSTANT_REGISTER_DECLARATION(FloatRegister, F10 , (10));
1.283 +CONSTANT_REGISTER_DECLARATION(FloatRegister, F11 , (11));
1.284 +CONSTANT_REGISTER_DECLARATION(FloatRegister, F12 , (12));
1.285 +CONSTANT_REGISTER_DECLARATION(FloatRegister, F13 , (13));
1.286 +CONSTANT_REGISTER_DECLARATION(FloatRegister, F14 , (14));
1.287 +CONSTANT_REGISTER_DECLARATION(FloatRegister, F15 , (15));
1.288 +CONSTANT_REGISTER_DECLARATION(FloatRegister, F16 , (16));
1.289 +CONSTANT_REGISTER_DECLARATION(FloatRegister, F17 , (17));
1.290 +CONSTANT_REGISTER_DECLARATION(FloatRegister, F18 , (18));
1.291 +CONSTANT_REGISTER_DECLARATION(FloatRegister, F19 , (19));
1.292 +CONSTANT_REGISTER_DECLARATION(FloatRegister, F20 , (20));
1.293 +CONSTANT_REGISTER_DECLARATION(FloatRegister, F21 , (21));
1.294 +CONSTANT_REGISTER_DECLARATION(FloatRegister, F22 , (22));
1.295 +CONSTANT_REGISTER_DECLARATION(FloatRegister, F23 , (23));
1.296 +CONSTANT_REGISTER_DECLARATION(FloatRegister, F24 , (24));
1.297 +CONSTANT_REGISTER_DECLARATION(FloatRegister, F25 , (25));
1.298 +CONSTANT_REGISTER_DECLARATION(FloatRegister, F26 , (26));
1.299 +CONSTANT_REGISTER_DECLARATION(FloatRegister, F27 , (27));
1.300 +CONSTANT_REGISTER_DECLARATION(FloatRegister, F28 , (28));
1.301 +CONSTANT_REGISTER_DECLARATION(FloatRegister, F29 , (29));
1.302 +CONSTANT_REGISTER_DECLARATION(FloatRegister, F30 , (30));
1.303 +CONSTANT_REGISTER_DECLARATION(FloatRegister, F31 , (31));
1.304 +
1.305 +CONSTANT_REGISTER_DECLARATION(FloatRegister, F32 , (32));
1.306 +CONSTANT_REGISTER_DECLARATION(FloatRegister, F34 , (34));
1.307 +CONSTANT_REGISTER_DECLARATION(FloatRegister, F36 , (36));
1.308 +CONSTANT_REGISTER_DECLARATION(FloatRegister, F38 , (38));
1.309 +CONSTANT_REGISTER_DECLARATION(FloatRegister, F40 , (40));
1.310 +CONSTANT_REGISTER_DECLARATION(FloatRegister, F42 , (42));
1.311 +CONSTANT_REGISTER_DECLARATION(FloatRegister, F44 , (44));
1.312 +CONSTANT_REGISTER_DECLARATION(FloatRegister, F46 , (46));
1.313 +CONSTANT_REGISTER_DECLARATION(FloatRegister, F48 , (48));
1.314 +CONSTANT_REGISTER_DECLARATION(FloatRegister, F50 , (50));
1.315 +CONSTANT_REGISTER_DECLARATION(FloatRegister, F52 , (52));
1.316 +CONSTANT_REGISTER_DECLARATION(FloatRegister, F54 , (54));
1.317 +CONSTANT_REGISTER_DECLARATION(FloatRegister, F56 , (56));
1.318 +CONSTANT_REGISTER_DECLARATION(FloatRegister, F58 , (58));
1.319 +CONSTANT_REGISTER_DECLARATION(FloatRegister, F60 , (60));
1.320 +CONSTANT_REGISTER_DECLARATION(FloatRegister, F62 , (62));
1.321 +
1.322 +
1.323 +#ifndef DONT_USE_REGISTER_DEFINES
1.324 +#define fnoreg ((FloatRegister)(fnoreg_FloatRegisterEnumValue))
1.325 +#define F0 ((FloatRegister)( F0_FloatRegisterEnumValue))
1.326 +#define F1 ((FloatRegister)( F1_FloatRegisterEnumValue))
1.327 +#define F2 ((FloatRegister)( F2_FloatRegisterEnumValue))
1.328 +#define F3 ((FloatRegister)( F3_FloatRegisterEnumValue))
1.329 +#define F4 ((FloatRegister)( F4_FloatRegisterEnumValue))
1.330 +#define F5 ((FloatRegister)( F5_FloatRegisterEnumValue))
1.331 +#define F6 ((FloatRegister)( F6_FloatRegisterEnumValue))
1.332 +#define F7 ((FloatRegister)( F7_FloatRegisterEnumValue))
1.333 +#define F8 ((FloatRegister)( F8_FloatRegisterEnumValue))
1.334 +#define F9 ((FloatRegister)( F9_FloatRegisterEnumValue))
1.335 +#define F10 ((FloatRegister)( F10_FloatRegisterEnumValue))
1.336 +#define F11 ((FloatRegister)( F11_FloatRegisterEnumValue))
1.337 +#define F12 ((FloatRegister)( F12_FloatRegisterEnumValue))
1.338 +#define F13 ((FloatRegister)( F13_FloatRegisterEnumValue))
1.339 +#define F14 ((FloatRegister)( F14_FloatRegisterEnumValue))
1.340 +#define F15 ((FloatRegister)( F15_FloatRegisterEnumValue))
1.341 +#define F16 ((FloatRegister)( F16_FloatRegisterEnumValue))
1.342 +#define F17 ((FloatRegister)( F17_FloatRegisterEnumValue))
1.343 +#define F18 ((FloatRegister)( F18_FloatRegisterEnumValue))
1.344 +#define F19 ((FloatRegister)( F19_FloatRegisterEnumValue))
1.345 +#define F20 ((FloatRegister)( F20_FloatRegisterEnumValue))
1.346 +#define F21 ((FloatRegister)( F21_FloatRegisterEnumValue))
1.347 +#define F22 ((FloatRegister)( F22_FloatRegisterEnumValue))
1.348 +#define F23 ((FloatRegister)( F23_FloatRegisterEnumValue))
1.349 +#define F24 ((FloatRegister)( F24_FloatRegisterEnumValue))
1.350 +#define F25 ((FloatRegister)( F25_FloatRegisterEnumValue))
1.351 +#define F26 ((FloatRegister)( F26_FloatRegisterEnumValue))
1.352 +#define F27 ((FloatRegister)( F27_FloatRegisterEnumValue))
1.353 +#define F28 ((FloatRegister)( F28_FloatRegisterEnumValue))
1.354 +#define F29 ((FloatRegister)( F29_FloatRegisterEnumValue))
1.355 +#define F30 ((FloatRegister)( F30_FloatRegisterEnumValue))
1.356 +#define F31 ((FloatRegister)( F31_FloatRegisterEnumValue))
1.357 +#define F32 ((FloatRegister)( F32_FloatRegisterEnumValue))
1.358 +#define F34 ((FloatRegister)( F34_FloatRegisterEnumValue))
1.359 +#define F36 ((FloatRegister)( F36_FloatRegisterEnumValue))
1.360 +#define F38 ((FloatRegister)( F38_FloatRegisterEnumValue))
1.361 +#define F40 ((FloatRegister)( F40_FloatRegisterEnumValue))
1.362 +#define F42 ((FloatRegister)( F42_FloatRegisterEnumValue))
1.363 +#define F44 ((FloatRegister)( F44_FloatRegisterEnumValue))
1.364 +#define F46 ((FloatRegister)( F46_FloatRegisterEnumValue))
1.365 +#define F48 ((FloatRegister)( F48_FloatRegisterEnumValue))
1.366 +#define F50 ((FloatRegister)( F50_FloatRegisterEnumValue))
1.367 +#define F52 ((FloatRegister)( F52_FloatRegisterEnumValue))
1.368 +#define F54 ((FloatRegister)( F54_FloatRegisterEnumValue))
1.369 +#define F56 ((FloatRegister)( F56_FloatRegisterEnumValue))
1.370 +#define F58 ((FloatRegister)( F58_FloatRegisterEnumValue))
1.371 +#define F60 ((FloatRegister)( F60_FloatRegisterEnumValue))
1.372 +#define F62 ((FloatRegister)( F62_FloatRegisterEnumValue))
1.373 +#endif // DONT_USE_REGISTER_DEFINES
1.374 +
1.375 +// Maximum number of incoming arguments that can be passed in i registers.
1.376 +const int SPARC_ARGS_IN_REGS_NUM = 6;
1.377 +
1.378 +class ConcreteRegisterImpl : public AbstractRegisterImpl {
1.379 + public:
1.380 + enum {
1.381 + // This number must be large enough to cover REG_COUNT (defined by c2) registers.
1.382 + // There is no requirement that any ordering here matches any ordering c2 gives
1.383 + // it's optoregs.
1.384 + number_of_registers = 2*RegisterImpl::number_of_registers +
1.385 + FloatRegisterImpl::number_of_registers +
1.386 + 1 + // ccr
1.387 + 4 // fcc
1.388 + };
1.389 + static const int max_gpr;
1.390 + static const int max_fpr;
1.391 +
1.392 +};
1.393 +
1.394 +// Single, Double and Quad fp reg classes. These exist to map the ADLC
1.395 +// encoding for a floating point register, to the FloatRegister number
1.396 +// desired by the macroassembler. A FloatRegister is a number between
1.397 +// 0 and 63 passed around as a pointer. For ADLC, an fp register encoding
1.398 +// is the actual bit encoding used by the sparc hardware. When ADLC used
1.399 +// the macroassembler to generate an instruction that references, e.g., a
1.400 +// double fp reg, it passed the bit encoding to the macroassembler via
1.401 +// as_FloatRegister, which, for double regs > 30, returns an illegal
1.402 +// register number.
1.403 +//
1.404 +// Therefore we provide the following classes for use by ADLC. Their
1.405 +// sole purpose is to convert from sparc register encodings to FloatRegisters.
1.406 +// At some future time, we might replace FloatRegister with these classes,
1.407 +// hence the definitions of as_xxxFloatRegister as class methods rather
1.408 +// than as external inline routines.
1.409 +
1.410 +class SingleFloatRegisterImpl;
1.411 +typedef SingleFloatRegisterImpl *SingleFloatRegister;
1.412 +
1.413 +inline FloatRegister as_SingleFloatRegister(int encoding);
1.414 +class SingleFloatRegisterImpl {
1.415 + public:
1.416 + friend inline FloatRegister as_SingleFloatRegister(int encoding) {
1.417 + assert(encoding < 32, "bad single float register encoding");
1.418 + return as_FloatRegister(encoding);
1.419 + }
1.420 +};
1.421 +
1.422 +
1.423 +class DoubleFloatRegisterImpl;
1.424 +typedef DoubleFloatRegisterImpl *DoubleFloatRegister;
1.425 +
1.426 +inline FloatRegister as_DoubleFloatRegister(int encoding);
1.427 +class DoubleFloatRegisterImpl {
1.428 + public:
1.429 + friend inline FloatRegister as_DoubleFloatRegister(int encoding) {
1.430 + assert(encoding < 32, "bad double float register encoding");
1.431 + return as_FloatRegister( ((encoding & 1) << 5) | (encoding & 0x1e) );
1.432 + }
1.433 +};
1.434 +
1.435 +
1.436 +class QuadFloatRegisterImpl;
1.437 +typedef QuadFloatRegisterImpl *QuadFloatRegister;
1.438 +
1.439 +class QuadFloatRegisterImpl {
1.440 + public:
1.441 + friend FloatRegister as_QuadFloatRegister(int encoding) {
1.442 + assert(encoding < 32 && ((encoding & 2) == 0), "bad quad float register encoding");
1.443 + return as_FloatRegister( ((encoding & 1) << 5) | (encoding & 0x1c) );
1.444 + }
1.445 +};
