1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/src/cpu/sparc/vm/icBuffer_sparc.cpp Sat Dec 01 00:00:00 2007 +0000
1.3 @@ -0,0 +1,73 @@
1.4 +/*
1.5 + * Copyright 1997-2006 Sun Microsystems, Inc. All Rights Reserved.
1.6 + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
1.7 + *
1.8 + * This code is free software; you can redistribute it and/or modify it
1.9 + * under the terms of the GNU General Public License version 2 only, as
1.10 + * published by the Free Software Foundation.
1.11 + *
1.12 + * This code is distributed in the hope that it will be useful, but WITHOUT
1.13 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1.14 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1.15 + * version 2 for more details (a copy is included in the LICENSE file that
1.16 + * accompanied this code).
1.17 + *
1.18 + * You should have received a copy of the GNU General Public License version
1.19 + * 2 along with this work; if not, write to the Free Software Foundation,
1.20 + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
1.21 + *
1.22 + * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
1.23 + * CA 95054 USA or visit www.sun.com if you need additional information or
1.24 + * have any questions.
1.25 + *
1.26 + */
1.27 +
1.28 +#include "incls/_precompiled.incl"
1.29 +#include "incls/_icBuffer_sparc.cpp.incl"
1.30 +
1.31 +int InlineCacheBuffer::ic_stub_code_size() {
1.32 +#ifdef _LP64
1.33 + if (TraceJumps) return 600 * wordSize;
1.34 + return (NativeMovConstReg::instruction_size + // sethi;add
1.35 + NativeJump::instruction_size + // sethi; jmp; delay slot
1.36 + (1*BytesPerInstWord) + 1); // flush + 1 extra byte
1.37 +#else
1.38 + if (TraceJumps) return 300 * wordSize;
1.39 + return (2+2+ 1) * wordSize + 1; // set/jump_to/nop + 1 byte so that code_end can be set in CodeBuffer
1.40 +#endif
1.41 +}
1.42 +
1.43 +void InlineCacheBuffer::assemble_ic_buffer_code(address code_begin, oop cached_oop, address entry_point) {
1.44 + ResourceMark rm;
1.45 + CodeBuffer code(code_begin, ic_stub_code_size());
1.46 + MacroAssembler* masm = new MacroAssembler(&code);
1.47 + // note: even though the code contains an embedded oop, we do not need reloc info
1.48 + // because
1.49 + // (1) the oop is old (i.e., doesn't matter for scavenges)
1.50 + // (2) these ICStubs are removed *before* a GC happens, so the roots disappear
1.51 + assert(cached_oop == NULL || cached_oop->is_perm(), "must be old oop");
1.52 + Address cached_oop_addr(G5_inline_cache_reg, address(cached_oop));
1.53 + // Force the sethi to generate the fixed sequence so next_instruction_address works
1.54 + masm->sethi(cached_oop_addr, true /* ForceRelocatable */ );
1.55 + masm->add(cached_oop_addr, G5_inline_cache_reg);
1.56 + assert(G3_scratch != G5_method, "Do not clobber the method oop in the transition stub");
1.57 + assert(G3_scratch != G5_inline_cache_reg, "Do not clobber the inline cache register in the transition stub");
1.58 + Address entry(G3_scratch, entry_point);
1.59 + masm->JUMP(entry, 0);
1.60 + masm->delayed()->nop();
1.61 + masm->flush();
1.62 +}
1.63 +
1.64 +
1.65 +address InlineCacheBuffer::ic_buffer_entry_point(address code_begin) {
1.66 + NativeMovConstReg* move = nativeMovConstReg_at(code_begin); // creation also verifies the object
1.67 + NativeJump* jump = nativeJump_at(move->next_instruction_address());
1.68 + return jump->jump_destination();
1.69 +}
1.70 +
1.71 +
1.72 +oop InlineCacheBuffer::ic_buffer_cached_oop(address code_begin) {
1.73 + NativeMovConstReg* move = nativeMovConstReg_at(code_begin); // creation also verifies the object
1.74 + NativeJump* jump = nativeJump_at(move->next_instruction_address());
1.75 + return (oop)move->data();
1.76 +}
