1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/src/cpu/sparc/vm/c1_LIRAssembler_sparc.hpp Sat Dec 01 00:00:00 2007 +0000
1.3 @@ -0,0 +1,85 @@
1.4 +/*
1.5 + * Copyright 2000-2006 Sun Microsystems, Inc. All Rights Reserved.
1.6 + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
1.7 + *
1.8 + * This code is free software; you can redistribute it and/or modify it
1.9 + * under the terms of the GNU General Public License version 2 only, as
1.10 + * published by the Free Software Foundation.
1.11 + *
1.12 + * This code is distributed in the hope that it will be useful, but WITHOUT
1.13 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1.14 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1.15 + * version 2 for more details (a copy is included in the LICENSE file that
1.16 + * accompanied this code).
1.17 + *
1.18 + * You should have received a copy of the GNU General Public License version
1.19 + * 2 along with this work; if not, write to the Free Software Foundation,
1.20 + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
1.21 + *
1.22 + * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
1.23 + * CA 95054 USA or visit www.sun.com if you need additional information or
1.24 + * have any questions.
1.25 + *
1.26 + */
1.27 +
1.28 + private:
1.29 +
1.30 + //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
1.31 + //
1.32 + // Sparc load/store emission
1.33 + //
1.34 + // The sparc ld/st instructions cannot accomodate displacements > 13 bits long.
1.35 + // The following "pseudo" sparc instructions (load/store) make it easier to use the indexed addressing mode
1.36 + // by allowing 32 bit displacements:
1.37 + //
1.38 + // When disp <= 13 bits long, a single load or store instruction is emitted with (disp + [d]).
1.39 + // When disp > 13 bits long, code is emitted to set the displacement into the O7 register,
1.40 + // and then a load or store is emitted with ([O7] + [d]).
1.41 + //
1.42 +
1.43 + // some load/store variants return the code_offset for proper positioning of debug info for null checks
1.44 +
1.45 + // load/store with 32 bit displacement
1.46 + int load(Register s, int disp, Register d, BasicType ld_type, CodeEmitInfo* info = NULL);
1.47 + void store(Register value, Register base, int offset, BasicType type, CodeEmitInfo *info = NULL);
1.48 +
1.49 + // loadf/storef with 32 bit displacement
1.50 + void load(Register s, int disp, FloatRegister d, BasicType ld_type, CodeEmitInfo* info = NULL);
1.51 + void store(FloatRegister d, Register s1, int disp, BasicType st_type, CodeEmitInfo* info = NULL);
1.52 +
1.53 + // convienence methods for calling load/store with an Address
1.54 + void load(const Address& a, Register d, BasicType ld_type, CodeEmitInfo* info = NULL, int offset = 0);
1.55 + void store(Register d, const Address& a, BasicType st_type, CodeEmitInfo* info = NULL, int offset = 0);
1.56 + void load(const Address& a, FloatRegister d, BasicType ld_type, CodeEmitInfo* info = NULL, int offset = 0);
1.57 + void store(FloatRegister d, const Address& a, BasicType st_type, CodeEmitInfo* info = NULL, int offset = 0);
1.58 +
1.59 + // convienence methods for calling load/store with an LIR_Address
1.60 + void load(LIR_Address* a, Register d, BasicType ld_type, CodeEmitInfo* info = NULL);
1.61 + void store(Register d, LIR_Address* a, BasicType st_type, CodeEmitInfo* info = NULL);
1.62 + void load(LIR_Address* a, FloatRegister d, BasicType ld_type, CodeEmitInfo* info = NULL);
1.63 + void store(FloatRegister d, LIR_Address* a, BasicType st_type, CodeEmitInfo* info = NULL);
1.64 +
1.65 + int store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool unaligned = false);
1.66 + int store(LIR_Opr from_reg, Register base, Register disp, BasicType type);
1.67 +
1.68 + int load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool unaligned = false);
1.69 + int load(Register base, Register disp, LIR_Opr to_reg, BasicType type);
1.70 +
1.71 + void monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no);
1.72 +
1.73 + int shift_amount(BasicType t);
1.74 +
1.75 + static bool is_single_instruction(LIR_Op* op);
1.76 +
1.77 + public:
1.78 + void pack64( Register rs, Register rd );
1.79 + void unpack64( Register rd );
1.80 +
1.81 +enum {
1.82 +#ifdef _LP64
1.83 + call_stub_size = 68,
1.84 +#else
1.85 + call_stub_size = 20,
1.86 +#endif // _LP64
1.87 + exception_handler_size = DEBUG_ONLY(1*K) NOT_DEBUG(10*4),
1.88 + deopt_handler_size = DEBUG_ONLY(1*K) NOT_DEBUG(10*4) };
