1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/src/cpu/sparc/vm/c1_FrameMap_sparc.cpp Sat Dec 01 00:00:00 2007 +0000
1.3 @@ -0,0 +1,355 @@
1.4 +/*
1.5 + * Copyright 1999-2006 Sun Microsystems, Inc. All Rights Reserved.
1.6 + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
1.7 + *
1.8 + * This code is free software; you can redistribute it and/or modify it
1.9 + * under the terms of the GNU General Public License version 2 only, as
1.10 + * published by the Free Software Foundation.
1.11 + *
1.12 + * This code is distributed in the hope that it will be useful, but WITHOUT
1.13 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1.14 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1.15 + * version 2 for more details (a copy is included in the LICENSE file that
1.16 + * accompanied this code).
1.17 + *
1.18 + * You should have received a copy of the GNU General Public License version
1.19 + * 2 along with this work; if not, write to the Free Software Foundation,
1.20 + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
1.21 + *
1.22 + * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
1.23 + * CA 95054 USA or visit www.sun.com if you need additional information or
1.24 + * have any questions.
1.25 + *
1.26 + */
1.27 +
1.28 +# include "incls/_precompiled.incl"
1.29 +# include "incls/_c1_FrameMap_sparc.cpp.incl"
1.30 +
1.31 +
1.32 +const int FrameMap::pd_c_runtime_reserved_arg_size = 7;
1.33 +
1.34 +
1.35 +LIR_Opr FrameMap::map_to_opr(BasicType type, VMRegPair* reg, bool outgoing) {
1.36 + LIR_Opr opr = LIR_OprFact::illegalOpr;
1.37 + VMReg r_1 = reg->first();
1.38 + VMReg r_2 = reg->second();
1.39 + if (r_1->is_stack()) {
1.40 + // Convert stack slot to an SP offset
1.41 + // The calling convention does not count the SharedRuntime::out_preserve_stack_slots() value
1.42 + // so we must add it in here.
1.43 + int st_off = (r_1->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
1.44 + opr = LIR_OprFact::address(new LIR_Address(SP_opr, st_off + STACK_BIAS, type));
1.45 + } else if (r_1->is_Register()) {
1.46 + Register reg = r_1->as_Register();
1.47 + if (outgoing) {
1.48 + assert(!reg->is_in(), "should be using I regs");
1.49 + } else {
1.50 + assert(!reg->is_out(), "should be using O regs");
1.51 + }
1.52 + if (r_2->is_Register() && (type == T_LONG || type == T_DOUBLE)) {
1.53 + opr = as_long_opr(reg);
1.54 + } else if (type == T_OBJECT || type == T_ARRAY) {
1.55 + opr = as_oop_opr(reg);
1.56 + } else {
1.57 + opr = as_opr(reg);
1.58 + }
1.59 + } else if (r_1->is_FloatRegister()) {
1.60 + assert(type == T_DOUBLE || type == T_FLOAT, "wrong type");
1.61 + FloatRegister f = r_1->as_FloatRegister();
1.62 + if (type == T_DOUBLE) {
1.63 + opr = as_double_opr(f);
1.64 + } else {
1.65 + opr = as_float_opr(f);
1.66 + }
1.67 + }
1.68 + return opr;
1.69 +}
1.70 +
1.71 +// FrameMap
1.72 +//--------------------------------------------------------
1.73 +
1.74 +FloatRegister FrameMap::_fpu_regs [FrameMap::nof_fpu_regs];
1.75 +
1.76 +// some useful constant RInfo's:
1.77 +LIR_Opr FrameMap::in_long_opr;
1.78 +LIR_Opr FrameMap::out_long_opr;
1.79 +
1.80 +LIR_Opr FrameMap::F0_opr;
1.81 +LIR_Opr FrameMap::F0_double_opr;
1.82 +
1.83 +LIR_Opr FrameMap::G0_opr;
1.84 +LIR_Opr FrameMap::G1_opr;
1.85 +LIR_Opr FrameMap::G2_opr;
1.86 +LIR_Opr FrameMap::G3_opr;
1.87 +LIR_Opr FrameMap::G4_opr;
1.88 +LIR_Opr FrameMap::G5_opr;
1.89 +LIR_Opr FrameMap::G6_opr;
1.90 +LIR_Opr FrameMap::G7_opr;
1.91 +LIR_Opr FrameMap::O0_opr;
1.92 +LIR_Opr FrameMap::O1_opr;
1.93 +LIR_Opr FrameMap::O2_opr;
1.94 +LIR_Opr FrameMap::O3_opr;
1.95 +LIR_Opr FrameMap::O4_opr;
1.96 +LIR_Opr FrameMap::O5_opr;
1.97 +LIR_Opr FrameMap::O6_opr;
1.98 +LIR_Opr FrameMap::O7_opr;
1.99 +LIR_Opr FrameMap::L0_opr;
1.100 +LIR_Opr FrameMap::L1_opr;
1.101 +LIR_Opr FrameMap::L2_opr;
1.102 +LIR_Opr FrameMap::L3_opr;
1.103 +LIR_Opr FrameMap::L4_opr;
1.104 +LIR_Opr FrameMap::L5_opr;
1.105 +LIR_Opr FrameMap::L6_opr;
1.106 +LIR_Opr FrameMap::L7_opr;
1.107 +LIR_Opr FrameMap::I0_opr;
1.108 +LIR_Opr FrameMap::I1_opr;
1.109 +LIR_Opr FrameMap::I2_opr;
1.110 +LIR_Opr FrameMap::I3_opr;
1.111 +LIR_Opr FrameMap::I4_opr;
1.112 +LIR_Opr FrameMap::I5_opr;
1.113 +LIR_Opr FrameMap::I6_opr;
1.114 +LIR_Opr FrameMap::I7_opr;
1.115 +
1.116 +LIR_Opr FrameMap::G0_oop_opr;
1.117 +LIR_Opr FrameMap::G1_oop_opr;
1.118 +LIR_Opr FrameMap::G2_oop_opr;
1.119 +LIR_Opr FrameMap::G3_oop_opr;
1.120 +LIR_Opr FrameMap::G4_oop_opr;
1.121 +LIR_Opr FrameMap::G5_oop_opr;
1.122 +LIR_Opr FrameMap::G6_oop_opr;
1.123 +LIR_Opr FrameMap::G7_oop_opr;
1.124 +LIR_Opr FrameMap::O0_oop_opr;
1.125 +LIR_Opr FrameMap::O1_oop_opr;
1.126 +LIR_Opr FrameMap::O2_oop_opr;
1.127 +LIR_Opr FrameMap::O3_oop_opr;
1.128 +LIR_Opr FrameMap::O4_oop_opr;
1.129 +LIR_Opr FrameMap::O5_oop_opr;
1.130 +LIR_Opr FrameMap::O6_oop_opr;
1.131 +LIR_Opr FrameMap::O7_oop_opr;
1.132 +LIR_Opr FrameMap::L0_oop_opr;
1.133 +LIR_Opr FrameMap::L1_oop_opr;
1.134 +LIR_Opr FrameMap::L2_oop_opr;
1.135 +LIR_Opr FrameMap::L3_oop_opr;
1.136 +LIR_Opr FrameMap::L4_oop_opr;
1.137 +LIR_Opr FrameMap::L5_oop_opr;
1.138 +LIR_Opr FrameMap::L6_oop_opr;
1.139 +LIR_Opr FrameMap::L7_oop_opr;
1.140 +LIR_Opr FrameMap::I0_oop_opr;
1.141 +LIR_Opr FrameMap::I1_oop_opr;
1.142 +LIR_Opr FrameMap::I2_oop_opr;
1.143 +LIR_Opr FrameMap::I3_oop_opr;
1.144 +LIR_Opr FrameMap::I4_oop_opr;
1.145 +LIR_Opr FrameMap::I5_oop_opr;
1.146 +LIR_Opr FrameMap::I6_oop_opr;
1.147 +LIR_Opr FrameMap::I7_oop_opr;
1.148 +
1.149 +LIR_Opr FrameMap::SP_opr;
1.150 +LIR_Opr FrameMap::FP_opr;
1.151 +
1.152 +LIR_Opr FrameMap::Oexception_opr;
1.153 +LIR_Opr FrameMap::Oissuing_pc_opr;
1.154 +
1.155 +LIR_Opr FrameMap::_caller_save_cpu_regs[] = { 0, };
1.156 +LIR_Opr FrameMap::_caller_save_fpu_regs[] = { 0, };
1.157 +
1.158 +
1.159 +FloatRegister FrameMap::nr2floatreg (int rnr) {
1.160 + assert(_init_done, "tables not initialized");
1.161 + debug_only(fpu_range_check(rnr);)
1.162 + return _fpu_regs[rnr];
1.163 +}
1.164 +
1.165 +
1.166 +// returns true if reg could be smashed by a callee.
1.167 +bool FrameMap::is_caller_save_register (LIR_Opr reg) {
1.168 + if (reg->is_single_fpu() || reg->is_double_fpu()) { return true; }
1.169 + if (reg->is_double_cpu()) {
1.170 + return is_caller_save_register(reg->as_register_lo()) ||
1.171 + is_caller_save_register(reg->as_register_hi());
1.172 + }
1.173 + return is_caller_save_register(reg->as_register());
1.174 +}
1.175 +
1.176 +
1.177 +NEEDS_CLEANUP // once the new calling convention is enabled, we no
1.178 + // longer need to treat I5, I4 and L0 specially
1.179 +// Because the interpreter destroys caller's I5, I4 and L0,
1.180 +// we must spill them before doing a Java call as we may land in
1.181 +// interpreter.
1.182 +bool FrameMap::is_caller_save_register (Register r) {
1.183 + return (r->is_global() && (r != G0)) || r->is_out();
1.184 +}
1.185 +
1.186 +
1.187 +void FrameMap::init () {
1.188 + if (_init_done) return;
1.189 +
1.190 + int i=0;
1.191 + // Register usage:
1.192 + // O6: sp
1.193 + // I6: fp
1.194 + // I7: return address
1.195 + // G0: zero
1.196 + // G2: thread
1.197 + // G7: not available
1.198 + // G6: not available
1.199 + /* 0 */ map_register(i++, L0);
1.200 + /* 1 */ map_register(i++, L1);
1.201 + /* 2 */ map_register(i++, L2);
1.202 + /* 3 */ map_register(i++, L3);
1.203 + /* 4 */ map_register(i++, L4);
1.204 + /* 5 */ map_register(i++, L5);
1.205 + /* 6 */ map_register(i++, L6);
1.206 + /* 7 */ map_register(i++, L7);
1.207 +
1.208 + /* 8 */ map_register(i++, I0);
1.209 + /* 9 */ map_register(i++, I1);
1.210 + /* 10 */ map_register(i++, I2);
1.211 + /* 11 */ map_register(i++, I3);
1.212 + /* 12 */ map_register(i++, I4);
1.213 + /* 13 */ map_register(i++, I5);
1.214 + /* 14 */ map_register(i++, O0);
1.215 + /* 15 */ map_register(i++, O1);
1.216 + /* 16 */ map_register(i++, O2);
1.217 + /* 17 */ map_register(i++, O3);
1.218 + /* 18 */ map_register(i++, O4);
1.219 + /* 19 */ map_register(i++, O5); // <- last register visible in RegAlloc (RegAlloc::nof+cpu_regs)
1.220 + /* 20 */ map_register(i++, G1);
1.221 + /* 21 */ map_register(i++, G3);
1.222 + /* 22 */ map_register(i++, G4);
1.223 + /* 23 */ map_register(i++, G5);
1.224 + /* 24 */ map_register(i++, G0);
1.225 +
1.226 + // the following registers are not normally available
1.227 + /* 25 */ map_register(i++, O7);
1.228 + /* 26 */ map_register(i++, G2);
1.229 + /* 27 */ map_register(i++, O6);
1.230 + /* 28 */ map_register(i++, I6);
1.231 + /* 29 */ map_register(i++, I7);
1.232 + /* 30 */ map_register(i++, G6);
1.233 + /* 31 */ map_register(i++, G7);
1.234 + assert(i == nof_cpu_regs, "number of CPU registers");
1.235 +
1.236 + for (i = 0; i < nof_fpu_regs; i++) {
1.237 + _fpu_regs[i] = as_FloatRegister(i);
1.238 + }
1.239 +
1.240 + _init_done = true;
1.241 +
1.242 + in_long_opr = as_long_opr(I0);
1.243 + out_long_opr = as_long_opr(O0);
1.244 +
1.245 + G0_opr = as_opr(G0);
1.246 + G1_opr = as_opr(G1);
1.247 + G2_opr = as_opr(G2);
1.248 + G3_opr = as_opr(G3);
1.249 + G4_opr = as_opr(G4);
1.250 + G5_opr = as_opr(G5);
1.251 + G6_opr = as_opr(G6);
1.252 + G7_opr = as_opr(G7);
1.253 + O0_opr = as_opr(O0);
1.254 + O1_opr = as_opr(O1);
1.255 + O2_opr = as_opr(O2);
1.256 + O3_opr = as_opr(O3);
1.257 + O4_opr = as_opr(O4);
1.258 + O5_opr = as_opr(O5);
1.259 + O6_opr = as_opr(O6);
1.260 + O7_opr = as_opr(O7);
1.261 + L0_opr = as_opr(L0);
1.262 + L1_opr = as_opr(L1);
1.263 + L2_opr = as_opr(L2);
1.264 + L3_opr = as_opr(L3);
1.265 + L4_opr = as_opr(L4);
1.266 + L5_opr = as_opr(L5);
1.267 + L6_opr = as_opr(L6);
1.268 + L7_opr = as_opr(L7);
1.269 + I0_opr = as_opr(I0);
1.270 + I1_opr = as_opr(I1);
1.271 + I2_opr = as_opr(I2);
1.272 + I3_opr = as_opr(I3);
1.273 + I4_opr = as_opr(I4);
1.274 + I5_opr = as_opr(I5);
1.275 + I6_opr = as_opr(I6);
1.276 + I7_opr = as_opr(I7);
1.277 +
1.278 + G0_oop_opr = as_oop_opr(G0);
1.279 + G1_oop_opr = as_oop_opr(G1);
1.280 + G2_oop_opr = as_oop_opr(G2);
1.281 + G3_oop_opr = as_oop_opr(G3);
1.282 + G4_oop_opr = as_oop_opr(G4);
1.283 + G5_oop_opr = as_oop_opr(G5);
1.284 + G6_oop_opr = as_oop_opr(G6);
1.285 + G7_oop_opr = as_oop_opr(G7);
1.286 + O0_oop_opr = as_oop_opr(O0);
1.287 + O1_oop_opr = as_oop_opr(O1);
1.288 + O2_oop_opr = as_oop_opr(O2);
1.289 + O3_oop_opr = as_oop_opr(O3);
1.290 + O4_oop_opr = as_oop_opr(O4);
1.291 + O5_oop_opr = as_oop_opr(O5);
1.292 + O6_oop_opr = as_oop_opr(O6);
1.293 + O7_oop_opr = as_oop_opr(O7);
1.294 + L0_oop_opr = as_oop_opr(L0);
1.295 + L1_oop_opr = as_oop_opr(L1);
1.296 + L2_oop_opr = as_oop_opr(L2);
1.297 + L3_oop_opr = as_oop_opr(L3);
1.298 + L4_oop_opr = as_oop_opr(L4);
1.299 + L5_oop_opr = as_oop_opr(L5);
1.300 + L6_oop_opr = as_oop_opr(L6);
1.301 + L7_oop_opr = as_oop_opr(L7);
1.302 + I0_oop_opr = as_oop_opr(I0);
1.303 + I1_oop_opr = as_oop_opr(I1);
1.304 + I2_oop_opr = as_oop_opr(I2);
1.305 + I3_oop_opr = as_oop_opr(I3);
1.306 + I4_oop_opr = as_oop_opr(I4);
1.307 + I5_oop_opr = as_oop_opr(I5);
1.308 + I6_oop_opr = as_oop_opr(I6);
1.309 + I7_oop_opr = as_oop_opr(I7);
1.310 +
1.311 + FP_opr = as_pointer_opr(FP);
1.312 + SP_opr = as_pointer_opr(SP);
1.313 +
1.314 + F0_opr = as_float_opr(F0);
1.315 + F0_double_opr = as_double_opr(F0);
1.316 +
1.317 + Oexception_opr = as_oop_opr(Oexception);
1.318 + Oissuing_pc_opr = as_opr(Oissuing_pc);
1.319 +
1.320 + _caller_save_cpu_regs[0] = FrameMap::O0_opr;
1.321 + _caller_save_cpu_regs[1] = FrameMap::O1_opr;
1.322 + _caller_save_cpu_regs[2] = FrameMap::O2_opr;
1.323 + _caller_save_cpu_regs[3] = FrameMap::O3_opr;
1.324 + _caller_save_cpu_regs[4] = FrameMap::O4_opr;
1.325 + _caller_save_cpu_regs[5] = FrameMap::O5_opr;
1.326 + for (int i = 0; i < nof_caller_save_fpu_regs; i++) {
1.327 + _caller_save_fpu_regs[i] = LIR_OprFact::single_fpu(i);
1.328 + }
1.329 +}
1.330 +
1.331 +
1.332 +Address FrameMap::make_new_address(ByteSize sp_offset) const {
1.333 + return Address(SP, 0, STACK_BIAS + in_bytes(sp_offset));
1.334 +}
1.335 +
1.336 +
1.337 +VMReg FrameMap::fpu_regname (int n) {
1.338 + return as_FloatRegister(n)->as_VMReg();
1.339 +}
1.340 +
1.341 +
1.342 +LIR_Opr FrameMap::stack_pointer() {
1.343 + return SP_opr;
1.344 +}
1.345 +
1.346 +
1.347 +bool FrameMap::validate_frame() {
1.348 + int max_offset = in_bytes(framesize_in_bytes());
1.349 + int java_index = 0;
1.350 + for (int i = 0; i < _incoming_arguments->length(); i++) {
1.351 + LIR_Opr opr = _incoming_arguments->at(i);
1.352 + if (opr->is_stack()) {
1.353 + max_offset = MAX2(_argument_locations->at(java_index), max_offset);
1.354 + }
1.355 + java_index += type2size[opr->type()];
1.356 + }
1.357 + return Assembler::is_simm13(max_offset + STACK_BIAS);
1.358 +}
