1.1 --- a/src/cpu/x86/vm/x86_32.ad Thu Nov 06 20:00:03 2008 -0800
1.2 +++ b/src/cpu/x86/vm/x86_32.ad Fri Nov 07 09:29:38 2008 -0800
1.3 @@ -3313,7 +3313,7 @@
1.4 // Beware -- there's a subtle invariant that fetch of the markword
1.5 // at [FETCH], below, will never observe a biased encoding (*101b).
1.6 // If this invariant is not held we risk exclusion (safety) failure.
1.7 - if (UseBiasedLocking) {
1.8 + if (UseBiasedLocking && !UseOptoBiasInlining) {
1.9 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
1.10 }
1.11
1.12 @@ -3534,7 +3534,7 @@
1.13
1.14 // Critically, the biased locking test must have precedence over
1.15 // and appear before the (box->dhw == 0) recursive stack-lock test.
1.16 - if (UseBiasedLocking) {
1.17 + if (UseBiasedLocking && !UseOptoBiasInlining) {
1.18 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
1.19 }
1.20
1.21 @@ -7930,33 +7930,36 @@
1.22 ins_pipe( pipe_cmpxchg );
1.23 %}
1.24
1.25 -// Conditional-store of a long value
1.26 -// Returns a boolean value (0/1) on success. Implemented with a CMPXCHG8 on Intel.
1.27 -// mem_ptr can actually be in either ESI or EDI
1.28 -instruct storeLConditional( eRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
1.29 - match(Set res (StoreLConditional mem_ptr (Binary oldval newval)));
1.30 - effect(KILL cr);
1.31 - // EDX:EAX is killed if there is contention, but then it's also unused.
1.32 - // In the common case of no contention, EDX:EAX holds the new oop address.
1.33 - format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
1.34 - "MOV $res,0\n\t"
1.35 - "JNE,s fail\n\t"
1.36 - "MOV $res,1\n"
1.37 - "fail:" %}
1.38 - ins_encode( enc_cmpxchg8(mem_ptr),
1.39 - enc_flags_ne_to_boolean(res) );
1.40 +// Conditional-store of an int value.
1.41 +// ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
1.42 +instruct storeIConditional( memory mem, eAXRegI oldval, eRegI newval, eFlagsReg cr ) %{
1.43 + match(Set cr (StoreIConditional mem (Binary oldval newval)));
1.44 + effect(KILL oldval);
1.45 + format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
1.46 + ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
1.47 ins_pipe( pipe_cmpxchg );
1.48 %}
1.49
1.50 -// Conditional-store of a long value
1.51 -// ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel.
1.52 -// mem_ptr can actually be in either ESI or EDI
1.53 -instruct storeLConditional_flags( eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr, immI0 zero ) %{
1.54 - match(Set cr (CmpI (StoreLConditional mem_ptr (Binary oldval newval)) zero));
1.55 - // EDX:EAX is killed if there is contention, but then it's also unused.
1.56 - // In the common case of no contention, EDX:EAX holds the new oop address.
1.57 - format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" %}
1.58 - ins_encode( enc_cmpxchg8(mem_ptr) );
1.59 +// Conditional-store of a long value.
1.60 +// ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel.
1.61 +instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
1.62 + match(Set cr (StoreLConditional mem (Binary oldval newval)));
1.63 + effect(KILL oldval);
1.64 + format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t"
1.65 + "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t"
1.66 + "XCHG EBX,ECX"
1.67 + %}
1.68 + ins_encode %{
1.69 + // Note: we need to swap rbx, and rcx before and after the
1.70 + // cmpxchg8 instruction because the instruction uses
1.71 + // rcx as the high order word of the new value to store but
1.72 + // our register encoding uses rbx.
1.73 + __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
1.74 + if( os::is_MP() )
1.75 + __ lock();
1.76 + __ cmpxchg8(Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp));
1.77 + __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
1.78 + %}
1.79 ins_pipe( pipe_cmpxchg );
1.80 %}
1.81
1.82 @@ -8423,6 +8426,7 @@
1.83 ins_pipe( ialu_reg );
1.84 %}
1.85
1.86 +
1.87 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
1.88 // This idiom is used by the compiler for the i2b bytecode.
1.89 instruct i2b(eRegI dst, xRegI src, immI_24 twentyfour, eFlagsReg cr) %{
1.90 @@ -8540,6 +8544,18 @@
1.91 ins_pipe( ialu_reg_reg );
1.92 %}
1.93
1.94 +instruct orI_eReg_castP2X(eRegI dst, eRegP src, eFlagsReg cr) %{
1.95 + match(Set dst (OrI dst (CastP2X src)));
1.96 + effect(KILL cr);
1.97 +
1.98 + size(2);
1.99 + format %{ "OR $dst,$src" %}
1.100 + opcode(0x0B);
1.101 + ins_encode( OpcP, RegReg( dst, src) );
1.102 + ins_pipe( ialu_reg_reg );
1.103 +%}
1.104 +
1.105 +
1.106 // Or Register with Immediate
1.107 instruct orI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
1.108 match(Set dst (OrI dst src));
