1.1 --- a/src/cpu/sparc/vm/sparc.ad Thu Nov 06 20:00:03 2008 -0800
1.2 +++ b/src/cpu/sparc/vm/sparc.ad Fri Nov 07 09:29:38 2008 -0800
1.3 @@ -395,6 +395,7 @@
1.4 );
1.5
1.6 reg_class g1_regL(R_G1H,R_G1);
1.7 +reg_class g3_regL(R_G3H,R_G3);
1.8 reg_class o2_regL(R_O2H,R_O2);
1.9 reg_class o7_regL(R_O7H,R_O7);
1.10
1.11 @@ -2688,7 +2689,7 @@
1.12 assert(Rbox != Rscratch, "");
1.13 assert(Rbox != Rmark, "");
1.14
1.15 - __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters);
1.16 + __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
1.17 %}
1.18
1.19 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
1.20 @@ -2704,7 +2705,7 @@
1.21 assert(Rbox != Rscratch, "");
1.22 assert(Rbox != Rmark, "");
1.23
1.24 - __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch);
1.25 + __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
1.26 %}
1.27
1.28 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
1.29 @@ -2716,8 +2717,7 @@
1.30 // casx_under_lock picks 1 of 3 encodings:
1.31 // For 32-bit pointers you get a 32-bit CAS
1.32 // For 64-bit pointers you get a 64-bit CASX
1.33 - __ casx_under_lock(Rmem, Rold, Rnew, // Swap(*Rmem,Rnew) if *Rmem == Rold
1.34 - (address) StubRoutines::Sparc::atomic_memory_operation_lock_addr());
1.35 + __ casn(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
1.36 __ cmp( Rold, Rnew );
1.37 %}
1.38
1.39 @@ -3766,6 +3766,14 @@
1.40 interface(REG_INTER);
1.41 %}
1.42
1.43 +operand g3RegL() %{
1.44 + constraint(ALLOC_IN_RC(g3_regL));
1.45 + match(iRegL);
1.46 +
1.47 + format %{ %}
1.48 + interface(REG_INTER);
1.49 +%}
1.50 +
1.51 // Int Register safe
1.52 // This is 64bit safe
1.53 operand iRegIsafe() %{
1.54 @@ -6602,32 +6610,23 @@
1.55 ins_pipe( long_memory_op );
1.56 %}
1.57
1.58 -instruct storeLConditional_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
1.59 - match(Set res (StoreLConditional mem_ptr (Binary oldval newval)));
1.60 - effect( USE mem_ptr, KILL ccr, KILL tmp1);
1.61 - // Marshal the register pairs into V9 64-bit registers, then do the compare-and-swap
1.62 - format %{
1.63 - "MOV $newval,R_O7\n\t"
1.64 - "CASXA [$mem_ptr],$oldval,R_O7\t! If $oldval==[$mem_ptr] Then store R_O7 into [$mem_ptr], set R_O7=[$mem_ptr] in any case\n\t"
1.65 - "CMP $oldval,R_O7\t\t! See if we made progress\n\t"
1.66 - "MOV 1,$res\n\t"
1.67 - "MOVne xcc,R_G0,$res"
1.68 - %}
1.69 - ins_encode( enc_casx(mem_ptr, oldval, newval),
1.70 - enc_lflags_ne_to_boolean(res) );
1.71 +// Conditional-store of an int value.
1.72 +instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
1.73 + match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
1.74 + effect( KILL newval );
1.75 + format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
1.76 + "CMP $oldval,$newval\t\t! See if we made progress" %}
1.77 + ins_encode( enc_cas(mem_ptr,oldval,newval) );
1.78 ins_pipe( long_memory_op );
1.79 %}
1.80
1.81 -instruct storeLConditional_flags(iRegP mem_ptr, iRegL oldval, iRegL newval, flagsRegL xcc, o7RegI tmp1, immI0 zero) %{
1.82 - match(Set xcc (CmpI (StoreLConditional mem_ptr (Binary oldval newval)) zero));
1.83 - effect( USE mem_ptr, KILL tmp1);
1.84 - // Marshal the register pairs into V9 64-bit registers, then do the compare-and-swap
1.85 - format %{
1.86 - "MOV $newval,R_O7\n\t"
1.87 - "CASXA [$mem_ptr],$oldval,R_O7\t! If $oldval==[$mem_ptr] Then store R_O7 into [$mem_ptr], set R_O7=[$mem_ptr] in any case\n\t"
1.88 - "CMP $oldval,R_O7\t\t! See if we made progress"
1.89 - %}
1.90 - ins_encode( enc_casx(mem_ptr, oldval, newval));
1.91 +// Conditional-store of a long value.
1.92 +instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
1.93 + match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
1.94 + effect( KILL newval );
1.95 + format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
1.96 + "CMP $oldval,$newval\t\t! See if we made progress" %}
1.97 + ins_encode( enc_cas(mem_ptr,oldval,newval) );
1.98 ins_pipe( long_memory_op );
1.99 %}
1.100
1.101 @@ -7410,6 +7409,34 @@
1.102 ins_pipe(ialu_reg_imm);
1.103 %}
1.104
1.105 +#ifndef _LP64
1.106 +
1.107 +// Use sp_ptr_RegP to match G2 (TLS register) without spilling.
1.108 +instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
1.109 + match(Set dst (OrI src1 (CastP2X src2)));
1.110 +
1.111 + size(4);
1.112 + format %{ "OR $src1,$src2,$dst" %}
1.113 + opcode(Assembler::or_op3, Assembler::arith_op);
1.114 + ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
1.115 + ins_pipe(ialu_reg_reg);
1.116 +%}
1.117 +
1.118 +#else
1.119 +
1.120 +instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
1.121 + match(Set dst (OrL src1 (CastP2X src2)));
1.122 +
1.123 + ins_cost(DEFAULT_COST);
1.124 + size(4);
1.125 + format %{ "OR $src1,$src2,$dst\t! long" %}
1.126 + opcode(Assembler::or_op3, Assembler::arith_op);
1.127 + ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
1.128 + ins_pipe(ialu_reg_reg);
1.129 +%}
1.130 +
1.131 +#endif
1.132 +
1.133 // Xor Instructions
1.134 // Register Xor
1.135 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
