1.1 --- a/src/cpu/sparc/vm/sparc.ad Wed Dec 11 01:09:04 2013 +0400
1.2 +++ b/src/cpu/sparc/vm/sparc.ad Thu Dec 12 11:25:32 2013 -0800
1.3 @@ -757,7 +757,7 @@
1.4 #endif
1.5
1.6
1.7 -void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary,
1.8 +void emit_form3_mem_reg(CodeBuffer &cbuf, PhaseRegAlloc* ra, const MachNode* n, int primary, int tertiary,
1.9 int src1_enc, int disp32, int src2_enc, int dst_enc) {
1.10
1.11 #ifdef ASSERT
1.12 @@ -912,8 +912,14 @@
1.13 uint index = src2_enc;
1.14 int disp = disp32;
1.15
1.16 - if (src1_enc == R_SP_enc || src1_enc == R_FP_enc)
1.17 + if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) {
1.18 disp += STACK_BIAS;
1.19 + // Quick fix for JDK-8029668: check that stack offset fits, bailout if not
1.20 + if (!Assembler::is_simm13(disp)) {
1.21 + ra->C->record_method_not_compilable("unable to handle large constant offsets");
1.22 + return;
1.23 + }
1.24 + }
1.25
1.26 // We should have a compiler bailout here rather than a guarantee.
1.27 // Better yet would be some mechanism to handle variable-size matches correctly.
1.28 @@ -1279,20 +1285,15 @@
1.29 return rc_float;
1.30 }
1.31
1.32 -static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {
1.33 - if( cbuf ) {
1.34 - // Better yet would be some mechanism to handle variable-size matches correctly
1.35 - if (!Assembler::is_simm13(offset + STACK_BIAS)) {
1.36 - ra_->C->record_method_not_compilable("unable to handle large constant offsets");
1.37 - } else {
1.38 - emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1.39 - }
1.40 +static int impl_helper(const MachNode* mach, CodeBuffer* cbuf, PhaseRegAlloc* ra, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {
1.41 + if (cbuf) {
1.42 + emit_form3_mem_reg(*cbuf, ra, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1.43 }
1.44 #ifndef PRODUCT
1.45 - else if( !do_size ) {
1.46 - if( size != 0 ) st->print("\n\t");
1.47 - if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));
1.48 - else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);
1.49 + else if (!do_size) {
1.50 + if (size != 0) st->print("\n\t");
1.51 + if (is_load) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));
1.52 + else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);
1.53 }
1.54 #endif
1.55 return size+4;
1.56 @@ -2087,22 +2088,22 @@
1.57 %}
1.58
1.59 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
1.60 - emit_form3_mem_reg(cbuf, this, $primary, $tertiary,
1.61 + emit_form3_mem_reg(cbuf, ra_, this, $primary, $tertiary,
1.62 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
1.63 %}
1.64
1.65 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
1.66 - emit_form3_mem_reg(cbuf, this, $primary, -1,
1.67 + emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
1.68 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
1.69 %}
1.70
1.71 enc_class form3_mem_prefetch_read( memory mem ) %{
1.72 - emit_form3_mem_reg(cbuf, this, $primary, -1,
1.73 + emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
1.74 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
1.75 %}
1.76
1.77 enc_class form3_mem_prefetch_write( memory mem ) %{
1.78 - emit_form3_mem_reg(cbuf, this, $primary, -1,
1.79 + emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
1.80 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
1.81 %}
1.82
1.83 @@ -2110,8 +2111,8 @@
1.84 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
1.85 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
1.86 guarantee($mem$$index == R_G0_enc, "double index?");
1.87 - emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
1.88 - emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
1.89 + emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
1.90 + emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
1.91 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
1.92 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
1.93 %}
1.94 @@ -2121,14 +2122,14 @@
1.95 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
1.96 guarantee($mem$$index == R_G0_enc, "double index?");
1.97 // Load long with 2 instructions
1.98 - emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
1.99 - emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
1.100 + emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
1.101 + emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
1.102 %}
1.103
1.104 //%%% form3_mem_plus_4_reg is a hack--get rid of it
1.105 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
1.106 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
1.107 - emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
1.108 + emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
1.109 %}
1.110
1.111 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
