1.1 --- a/src/cpu/x86/vm/x86_32.ad Fri Feb 27 08:34:19 2009 -0800
1.2 +++ b/src/cpu/x86/vm/x86_32.ad Fri Feb 27 13:27:09 2009 -0800
1.3 @@ -130,7 +130,7 @@
1.4 // allocation. Highest priority is first. A useful heuristic is to
1.5 // give registers a low priority when they are required by machine
1.6 // instructions, like EAX and EDX. Registers which are used as
1.7 -// pairs must fall on an even boundry (witness the FPR#L's in this list).
1.8 +// pairs must fall on an even boundary (witness the FPR#L's in this list).
1.9 // For the Intel integer registers, the equivalent Long pairs are
1.10 // EDX:EAX, EBX:ECX, and EDI:EBP.
1.11 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
1.12 @@ -5857,7 +5857,7 @@
1.13
1.14 //----------OPERAND CLASSES----------------------------------------------------
1.15 // Operand Classes are groups of operands that are used as to simplify
1.16 -// instruction definitions by not requiring the AD writer to specify seperate
1.17 +// instruction definitions by not requiring the AD writer to specify separate
1.18 // instructions for every form of operand when the instruction accepts
1.19 // multiple operand types with the same basic encoding and format. The classic
1.20 // case of this is memory operands.
1.21 @@ -13220,7 +13220,7 @@
1.22 // These must follow all instruction definitions as they use the names
1.23 // defined in the instructions definitions.
1.24 //
1.25 -// peepmatch ( root_instr_name [preceeding_instruction]* );
1.26 +// peepmatch ( root_instr_name [preceding_instruction]* );
1.27 //
1.28 // peepconstraint %{
1.29 // (instruction_number.operand_name relational_op instruction_number.operand_name
