1.1 --- a/src/cpu/x86/vm/x86_32.ad Fri Jan 17 18:09:08 2014 -0800 1.2 +++ b/src/cpu/x86/vm/x86_32.ad Tue Jan 21 20:05:28 2014 -0800 1.3 @@ -3889,6 +3889,17 @@ 1.4 interface(CONST_INTER); 1.5 %} 1.6 1.7 +// Int Immediate non-negative 1.8 +operand immU31() 1.9 +%{ 1.10 + predicate(n->get_int() >= 0); 1.11 + match(ConI); 1.12 + 1.13 + op_cost(0); 1.14 + format %{ %} 1.15 + interface(CONST_INTER); 1.16 +%} 1.17 + 1.18 // Constant for long shifts 1.19 operand immI_32() %{ 1.20 predicate( n->get_int() == 32 ); 1.21 @@ -6119,12 +6130,12 @@ 1.22 ins_pipe(ialu_reg_mem); 1.23 %} 1.24 1.25 -// Load Integer with 32-bit mask into Long Register 1.26 -instruct loadI2L_immI(eRegL dst, memory mem, immI mask, eFlagsReg cr) %{ 1.27 +// Load Integer with 31-bit mask into Long Register 1.28 +instruct loadI2L_immU31(eRegL dst, memory mem, immU31 mask, eFlagsReg cr) %{ 1.29 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 1.30 effect(KILL cr); 1.31 1.32 - format %{ "MOV $dst.lo,$mem\t# int & 32-bit mask -> long\n\t" 1.33 + format %{ "MOV $dst.lo,$mem\t# int & 31-bit mask -> long\n\t" 1.34 "XOR $dst.hi,$dst.hi\n\t" 1.35 "AND $dst.lo,$mask" %} 1.36 ins_encode %{