1.1 --- a/src/cpu/x86/vm/x86_32.ad Tue May 05 11:02:10 2009 -0700
1.2 +++ b/src/cpu/x86/vm/x86_32.ad Wed May 06 00:27:52 2009 -0700
1.3 @@ -1281,6 +1281,13 @@
1.4 }
1.5
1.6
1.7 +const bool Matcher::match_rule_supported(int opcode) {
1.8 + if (!has_match_rule(opcode))
1.9 + return false;
1.10 +
1.11 + return true; // Per default match rules are supported.
1.12 +}
1.13 +
1.14 int Matcher::regnum_to_fpu_offset(int regnum) {
1.15 return regnum - 32; // The FP registers are in the second chunk
1.16 }
1.17 @@ -6644,6 +6651,153 @@
1.18 %}
1.19
1.20
1.21 +//---------- Zeros Count Instructions ------------------------------------------
1.22 +
1.23 +instruct countLeadingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{
1.24 + predicate(UseCountLeadingZerosInstruction);
1.25 + match(Set dst (CountLeadingZerosI src));
1.26 + effect(KILL cr);
1.27 +
1.28 + format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %}
1.29 + ins_encode %{
1.30 + __ lzcntl($dst$$Register, $src$$Register);
1.31 + %}
1.32 + ins_pipe(ialu_reg);
1.33 +%}
1.34 +
1.35 +instruct countLeadingZerosI_bsr(eRegI dst, eRegI src, eFlagsReg cr) %{
1.36 + predicate(!UseCountLeadingZerosInstruction);
1.37 + match(Set dst (CountLeadingZerosI src));
1.38 + effect(KILL cr);
1.39 +
1.40 + format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t"
1.41 + "JNZ skip\n\t"
1.42 + "MOV $dst, -1\n"
1.43 + "skip:\n\t"
1.44 + "NEG $dst\n\t"
1.45 + "ADD $dst, 31" %}
1.46 + ins_encode %{
1.47 + Register Rdst = $dst$$Register;
1.48 + Register Rsrc = $src$$Register;
1.49 + Label skip;
1.50 + __ bsrl(Rdst, Rsrc);
1.51 + __ jccb(Assembler::notZero, skip);
1.52 + __ movl(Rdst, -1);
1.53 + __ bind(skip);
1.54 + __ negl(Rdst);
1.55 + __ addl(Rdst, BitsPerInt - 1);
1.56 + %}
1.57 + ins_pipe(ialu_reg);
1.58 +%}
1.59 +
1.60 +instruct countLeadingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{
1.61 + predicate(UseCountLeadingZerosInstruction);
1.62 + match(Set dst (CountLeadingZerosL src));
1.63 + effect(TEMP dst, KILL cr);
1.64 +
1.65 + format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t"
1.66 + "JNC done\n\t"
1.67 + "LZCNT $dst, $src.lo\n\t"
1.68 + "ADD $dst, 32\n"
1.69 + "done:" %}
1.70 + ins_encode %{
1.71 + Register Rdst = $dst$$Register;
1.72 + Register Rsrc = $src$$Register;
1.73 + Label done;
1.74 + __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
1.75 + __ jccb(Assembler::carryClear, done);
1.76 + __ lzcntl(Rdst, Rsrc);
1.77 + __ addl(Rdst, BitsPerInt);
1.78 + __ bind(done);
1.79 + %}
1.80 + ins_pipe(ialu_reg);
1.81 +%}
1.82 +
1.83 +instruct countLeadingZerosL_bsr(eRegI dst, eRegL src, eFlagsReg cr) %{
1.84 + predicate(!UseCountLeadingZerosInstruction);
1.85 + match(Set dst (CountLeadingZerosL src));
1.86 + effect(TEMP dst, KILL cr);
1.87 +
1.88 + format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t"
1.89 + "JZ msw_is_zero\n\t"
1.90 + "ADD $dst, 32\n\t"
1.91 + "JMP not_zero\n"
1.92 + "msw_is_zero:\n\t"
1.93 + "BSR $dst, $src.lo\n\t"
1.94 + "JNZ not_zero\n\t"
1.95 + "MOV $dst, -1\n"
1.96 + "not_zero:\n\t"
1.97 + "NEG $dst\n\t"
1.98 + "ADD $dst, 63\n" %}
1.99 + ins_encode %{
1.100 + Register Rdst = $dst$$Register;
1.101 + Register Rsrc = $src$$Register;
1.102 + Label msw_is_zero;
1.103 + Label not_zero;
1.104 + __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc));
1.105 + __ jccb(Assembler::zero, msw_is_zero);
1.106 + __ addl(Rdst, BitsPerInt);
1.107 + __ jmpb(not_zero);
1.108 + __ bind(msw_is_zero);
1.109 + __ bsrl(Rdst, Rsrc);
1.110 + __ jccb(Assembler::notZero, not_zero);
1.111 + __ movl(Rdst, -1);
1.112 + __ bind(not_zero);
1.113 + __ negl(Rdst);
1.114 + __ addl(Rdst, BitsPerLong - 1);
1.115 + %}
1.116 + ins_pipe(ialu_reg);
1.117 +%}
1.118 +
1.119 +instruct countTrailingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{
1.120 + match(Set dst (CountTrailingZerosI src));
1.121 + effect(KILL cr);
1.122 +
1.123 + format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t"
1.124 + "JNZ done\n\t"
1.125 + "MOV $dst, 32\n"
1.126 + "done:" %}
1.127 + ins_encode %{
1.128 + Register Rdst = $dst$$Register;
1.129 + Label done;
1.130 + __ bsfl(Rdst, $src$$Register);
1.131 + __ jccb(Assembler::notZero, done);
1.132 + __ movl(Rdst, BitsPerInt);
1.133 + __ bind(done);
1.134 + %}
1.135 + ins_pipe(ialu_reg);
1.136 +%}
1.137 +
1.138 +instruct countTrailingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{
1.139 + match(Set dst (CountTrailingZerosL src));
1.140 + effect(TEMP dst, KILL cr);
1.141 +
1.142 + format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t"
1.143 + "JNZ done\n\t"
1.144 + "BSF $dst, $src.hi\n\t"
1.145 + "JNZ msw_not_zero\n\t"
1.146 + "MOV $dst, 32\n"
1.147 + "msw_not_zero:\n\t"
1.148 + "ADD $dst, 32\n"
1.149 + "done:" %}
1.150 + ins_encode %{
1.151 + Register Rdst = $dst$$Register;
1.152 + Register Rsrc = $src$$Register;
1.153 + Label msw_not_zero;
1.154 + Label done;
1.155 + __ bsfl(Rdst, Rsrc);
1.156 + __ jccb(Assembler::notZero, done);
1.157 + __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc));
1.158 + __ jccb(Assembler::notZero, msw_not_zero);
1.159 + __ movl(Rdst, BitsPerInt);
1.160 + __ bind(msw_not_zero);
1.161 + __ addl(Rdst, BitsPerInt);
1.162 + __ bind(done);
1.163 + %}
1.164 + ins_pipe(ialu_reg);
1.165 +%}
1.166 +
1.167 +
1.168 //---------- Population Count Instructions -------------------------------------
1.169
1.170 instruct popCountI(eRegI dst, eRegI src) %{
