1.1 --- a/src/cpu/mips/vm/mips_64.ad Wed Sep 12 16:47:16 2018 +0800 1.2 +++ b/src/cpu/mips/vm/mips_64.ad Thu Sep 13 15:03:14 2018 +0800 1.3 @@ -9794,6 +9794,59 @@ 1.4 ins_pipe( pipe_slow ); 1.5 %} 1.6 1.7 +instruct cmovL_cmpP_reg_reg(mRegL dst, mRegL src, mRegP tmp1, mRegP tmp2, cmpOpU cop ) %{ 1.8 + match(Set dst (CMoveL (Binary cop (CmpP tmp1 tmp2)) (Binary dst src))); 1.9 + ins_cost(80); 1.10 + format %{ 1.11 + "CMPU$cop $tmp1,$tmp2\t @cmovL_cmpP_reg_reg\n\t" 1.12 + "CMOV $dst,$src\t @cmovL_cmpP_reg_reg" 1.13 + %} 1.14 + ins_encode %{ 1.15 + Register op1 = $tmp1$$Register; 1.16 + Register op2 = $tmp2$$Register; 1.17 + Register dst = $dst$$Register; 1.18 + Register src = $src$$Register; 1.19 + int flag = $cop$$cmpcode; 1.20 + 1.21 + switch(flag) { 1.22 + case 0x01: //equal 1.23 + __ subu(AT, op1, op2); 1.24 + __ movz(dst, src, AT); 1.25 + break; 1.26 + 1.27 + case 0x02: //not_equal 1.28 + __ subu(AT, op1, op2); 1.29 + __ movn(dst, src, AT); 1.30 + break; 1.31 + 1.32 + case 0x03: //above 1.33 + __ sltu(AT, op2, op1); 1.34 + __ movn(dst, src, AT); 1.35 + break; 1.36 + 1.37 + case 0x04: //above_equal 1.38 + __ sltu(AT, op1, op2); 1.39 + __ movz(dst, src, AT); 1.40 + break; 1.41 + 1.42 + case 0x05: //below 1.43 + __ sltu(AT, op1, op2); 1.44 + __ movn(dst, src, AT); 1.45 + break; 1.46 + 1.47 + case 0x06: //below_equal 1.48 + __ sltu(AT, op2, op1); 1.49 + __ movz(dst, src, AT); 1.50 + break; 1.51 + 1.52 + default: 1.53 + Unimplemented(); 1.54 + } 1.55 + %} 1.56 + 1.57 + ins_pipe( pipe_slow ); 1.58 +%} 1.59 + 1.60 instruct cmovN_cmpL_reg_reg(mRegN dst, mRegN src, mRegL tmp1, mRegL tmp2, cmpOp cop) %{ 1.61 match(Set dst (CMoveN (Binary cop (CmpL tmp1 tmp2)) (Binary dst src))); 1.62 ins_cost(80);