1.1 --- a/src/cpu/x86/vm/vm_version_x86.hpp Mon Jan 27 13:14:53 2014 +0100
1.2 +++ b/src/cpu/x86/vm/vm_version_x86.hpp Wed Mar 12 11:24:26 2014 -0700
1.3 @@ -141,7 +141,8 @@
1.4 struct {
1.5 uint32_t LahfSahf : 1,
1.6 CmpLegacy : 1,
1.7 - : 4,
1.8 + : 3,
1.9 + lzcnt_intel : 1,
1.10 lzcnt : 1,
1.11 sse4a : 1,
1.12 misalignsse : 1,
1.13 @@ -251,7 +252,9 @@
1.14 CPU_AVX2 = (1 << 18),
1.15 CPU_AES = (1 << 19),
1.16 CPU_ERMS = (1 << 20), // enhanced 'rep movsb/stosb' instructions
1.17 - CPU_CLMUL = (1 << 21) // carryless multiply for CRC
1.18 + CPU_CLMUL = (1 << 21), // carryless multiply for CRC
1.19 + CPU_BMI1 = (1 << 22),
1.20 + CPU_BMI2 = (1 << 23)
1.21 } cpuFeatureFlags;
1.22
1.23 enum {
1.24 @@ -423,6 +426,8 @@
1.25 if (_cpuid_info.sef_cpuid7_ebx.bits.avx2 != 0)
1.26 result |= CPU_AVX2;
1.27 }
1.28 + if(_cpuid_info.sef_cpuid7_ebx.bits.bmi1 != 0)
1.29 + result |= CPU_BMI1;
1.30 if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0)
1.31 result |= CPU_TSC;
1.32 if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0)
1.33 @@ -444,6 +449,13 @@
1.34 if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0)
1.35 result |= CPU_SSE4A;
1.36 }
1.37 + // Intel features.
1.38 + if(is_intel()) {
1.39 + if(_cpuid_info.sef_cpuid7_ebx.bits.bmi2 != 0)
1.40 + result |= CPU_BMI2;
1.41 + if(_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0)
1.42 + result |= CPU_LZCNT;
1.43 + }
1.44
1.45 return result;
1.46 }
1.47 @@ -560,7 +572,8 @@
1.48 static bool supports_aes() { return (_cpuFeatures & CPU_AES) != 0; }
1.49 static bool supports_erms() { return (_cpuFeatures & CPU_ERMS) != 0; }
1.50 static bool supports_clmul() { return (_cpuFeatures & CPU_CLMUL) != 0; }
1.51 -
1.52 + static bool supports_bmi1() { return (_cpuFeatures & CPU_BMI1) != 0; }
1.53 + static bool supports_bmi2() { return (_cpuFeatures & CPU_BMI2) != 0; }
1.54 // Intel features
1.55 static bool is_intel_family_core() { return is_intel() &&
1.56 extended_cpu_family() == CPU_FAMILY_INTEL_CORE; }
