1.1 --- a/src/share/vm/c1/c1_LIR.cpp Wed Sep 19 16:50:26 2012 -0700
1.2 +++ b/src/share/vm/c1/c1_LIR.cpp Thu Sep 20 16:49:17 2012 +0200
1.3 @@ -264,6 +264,7 @@
1.4 #ifdef ASSERT
1.5 switch (code()) {
1.6 case lir_cmove:
1.7 + case lir_xchg:
1.8 break;
1.9
1.10 default:
1.11 @@ -630,6 +631,8 @@
1.12 case lir_shl:
1.13 case lir_shr:
1.14 case lir_ushr:
1.15 + case lir_xadd:
1.16 + case lir_xchg:
1.17 {
1.18 assert(op->as_Op2() != NULL, "must be");
1.19 LIR_Op2* op2 = (LIR_Op2*)op;
1.20 @@ -641,6 +644,13 @@
1.21 if (op2->_opr2->is_valid()) do_input(op2->_opr2);
1.22 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
1.23 if (op2->_result->is_valid()) do_output(op2->_result);
1.24 + if (op->code() == lir_xchg || op->code() == lir_xadd) {
1.25 + // on ARM and PPC, return value is loaded first so could
1.26 + // destroy inputs. On other platforms that implement those
1.27 + // (x86, sparc), the extra constrainsts are harmless.
1.28 + if (op2->_opr1->is_valid()) do_temp(op2->_opr1);
1.29 + if (op2->_opr2->is_valid()) do_temp(op2->_opr2);
1.30 + }
1.31
1.32 break;
1.33 }
1.34 @@ -1733,6 +1743,8 @@
1.35 case lir_shr: s = "shift_right"; break;
1.36 case lir_ushr: s = "ushift_right"; break;
1.37 case lir_alloc_array: s = "alloc_array"; break;
1.38 + case lir_xadd: s = "xadd"; break;
1.39 + case lir_xchg: s = "xchg"; break;
1.40 // LIR_Op3
1.41 case lir_idiv: s = "idiv"; break;
1.42 case lir_irem: s = "irem"; break;
