1.1 --- a/src/cpu/sparc/vm/sparc.ad Mon Mar 09 13:34:00 2009 -0700
1.2 +++ b/src/cpu/sparc/vm/sparc.ad Thu Mar 12 18:16:36 2009 -0700
1.3 @@ -189,7 +189,7 @@
1.4 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
1.5 // wants 0-63, so we have to convert every time we want to use fp regs
1.6 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
1.7 -// 255 is a flag meaning 'dont go here'.
1.8 +// 255 is a flag meaning "don't go here".
1.9 // I believe we can't handle callee-save doubles D32 and up until
1.10 // the place in the sparc stack crawler that asserts on the 255 is
1.11 // fixed up.
1.12 @@ -462,7 +462,7 @@
1.13
1.14 // Macros to extract hi & lo halves from a long pair.
1.15 // G0 is not part of any long pair, so assert on that.
1.16 -// Prevents accidently using G1 instead of G0.
1.17 +// Prevents accidentally using G1 instead of G0.
1.18 #define LONG_HI_REG(x) (x)
1.19 #define LONG_LO_REG(x) (x)
1.20
1.21 @@ -1431,7 +1431,7 @@
1.22
1.23 #ifndef _LP64
1.24 // In the LP64 build, all registers can be moved as aligned/adjacent
1.25 - // pairs, so there's never any need to move the high bits seperately.
1.26 + // pairs, so there's never any need to move the high bits separately.
1.27 // The 32-bit builds have to deal with the 32-bit ABI which can force
1.28 // all sorts of silly alignment problems.
1.29
1.30 @@ -1624,7 +1624,7 @@
1.31 Register temp_reg = G3;
1.32 assert( G5_ic_reg != temp_reg, "conflicting registers" );
1.33
1.34 - // Load klass from reciever
1.35 + // Load klass from receiver
1.36 __ load_klass(O0, temp_reg);
1.37 // Compare against expected klass
1.38 __ cmp(temp_reg, G5_ic_reg);
1.39 @@ -4149,7 +4149,7 @@
1.40
1.41 //----------OPERAND CLASSES----------------------------------------------------
1.42 // Operand Classes are groups of operands that are used to simplify
1.43 -// instruction definitions by not requiring the AD writer to specify seperate
1.44 +// instruction definitions by not requiring the AD writer to specify separate
1.45 // instructions for every form of operand when the instruction accepts
1.46 // multiple operand types with the same basic encoding and format. The classic
1.47 // case of this is memory operands.
1.48 @@ -5286,55 +5286,91 @@
1.49 ins_cost(MEMORY_REF_COST);
1.50
1.51 size(4);
1.52 - format %{ "LDSB $mem,$dst" %}
1.53 + format %{ "LDSB $mem,$dst\t! byte" %}
1.54 opcode(Assembler::ldsb_op3);
1.55 ins_encode(simple_form3_mem_reg( mem, dst ) );
1.56 ins_pipe(iload_mask_mem);
1.57 %}
1.58
1.59 -// Load Byte (8bit UNsigned) into an int reg
1.60 -instruct loadUB(iRegI dst, memory mem, immI_255 bytemask) %{
1.61 - match(Set dst (AndI (LoadB mem) bytemask));
1.62 +// Load Byte (8bit signed) into a Long Register
1.63 +instruct loadB2L(iRegL dst, memory mem) %{
1.64 + match(Set dst (ConvI2L (LoadB mem)));
1.65 ins_cost(MEMORY_REF_COST);
1.66
1.67 size(4);
1.68 - format %{ "LDUB $mem,$dst" %}
1.69 + format %{ "LDSB $mem,$dst\t! byte -> long" %}
1.70 + opcode(Assembler::ldsb_op3);
1.71 + ins_encode(simple_form3_mem_reg( mem, dst ) );
1.72 + ins_pipe(iload_mask_mem);
1.73 +%}
1.74 +
1.75 +// Load Unsigned Byte (8bit UNsigned) into an int reg
1.76 +instruct loadUB(iRegI dst, memory mem) %{
1.77 + match(Set dst (LoadUB mem));
1.78 + ins_cost(MEMORY_REF_COST);
1.79 +
1.80 + size(4);
1.81 + format %{ "LDUB $mem,$dst\t! ubyte" %}
1.82 opcode(Assembler::ldub_op3);
1.83 ins_encode(simple_form3_mem_reg( mem, dst ) );
1.84 ins_pipe(iload_mask_mem);
1.85 %}
1.86
1.87 -// Load Byte (8bit UNsigned) into a Long Register
1.88 -instruct loadUBL(iRegL dst, memory mem, immL_FF bytemask) %{
1.89 - match(Set dst (AndL (ConvI2L (LoadB mem)) bytemask));
1.90 +// Load Unsigned Byte (8bit UNsigned) into a Long Register
1.91 +instruct loadUB2L(iRegL dst, memory mem) %{
1.92 + match(Set dst (ConvI2L (LoadUB mem)));
1.93 ins_cost(MEMORY_REF_COST);
1.94
1.95 size(4);
1.96 - format %{ "LDUB $mem,$dst" %}
1.97 + format %{ "LDUB $mem,$dst\t! ubyte -> long" %}
1.98 opcode(Assembler::ldub_op3);
1.99 ins_encode(simple_form3_mem_reg( mem, dst ) );
1.100 ins_pipe(iload_mask_mem);
1.101 %}
1.102
1.103 -// Load Unsigned Short/Char (16bit UNsigned) into a Long Register
1.104 -instruct loadUS2L(iRegL dst, memory mem, immL_FFFF bytemask) %{
1.105 - match(Set dst (AndL (ConvI2L (LoadUS mem)) bytemask));
1.106 +// Load Short (16bit signed)
1.107 +instruct loadS(iRegI dst, memory mem) %{
1.108 + match(Set dst (LoadS mem));
1.109 ins_cost(MEMORY_REF_COST);
1.110
1.111 size(4);
1.112 - format %{ "LDUH $mem,$dst" %}
1.113 + format %{ "LDSH $mem,$dst\t! short" %}
1.114 + opcode(Assembler::ldsh_op3);
1.115 + ins_encode(simple_form3_mem_reg( mem, dst ) );
1.116 + ins_pipe(iload_mask_mem);
1.117 +%}
1.118 +
1.119 +// Load Short (16bit signed) into a Long Register
1.120 +instruct loadS2L(iRegL dst, memory mem) %{
1.121 + match(Set dst (ConvI2L (LoadS mem)));
1.122 + ins_cost(MEMORY_REF_COST);
1.123 +
1.124 + size(4);
1.125 + format %{ "LDSH $mem,$dst\t! short -> long" %}
1.126 + opcode(Assembler::ldsh_op3);
1.127 + ins_encode(simple_form3_mem_reg( mem, dst ) );
1.128 + ins_pipe(iload_mask_mem);
1.129 +%}
1.130 +
1.131 +// Load Unsigned Short/Char (16bit UNsigned)
1.132 +instruct loadUS(iRegI dst, memory mem) %{
1.133 + match(Set dst (LoadUS mem));
1.134 + ins_cost(MEMORY_REF_COST);
1.135 +
1.136 + size(4);
1.137 + format %{ "LDUH $mem,$dst\t! ushort/char" %}
1.138 opcode(Assembler::lduh_op3);
1.139 ins_encode(simple_form3_mem_reg( mem, dst ) );
1.140 ins_pipe(iload_mask_mem);
1.141 %}
1.142
1.143 -// Load Unsigned Short/Char (16bit unsigned)
1.144 -instruct loadUS(iRegI dst, memory mem) %{
1.145 - match(Set dst (LoadUS mem));
1.146 +// Load Unsigned Short/Char (16bit UNsigned) into a Long Register
1.147 +instruct loadUS2L(iRegL dst, memory mem) %{
1.148 + match(Set dst (ConvI2L (LoadUS mem)));
1.149 ins_cost(MEMORY_REF_COST);
1.150
1.151 size(4);
1.152 - format %{ "LDUH $mem,$dst" %}
1.153 + format %{ "LDUH $mem,$dst\t! ushort/char -> long" %}
1.154 opcode(Assembler::lduh_op3);
1.155 ins_encode(simple_form3_mem_reg( mem, dst ) );
1.156 ins_pipe(iload_mask_mem);
1.157 @@ -5344,9 +5380,33 @@
1.158 instruct loadI(iRegI dst, memory mem) %{
1.159 match(Set dst (LoadI mem));
1.160 ins_cost(MEMORY_REF_COST);
1.161 - size(4);
1.162 -
1.163 - format %{ "LDUW $mem,$dst" %}
1.164 +
1.165 + size(4);
1.166 + format %{ "LDUW $mem,$dst\t! int" %}
1.167 + opcode(Assembler::lduw_op3);
1.168 + ins_encode(simple_form3_mem_reg( mem, dst ) );
1.169 + ins_pipe(iload_mem);
1.170 +%}
1.171 +
1.172 +// Load Integer into a Long Register
1.173 +instruct loadI2L(iRegL dst, memory mem) %{
1.174 + match(Set dst (ConvI2L (LoadI mem)));
1.175 + ins_cost(MEMORY_REF_COST);
1.176 +
1.177 + size(4);
1.178 + format %{ "LDSW $mem,$dst\t! int -> long" %}
1.179 + opcode(Assembler::ldsw_op3);
1.180 + ins_encode(simple_form3_mem_reg( mem, dst ) );
1.181 + ins_pipe(iload_mem);
1.182 +%}
1.183 +
1.184 +// Load Unsigned Integer into a Long Register
1.185 +instruct loadUI2L(iRegL dst, memory mem) %{
1.186 + match(Set dst (LoadUI2L mem));
1.187 + ins_cost(MEMORY_REF_COST);
1.188 +
1.189 + size(4);
1.190 + format %{ "LDUW $mem,$dst\t! uint -> long" %}
1.191 opcode(Assembler::lduw_op3);
1.192 ins_encode(simple_form3_mem_reg( mem, dst ) );
1.193 ins_pipe(iload_mem);
1.194 @@ -5356,6 +5416,7 @@
1.195 instruct loadL(iRegL dst, memory mem ) %{
1.196 match(Set dst (LoadL mem));
1.197 ins_cost(MEMORY_REF_COST);
1.198 +
1.199 size(4);
1.200 format %{ "LDX $mem,$dst\t! long" %}
1.201 opcode(Assembler::ldx_op3);
1.202 @@ -5471,13 +5532,11 @@
1.203
1.204 format %{ "LDUW $mem,$dst\t! compressed ptr" %}
1.205 ins_encode %{
1.206 - Register base = as_Register($mem$$base);
1.207 - Register index = as_Register($mem$$index);
1.208 - Register dst = $dst$$Register;
1.209 + Register index = $mem$$index$$Register;
1.210 if (index != G0) {
1.211 - __ lduw(base, index, dst);
1.212 + __ lduw($mem$$base$$Register, index, $dst$$Register);
1.213 } else {
1.214 - __ lduw(base, $mem$$disp, dst);
1.215 + __ lduw($mem$$base$$Register, $mem$$disp, $dst$$Register);
1.216 }
1.217 %}
1.218 ins_pipe(iload_mem);
1.219 @@ -5521,18 +5580,6 @@
1.220 ins_pipe(iload_mem);
1.221 %}
1.222
1.223 -// Load Short (16bit signed)
1.224 -instruct loadS(iRegI dst, memory mem) %{
1.225 - match(Set dst (LoadS mem));
1.226 - ins_cost(MEMORY_REF_COST);
1.227 -
1.228 - size(4);
1.229 - format %{ "LDSH $mem,$dst" %}
1.230 - opcode(Assembler::ldsh_op3);
1.231 - ins_encode(simple_form3_mem_reg( mem, dst ) );
1.232 - ins_pipe(iload_mask_mem);
1.233 -%}
1.234 -
1.235 // Load Double
1.236 instruct loadD(regD dst, memory mem) %{
1.237 match(Set dst (LoadD mem));
1.238 @@ -6847,7 +6894,7 @@
1.239 ins_pipe(sdiv_reg_reg);
1.240 %}
1.241
1.242 -// Magic constant, reciprical of 10
1.243 +// Magic constant, reciprocal of 10
1.244 instruct loadConI_x66666667(iRegIsafe dst) %{
1.245 effect( DEF dst );
1.246
1.247 @@ -6857,7 +6904,7 @@
1.248 ins_pipe(ialu_hi_lo_reg);
1.249 %}
1.250
1.251 -// Register Shift Right Arithmatic Long by 32-63
1.252 +// Register Shift Right Arithmetic Long by 32-63
1.253 instruct sra_31( iRegI dst, iRegI src ) %{
1.254 effect( DEF dst, USE src );
1.255 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
1.256 @@ -9048,7 +9095,7 @@
1.257 // These must follow all instruction definitions as they use the names
1.258 // defined in the instructions definitions.
1.259 //
1.260 -// peepmatch ( root_instr_name [preceeding_instruction]* );
1.261 +// peepmatch ( root_instr_name [preceding_instruction]* );
1.262 //
1.263 // peepconstraint %{
1.264 // (instruction_number.operand_name relational_op instruction_number.operand_name
