1.1 --- a/src/cpu/x86/vm/x86_64.ad Tue Oct 12 10:57:33 2010 -0400
1.2 +++ b/src/cpu/x86/vm/x86_64.ad Wed Oct 13 11:46:46 2010 -0400
1.3 @@ -7349,43 +7349,6 @@
1.4 ins_pipe( ialu_reg );
1.5 %}
1.6
1.7 -instruct loadI_reversed(rRegI dst, memory src) %{
1.8 - match(Set dst (ReverseBytesI (LoadI src)));
1.9 -
1.10 - format %{ "bswap_movl $dst, $src" %}
1.11 - opcode(0x8B, 0x0F, 0xC8); /* Opcode 8B 0F C8 */
1.12 - ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src), REX_reg(dst), OpcS, opc3_reg(dst));
1.13 - ins_pipe( ialu_reg_mem );
1.14 -%}
1.15 -
1.16 -instruct loadL_reversed(rRegL dst, memory src) %{
1.17 - match(Set dst (ReverseBytesL (LoadL src)));
1.18 -
1.19 - format %{ "bswap_movq $dst, $src" %}
1.20 - opcode(0x8B, 0x0F, 0xC8); /* Opcode 8B 0F C8 */
1.21 - ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src), REX_reg_wide(dst), OpcS, opc3_reg(dst));
1.22 - ins_pipe( ialu_reg_mem );
1.23 -%}
1.24 -
1.25 -instruct storeI_reversed(memory dst, rRegI src) %{
1.26 - match(Set dst (StoreI dst (ReverseBytesI src)));
1.27 -
1.28 - format %{ "movl_bswap $dst, $src" %}
1.29 - opcode(0x0F, 0xC8, 0x89); /* Opcode 0F C8 89 */
1.30 - ins_encode( REX_reg(src), OpcP, opc2_reg(src), REX_reg_mem(src, dst), OpcT, reg_mem(src, dst) );
1.31 - ins_pipe( ialu_mem_reg );
1.32 -%}
1.33 -
1.34 -instruct storeL_reversed(memory dst, rRegL src) %{
1.35 - match(Set dst (StoreL dst (ReverseBytesL src)));
1.36 -
1.37 - format %{ "movq_bswap $dst, $src" %}
1.38 - opcode(0x0F, 0xC8, 0x89); /* Opcode 0F C8 89 */
1.39 - ins_encode( REX_reg_wide(src), OpcP, opc2_reg(src), REX_reg_mem_wide(src, dst), OpcT, reg_mem(src, dst) );
1.40 - ins_pipe( ialu_mem_reg );
1.41 -%}
1.42 -
1.43 -
1.44 //---------- Zeros Count Instructions ------------------------------------------
1.45
1.46 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
