1.1 --- a/src/share/vm/c1/c1_LIRAssembler.hpp Mon Sep 08 12:35:01 2014 -0700 1.2 +++ b/src/share/vm/c1/c1_LIRAssembler.hpp Tue Aug 08 15:57:29 2017 +0800 1.3 @@ -22,6 +22,12 @@ 1.4 * 1.5 */ 1.6 1.7 +/* 1.8 + * This file has been modified by Loongson Technology in 2015. These 1.9 + * modifications are Copyright (c) 2015 Loongson Technology, and are made 1.10 + * available on the same license terms set forth above. 1.11 + */ 1.12 + 1.13 #ifndef SHARE_VM_C1_C1_LIRASSEMBLER_HPP 1.14 #define SHARE_VM_C1_C1_LIRASSEMBLER_HPP 1.15 1.16 @@ -213,6 +219,9 @@ 1.17 void emit_delay(LIR_OpDelay* op); 1.18 1.19 void arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack); 1.20 +#ifdef MIPS64 1.21 + void arithmetic_frem(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info = NULL); 1.22 +#endif 1.23 void arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info); 1.24 void intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op); 1.25 #ifdef ASSERT 1.26 @@ -265,6 +274,9 @@ 1.27 #ifdef TARGET_ARCH_x86 1.28 # include "c1_LIRAssembler_x86.hpp" 1.29 #endif 1.30 +#ifdef TARGET_ARCH_mips 1.31 +# include "c1_LIRAssembler_mips.hpp" 1.32 +#endif 1.33 #ifdef TARGET_ARCH_sparc 1.34 # include "c1_LIRAssembler_sparc.hpp" 1.35 #endif