1.1 --- a/src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp Wed Feb 22 14:00:34 2012 -0500
1.2 +++ b/src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp Tue Feb 21 13:14:55 2012 -0500
1.3 @@ -3231,6 +3231,26 @@
1.4 // no-op on TSO
1.5 }
1.6
1.7 +void LIR_Assembler::membar_loadload() {
1.8 + // no-op
1.9 + //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
1.10 +}
1.11 +
1.12 +void LIR_Assembler::membar_storestore() {
1.13 + // no-op
1.14 + //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
1.15 +}
1.16 +
1.17 +void LIR_Assembler::membar_loadstore() {
1.18 + // no-op
1.19 + //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
1.20 +}
1.21 +
1.22 +void LIR_Assembler::membar_storeload() {
1.23 + __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
1.24 +}
1.25 +
1.26 +
1.27 // Pack two sequential registers containing 32 bit values
1.28 // into a single 64 bit register.
1.29 // src and src->successor() are packed into dst
