1.1 --- a/src/cpu/ppc/vm/assembler_ppc.hpp Mon Apr 15 16:27:50 2019 +0000
1.2 +++ b/src/cpu/ppc/vm/assembler_ppc.hpp Wed Apr 24 11:48:37 2019 -0400
1.3 @@ -469,6 +469,8 @@
1.4 LVSR_OPCODE = (31u << OPCODE_SHIFT | 38u << 1),
1.5
1.6 // Vector-Scalar (VSX) instruction support.
1.7 + LXVD2X_OPCODE = (31u << OPCODE_SHIFT | 844u << 1),
1.8 + STXVD2X_OPCODE = (31u << OPCODE_SHIFT | 972u << 1),
1.9 MTVSRD_OPCODE = (31u << OPCODE_SHIFT | 179u << 1),
1.10 MFVSRD_OPCODE = (31u << OPCODE_SHIFT | 51u << 1),
1.11
1.12 @@ -670,8 +672,10 @@
1.13 // Atomics.
1.14 LWARX_OPCODE = (31u << OPCODE_SHIFT | 20u << 1),
1.15 LDARX_OPCODE = (31u << OPCODE_SHIFT | 84u << 1),
1.16 + LQARX_OPCODE = (31u << OPCODE_SHIFT | 276u << 1),
1.17 STWCX_OPCODE = (31u << OPCODE_SHIFT | 150u << 1),
1.18 - STDCX_OPCODE = (31u << OPCODE_SHIFT | 214u << 1)
1.19 + STDCX_OPCODE = (31u << OPCODE_SHIFT | 214u << 1),
1.20 + STQCX_OPCODE = (31u << OPCODE_SHIFT | 182u << 1)
1.21
1.22 };
1.23
1.24 @@ -1052,6 +1056,19 @@
1.25 static int vrs( VectorRegister r) { return vrs(r->encoding());}
1.26 static int vrt( VectorRegister r) { return vrt(r->encoding());}
1.27
1.28 + // Support Vector-Scalar (VSX) instructions.
1.29 + static int vsra( int x) { return opp_u_field(x, 15, 11); }
1.30 + static int vsrb( int x) { return opp_u_field(x, 20, 16); }
1.31 + static int vsrc( int x) { return opp_u_field(x, 25, 21); }
1.32 + static int vsrs( int x) { return opp_u_field(x, 10, 6); }
1.33 + static int vsrt( int x) { return opp_u_field(x, 10, 6); }
1.34 +
1.35 + static int vsra( VectorSRegister r) { return vsra(r->encoding());}
1.36 + static int vsrb( VectorSRegister r) { return vsrb(r->encoding());}
1.37 + static int vsrc( VectorSRegister r) { return vsrc(r->encoding());}
1.38 + static int vsrs( VectorSRegister r) { return vsrs(r->encoding());}
1.39 + static int vsrt( VectorSRegister r) { return vsrt(r->encoding());}
1.40 +
1.41 static int vsplt_uim( int x) { return opp_u_field(x, 15, 12); } // for vsplt* instructions
1.42 static int vsplti_sim(int x) { return opp_u_field(x, 15, 11); } // for vsplti* instructions
1.43 static int vsldoi_shb(int x) { return opp_u_field(x, 25, 22); } // for vsldoi instruction
1.44 @@ -1663,11 +1680,14 @@
1.45 // atomics
1.46 inline void lwarx_unchecked(Register d, Register a, Register b, int eh1 = 0);
1.47 inline void ldarx_unchecked(Register d, Register a, Register b, int eh1 = 0);
1.48 + inline void lqarx_unchecked(Register d, Register a, Register b, int eh1 = 0);
1.49 inline bool lxarx_hint_exclusive_access();
1.50 inline void lwarx( Register d, Register a, Register b, bool hint_exclusive_access = false);
1.51 inline void ldarx( Register d, Register a, Register b, bool hint_exclusive_access = false);
1.52 + inline void lqarx( Register d, Register a, Register b, bool hint_exclusive_access = false);
1.53 inline void stwcx_( Register s, Register a, Register b);
1.54 inline void stdcx_( Register s, Register a, Register b);
1.55 + inline void stqcx_( Register s, Register a, Register b);
1.56
1.57 // Instructions for adjusting thread priority for simultaneous
1.58 // multithreading (SMT) on Power5.
1.59 @@ -1943,6 +1963,8 @@
1.60 inline void mfvscr( VectorRegister d);
1.61
1.62 // Vector-Scalar (VSX) instructions.
1.63 + inline void lxvd2x( VectorSRegister d, Register a, Register b);
1.64 + inline void stxvd2x( VectorSRegister d, Register a, Register b);
1.65 inline void mtvrd( VectorRegister d, Register a);
1.66 inline void mfvrd( Register a, VectorRegister d);
1.67
1.68 @@ -2022,10 +2044,13 @@
1.69 // Atomics: use ra0mem to disallow R0 as base.
1.70 inline void lwarx_unchecked(Register d, Register b, int eh1);
1.71 inline void ldarx_unchecked(Register d, Register b, int eh1);
1.72 + inline void lqarx_unchecked(Register d, Register b, int eh1);
1.73 inline void lwarx( Register d, Register b, bool hint_exclusive_access);
1.74 inline void ldarx( Register d, Register b, bool hint_exclusive_access);
1.75 + inline void lqarx( Register d, Register b, bool hint_exclusive_access);
1.76 inline void stwcx_(Register s, Register b);
1.77 inline void stdcx_(Register s, Register b);
1.78 + inline void stqcx_(Register s, Register b);
1.79 inline void lfs( FloatRegister d, int si16);
1.80 inline void lfsx( FloatRegister d, Register b);
1.81 inline void lfd( FloatRegister d, int si16);
