1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/src/os_cpu/aix_ppc/vm/atomic_aix_ppc.inline.hpp Fri Sep 06 20:16:09 2013 +0200
1.3 @@ -0,0 +1,401 @@
1.4 +/*
1.5 + * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
1.6 + * Copyright 2012, 2013 SAP AG. All rights reserved.
1.7 + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
1.8 + *
1.9 + * This code is free software; you can redistribute it and/or modify it
1.10 + * under the terms of the GNU General Public License version 2 only, as
1.11 + * published by the Free Software Foundation.
1.12 + *
1.13 + * This code is distributed in the hope that it will be useful, but WITHOUT
1.14 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1.15 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1.16 + * version 2 for more details (a copy is included in the LICENSE file that
1.17 + * accompanied this code).
1.18 + *
1.19 + * You should have received a copy of the GNU General Public License version
1.20 + * 2 along with this work; if not, write to the Free Software Foundation,
1.21 + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
1.22 + *
1.23 + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
1.24 + * or visit www.oracle.com if you need additional information or have any
1.25 + * questions.
1.26 + *
1.27 + */
1.28 +
1.29 +#ifndef OS_CPU_AIX_OJDKPPC_VM_ATOMIC_AIX_PPC_INLINE_HPP
1.30 +#define OS_CPU_AIX_OJDKPPC_VM_ATOMIC_AIX_PPC_INLINE_HPP
1.31 +
1.32 +#include "orderAccess_aix_ppc.inline.hpp"
1.33 +#include "runtime/atomic.hpp"
1.34 +#include "runtime/os.hpp"
1.35 +#include "vm_version_ppc.hpp"
1.36 +
1.37 +#ifndef _LP64
1.38 +#error "Atomic currently only impleneted for PPC64"
1.39 +#endif
1.40 +
1.41 +// Implementation of class atomic
1.42 +
1.43 +inline void Atomic::store (jbyte store_value, jbyte* dest) { *dest = store_value; }
1.44 +inline void Atomic::store (jshort store_value, jshort* dest) { *dest = store_value; }
1.45 +inline void Atomic::store (jint store_value, jint* dest) { *dest = store_value; }
1.46 +inline void Atomic::store (jlong store_value, jlong* dest) { *dest = store_value; }
1.47 +inline void Atomic::store_ptr(intptr_t store_value, intptr_t* dest) { *dest = store_value; }
1.48 +inline void Atomic::store_ptr(void* store_value, void* dest) { *(void**)dest = store_value; }
1.49 +
1.50 +inline void Atomic::store (jbyte store_value, volatile jbyte* dest) { *dest = store_value; }
1.51 +inline void Atomic::store (jshort store_value, volatile jshort* dest) { *dest = store_value; }
1.52 +inline void Atomic::store (jint store_value, volatile jint* dest) { *dest = store_value; }
1.53 +inline void Atomic::store (jlong store_value, volatile jlong* dest) { *dest = store_value; }
1.54 +inline void Atomic::store_ptr(intptr_t store_value, volatile intptr_t* dest) { *dest = store_value; }
1.55 +inline void Atomic::store_ptr(void* store_value, volatile void* dest) { *(void* volatile *)dest = store_value; }
1.56 +
1.57 +inline jlong Atomic::load(volatile jlong* src) { return *src; }
1.58 +
1.59 +/*
1.60 + machine barrier instructions:
1.61 +
1.62 + - ppc_sync two-way memory barrier, aka fence
1.63 + - ppc_lwsync orders Store|Store,
1.64 + Load|Store,
1.65 + Load|Load,
1.66 + but not Store|Load
1.67 + - ppc_eieio orders memory accesses for device memory (only)
1.68 + - ppc_isync invalidates speculatively executed instructions
1.69 + From the POWER ISA 2.06 documentation:
1.70 + "[...] an isync instruction prevents the execution of
1.71 + instructions following the isync until instructions
1.72 + preceding the isync have completed, [...]"
1.73 + From IBM's AIX assembler reference:
1.74 + "The isync [...] instructions causes the processor to
1.75 + refetch any instructions that might have been fetched
1.76 + prior to the isync instruction. The instruction isync
1.77 + causes the processor to wait for all previous instructions
1.78 + to complete. Then any instructions already fetched are
1.79 + discarded and instruction processing continues in the
1.80 + environment established by the previous instructions."
1.81 +
1.82 + semantic barrier instructions:
1.83 + (as defined in orderAccess.hpp)
1.84 +
1.85 + - ppc_release orders Store|Store, (maps to ppc_lwsync)
1.86 + Load|Store
1.87 + - ppc_acquire orders Load|Store, (maps to ppc_lwsync)
1.88 + Load|Load
1.89 + - ppc_fence orders Store|Store, (maps to ppc_sync)
1.90 + Load|Store,
1.91 + Load|Load,
1.92 + Store|Load
1.93 +*/
1.94 +
1.95 +#define strasm_ppc_sync "\n sync \n"
1.96 +#define strasm_ppc_lwsync "\n lwsync \n"
1.97 +#define strasm_ppc_isync "\n isync \n"
1.98 +#define strasm_ppc_release strasm_ppc_lwsync
1.99 +#define strasm_ppc_acquire strasm_ppc_lwsync
1.100 +#define strasm_ppc_fence strasm_ppc_sync
1.101 +#define strasm_ppc_nobarrier ""
1.102 +#define strasm_ppc_nobarrier_clobber_memory ""
1.103 +
1.104 +inline jint Atomic::add (jint add_value, volatile jint* dest) {
1.105 +
1.106 + unsigned int result;
1.107 +
1.108 + __asm__ __volatile__ (
1.109 + strasm_ppc_lwsync
1.110 + "1: lwarx %0, 0, %2 \n"
1.111 + " add %0, %0, %1 \n"
1.112 + " stwcx. %0, 0, %2 \n"
1.113 + " bne- 1b \n"
1.114 + strasm_ppc_isync
1.115 + : /*%0*/"=&r" (result)
1.116 + : /*%1*/"r" (add_value), /*%2*/"r" (dest)
1.117 + : "cc", "memory" );
1.118 +
1.119 + return (jint) result;
1.120 +}
1.121 +
1.122 +
1.123 +inline intptr_t Atomic::add_ptr(intptr_t add_value, volatile intptr_t* dest) {
1.124 +
1.125 + long result;
1.126 +
1.127 + __asm__ __volatile__ (
1.128 + strasm_ppc_lwsync
1.129 + "1: ldarx %0, 0, %2 \n"
1.130 + " add %0, %0, %1 \n"
1.131 + " stdcx. %0, 0, %2 \n"
1.132 + " bne- 1b \n"
1.133 + strasm_ppc_isync
1.134 + : /*%0*/"=&r" (result)
1.135 + : /*%1*/"r" (add_value), /*%2*/"r" (dest)
1.136 + : "cc", "memory" );
1.137 +
1.138 + return (intptr_t) result;
1.139 +}
1.140 +
1.141 +inline void* Atomic::add_ptr(intptr_t add_value, volatile void* dest) {
1.142 + return (void*)add_ptr(add_value, (volatile intptr_t*)dest);
1.143 +}
1.144 +
1.145 +
1.146 +inline void Atomic::inc (volatile jint* dest) {
1.147 +
1.148 + unsigned int temp;
1.149 +
1.150 + __asm__ __volatile__ (
1.151 + strasm_ppc_nobarrier
1.152 + "1: lwarx %0, 0, %2 \n"
1.153 + " addic %0, %0, 1 \n"
1.154 + " stwcx. %0, 0, %2 \n"
1.155 + " bne- 1b \n"
1.156 + strasm_ppc_nobarrier
1.157 + : /*%0*/"=&r" (temp), "=m" (*dest)
1.158 + : /*%2*/"r" (dest), "m" (*dest)
1.159 + : "cc" strasm_ppc_nobarrier_clobber_memory);
1.160 +
1.161 +}
1.162 +
1.163 +inline void Atomic::inc_ptr(volatile intptr_t* dest) {
1.164 +
1.165 + long temp;
1.166 +
1.167 + __asm__ __volatile__ (
1.168 + strasm_ppc_nobarrier
1.169 + "1: ldarx %0, 0, %2 \n"
1.170 + " addic %0, %0, 1 \n"
1.171 + " stdcx. %0, 0, %2 \n"
1.172 + " bne- 1b \n"
1.173 + strasm_ppc_nobarrier
1.174 + : /*%0*/"=&r" (temp), "=m" (*dest)
1.175 + : /*%2*/"r" (dest), "m" (*dest)
1.176 + : "cc" strasm_ppc_nobarrier_clobber_memory);
1.177 +
1.178 +}
1.179 +
1.180 +inline void Atomic::inc_ptr(volatile void* dest) {
1.181 + inc_ptr((volatile intptr_t*)dest);
1.182 +}
1.183 +
1.184 +
1.185 +inline void Atomic::dec (volatile jint* dest) {
1.186 +
1.187 + unsigned int temp;
1.188 +
1.189 + __asm__ __volatile__ (
1.190 + strasm_ppc_nobarrier
1.191 + "1: lwarx %0, 0, %2 \n"
1.192 + " addic %0, %0, -1 \n"
1.193 + " stwcx. %0, 0, %2 \n"
1.194 + " bne- 1b \n"
1.195 + strasm_ppc_nobarrier
1.196 + : /*%0*/"=&r" (temp), "=m" (*dest)
1.197 + : /*%2*/"r" (dest), "m" (*dest)
1.198 + : "cc" strasm_ppc_nobarrier_clobber_memory);
1.199 +
1.200 +}
1.201 +
1.202 +inline void Atomic::dec_ptr(volatile intptr_t* dest) {
1.203 +
1.204 + long temp;
1.205 +
1.206 + __asm__ __volatile__ (
1.207 + strasm_ppc_nobarrier
1.208 + "1: ldarx %0, 0, %2 \n"
1.209 + " addic %0, %0, -1 \n"
1.210 + " stdcx. %0, 0, %2 \n"
1.211 + " bne- 1b \n"
1.212 + strasm_ppc_nobarrier
1.213 + : /*%0*/"=&r" (temp), "=m" (*dest)
1.214 + : /*%2*/"r" (dest), "m" (*dest)
1.215 + : "cc" strasm_ppc_nobarrier_clobber_memory);
1.216 +
1.217 +}
1.218 +
1.219 +inline void Atomic::dec_ptr(volatile void* dest) {
1.220 + dec_ptr((volatile intptr_t*)dest);
1.221 +}
1.222 +
1.223 +inline jint Atomic::xchg(jint exchange_value, volatile jint* dest) {
1.224 +
1.225 + // Note that xchg_ptr doesn't necessarily do an acquire
1.226 + // (see synchronizer.cpp).
1.227 +
1.228 + unsigned int old_value;
1.229 + const uint64_t zero = 0;
1.230 +
1.231 + __asm__ __volatile__ (
1.232 + /* lwsync */
1.233 + strasm_ppc_lwsync
1.234 + /* atomic loop */
1.235 + "1: \n"
1.236 + " lwarx %[old_value], %[dest], %[zero] \n"
1.237 + " stwcx. %[exchange_value], %[dest], %[zero] \n"
1.238 + " bne- 1b \n"
1.239 + /* isync */
1.240 + strasm_ppc_sync
1.241 + /* exit */
1.242 + "2: \n"
1.243 + /* out */
1.244 + : [old_value] "=&r" (old_value),
1.245 + "=m" (*dest)
1.246 + /* in */
1.247 + : [dest] "b" (dest),
1.248 + [zero] "r" (zero),
1.249 + [exchange_value] "r" (exchange_value),
1.250 + "m" (*dest)
1.251 + /* clobber */
1.252 + : "cc",
1.253 + "memory"
1.254 + );
1.255 +
1.256 + return (jint) old_value;
1.257 +}
1.258 +
1.259 +inline intptr_t Atomic::xchg_ptr(intptr_t exchange_value, volatile intptr_t* dest) {
1.260 +
1.261 + // Note that xchg_ptr doesn't necessarily do an acquire
1.262 + // (see synchronizer.cpp).
1.263 +
1.264 + long old_value;
1.265 + const uint64_t zero = 0;
1.266 +
1.267 + __asm__ __volatile__ (
1.268 + /* lwsync */
1.269 + strasm_ppc_lwsync
1.270 + /* atomic loop */
1.271 + "1: \n"
1.272 + " ldarx %[old_value], %[dest], %[zero] \n"
1.273 + " stdcx. %[exchange_value], %[dest], %[zero] \n"
1.274 + " bne- 1b \n"
1.275 + /* isync */
1.276 + strasm_ppc_sync
1.277 + /* exit */
1.278 + "2: \n"
1.279 + /* out */
1.280 + : [old_value] "=&r" (old_value),
1.281 + "=m" (*dest)
1.282 + /* in */
1.283 + : [dest] "b" (dest),
1.284 + [zero] "r" (zero),
1.285 + [exchange_value] "r" (exchange_value),
1.286 + "m" (*dest)
1.287 + /* clobber */
1.288 + : "cc",
1.289 + "memory"
1.290 + );
1.291 +
1.292 + return (intptr_t) old_value;
1.293 +}
1.294 +
1.295 +inline void* Atomic::xchg_ptr(void* exchange_value, volatile void* dest) {
1.296 + return (void*)xchg_ptr((intptr_t)exchange_value, (volatile intptr_t*)dest);
1.297 +}
1.298 +
1.299 +inline jint Atomic::cmpxchg(jint exchange_value, volatile jint* dest, jint compare_value) {
1.300 +
1.301 + // Note that cmpxchg guarantees a two-way memory barrier across
1.302 + // the cmpxchg, so it's really a a 'fence_cmpxchg_acquire'
1.303 + // (see atomic.hpp).
1.304 +
1.305 + unsigned int old_value;
1.306 + const uint64_t zero = 0;
1.307 +
1.308 + __asm__ __volatile__ (
1.309 + /* fence */
1.310 + strasm_ppc_sync
1.311 + /* simple guard */
1.312 + " lwz %[old_value], 0(%[dest]) \n"
1.313 + " cmpw %[compare_value], %[old_value] \n"
1.314 + " bne- 2f \n"
1.315 + /* atomic loop */
1.316 + "1: \n"
1.317 + " lwarx %[old_value], %[dest], %[zero] \n"
1.318 + " cmpw %[compare_value], %[old_value] \n"
1.319 + " bne- 2f \n"
1.320 + " stwcx. %[exchange_value], %[dest], %[zero] \n"
1.321 + " bne- 1b \n"
1.322 + /* acquire */
1.323 + strasm_ppc_sync
1.324 + /* exit */
1.325 + "2: \n"
1.326 + /* out */
1.327 + : [old_value] "=&r" (old_value),
1.328 + "=m" (*dest)
1.329 + /* in */
1.330 + : [dest] "b" (dest),
1.331 + [zero] "r" (zero),
1.332 + [compare_value] "r" (compare_value),
1.333 + [exchange_value] "r" (exchange_value),
1.334 + "m" (*dest)
1.335 + /* clobber */
1.336 + : "cc",
1.337 + "memory"
1.338 + );
1.339 +
1.340 + return (jint) old_value;
1.341 +}
1.342 +
1.343 +inline jlong Atomic::cmpxchg(jlong exchange_value, volatile jlong* dest, jlong compare_value) {
1.344 +
1.345 + // Note that cmpxchg guarantees a two-way memory barrier across
1.346 + // the cmpxchg, so it's really a a 'fence_cmpxchg_acquire'
1.347 + // (see atomic.hpp).
1.348 +
1.349 + long old_value;
1.350 + const uint64_t zero = 0;
1.351 +
1.352 + __asm__ __volatile__ (
1.353 + /* fence */
1.354 + strasm_ppc_sync
1.355 + /* simple guard */
1.356 + " ld %[old_value], 0(%[dest]) \n"
1.357 + " cmpd %[compare_value], %[old_value] \n"
1.358 + " bne- 2f \n"
1.359 + /* atomic loop */
1.360 + "1: \n"
1.361 + " ldarx %[old_value], %[dest], %[zero] \n"
1.362 + " cmpd %[compare_value], %[old_value] \n"
1.363 + " bne- 2f \n"
1.364 + " stdcx. %[exchange_value], %[dest], %[zero] \n"
1.365 + " bne- 1b \n"
1.366 + /* acquire */
1.367 + strasm_ppc_sync
1.368 + /* exit */
1.369 + "2: \n"
1.370 + /* out */
1.371 + : [old_value] "=&r" (old_value),
1.372 + "=m" (*dest)
1.373 + /* in */
1.374 + : [dest] "b" (dest),
1.375 + [zero] "r" (zero),
1.376 + [compare_value] "r" (compare_value),
1.377 + [exchange_value] "r" (exchange_value),
1.378 + "m" (*dest)
1.379 + /* clobber */
1.380 + : "cc",
1.381 + "memory"
1.382 + );
1.383 +
1.384 + return (jlong) old_value;
1.385 +}
1.386 +
1.387 +inline intptr_t Atomic::cmpxchg_ptr(intptr_t exchange_value, volatile intptr_t* dest, intptr_t compare_value) {
1.388 + return (intptr_t)cmpxchg((jlong)exchange_value, (volatile jlong*)dest, (jlong)compare_value);
1.389 +}
1.390 +
1.391 +inline void* Atomic::cmpxchg_ptr(void* exchange_value, volatile void* dest, void* compare_value) {
1.392 + return (void*)cmpxchg((jlong)exchange_value, (volatile jlong*)dest, (jlong)compare_value);
1.393 +}
1.394 +
1.395 +#undef strasm_ppc_sync
1.396 +#undef strasm_ppc_lwsync
1.397 +#undef strasm_ppc_isync
1.398 +#undef strasm_ppc_release
1.399 +#undef strasm_ppc_acquire
1.400 +#undef strasm_ppc_fence
1.401 +#undef strasm_ppc_nobarrier
1.402 +#undef strasm_ppc_nobarrier_clobber_memory
1.403 +
1.404 +#endif // OS_CPU_AIX_OJDKPPC_VM_ATOMIC_AIX_PPC_INLINE_HPP
