1.1 --- a/src/cpu/x86/vm/x86_64.ad Wed Mar 11 14:16:13 2009 -0700
1.2 +++ b/src/cpu/x86/vm/x86_64.ad Thu Mar 12 10:37:46 2009 -0700
1.3 @@ -326,7 +326,6 @@
1.4 R9, R9_H,
1.5 R10, R10_H,
1.6 R11, R11_H,
1.7 - R12, R12_H,
1.8 R13, R13_H,
1.9 R14, R14_H);
1.10
1.11 @@ -340,7 +339,6 @@
1.12 R9, R9_H,
1.13 R10, R10_H,
1.14 R11, R11_H,
1.15 - R12, R12_H,
1.16 R13, R13_H,
1.17 R14, R14_H);
1.18
1.19 @@ -354,7 +352,6 @@
1.20 R9, R9_H,
1.21 R10, R10_H,
1.22 R11, R11_H,
1.23 - R12, R12_H,
1.24 R13, R13_H,
1.25 R14, R14_H);
1.26
1.27 @@ -444,9 +441,6 @@
1.28 // Singleton class for RDX long register
1.29 reg_class long_rdx_reg(RDX, RDX_H);
1.30
1.31 -// Singleton class for R12 long register
1.32 -reg_class long_r12_reg(R12, R12_H);
1.33 -
1.34 // Class for all int registers (except RSP)
1.35 reg_class int_reg(RAX,
1.36 RDX,
1.37 @@ -1842,7 +1836,9 @@
1.38 {
1.39 if (UseCompressedOops) {
1.40 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes() #%d]\t", oopDesc::klass_offset_in_bytes());
1.41 - st->print_cr("leaq rscratch1, [r12_heapbase, r, Address::times_8, 0]");
1.42 + if (Universe::narrow_oop_shift() != 0) {
1.43 + st->print_cr("leaq rscratch1, [r12_heapbase, r, Address::times_8, 0]");
1.44 + }
1.45 st->print_cr("cmpq rax, rscratch1\t # Inline cache check");
1.46 } else {
1.47 st->print_cr("cmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes() #%d]\t"
1.48 @@ -1891,7 +1887,11 @@
1.49 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1.50 {
1.51 if (UseCompressedOops) {
1.52 - return OptoBreakpoint ? 19 : 20;
1.53 + if (Universe::narrow_oop_shift() == 0) {
1.54 + return OptoBreakpoint ? 15 : 16;
1.55 + } else {
1.56 + return OptoBreakpoint ? 19 : 20;
1.57 + }
1.58 } else {
1.59 return OptoBreakpoint ? 11 : 12;
1.60 }
1.61 @@ -2593,21 +2593,19 @@
1.62 __ movl(Rrcx, Address(Rrdi, arrayOopDesc::length_offset_in_bytes()));
1.63 __ addptr(Rrdi, arrayOopDesc::base_offset_in_bytes(T_OBJECT));
1.64 if (UseCompressedOops) {
1.65 + __ push(Rrax);
1.66 __ encode_heap_oop(Rrax);
1.67 __ repne_scanl();
1.68 - __ jcc(Assembler::notEqual, cmiss);
1.69 - __ decode_heap_oop(Rrax);
1.70 + __ pop(Rrax);
1.71 + __ jccb(Assembler::notEqual, miss);
1.72 __ movptr(Address(Rrsi,
1.73 sizeof(oopDesc) +
1.74 Klass::secondary_super_cache_offset_in_bytes()),
1.75 Rrax);
1.76 __ jmp(hit);
1.77 - __ bind(cmiss);
1.78 - __ decode_heap_oop(Rrax);
1.79 - __ jmp(miss);
1.80 } else {
1.81 __ repne_scan();
1.82 - __ jcc(Assembler::notEqual, miss);
1.83 + __ jccb(Assembler::notEqual, miss);
1.84 __ movptr(Address(Rrsi,
1.85 sizeof(oopDesc) +
1.86 Klass::secondary_super_cache_offset_in_bytes()),
1.87 @@ -4906,15 +4904,6 @@
1.88 interface(REG_INTER);
1.89 %}
1.90
1.91 -
1.92 -operand r12RegL() %{
1.93 - constraint(ALLOC_IN_RC(long_r12_reg));
1.94 - match(RegL);
1.95 -
1.96 - format %{ %}
1.97 - interface(REG_INTER);
1.98 -%}
1.99 -
1.100 operand rRegN() %{
1.101 constraint(ALLOC_IN_RC(int_reg));
1.102 match(RegN);
1.103 @@ -5289,21 +5278,6 @@
1.104 %}
1.105 %}
1.106
1.107 -// Indirect Narrow Oop Plus Offset Operand
1.108 -operand indNarrowOopOffset(rRegN src, immL32 off) %{
1.109 - constraint(ALLOC_IN_RC(ptr_reg));
1.110 - match(AddP (DecodeN src) off);
1.111 -
1.112 - op_cost(10);
1.113 - format %{"[R12 + $src << 3 + $off] (compressed oop addressing)" %}
1.114 - interface(MEMORY_INTER) %{
1.115 - base(0xc); // R12
1.116 - index($src);
1.117 - scale(0x3);
1.118 - disp($off);
1.119 - %}
1.120 -%}
1.121 -
1.122 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
1.123 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
1.124 %{
1.125 @@ -5321,6 +5295,158 @@
1.126 %}
1.127 %}
1.128
1.129 +// Indirect Narrow Oop Plus Offset Operand
1.130 +// Note: x86 architecture doesn't support "scale * index + offset" without a base
1.131 +// we can't free r12 even with Universe::narrow_oop_base() == NULL.
1.132 +operand indCompressedOopOffset(rRegN reg, immL32 off) %{
1.133 + predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0));
1.134 + constraint(ALLOC_IN_RC(ptr_reg));
1.135 + match(AddP (DecodeN reg) off);
1.136 +
1.137 + op_cost(10);
1.138 + format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
1.139 + interface(MEMORY_INTER) %{
1.140 + base(0xc); // R12
1.141 + index($reg);
1.142 + scale(0x3);
1.143 + disp($off);
1.144 + %}
1.145 +%}
1.146 +
1.147 +// Indirect Memory Operand
1.148 +operand indirectNarrow(rRegN reg)
1.149 +%{
1.150 + predicate(Universe::narrow_oop_shift() == 0);
1.151 + constraint(ALLOC_IN_RC(ptr_reg));
1.152 + match(DecodeN reg);
1.153 +
1.154 + format %{ "[$reg]" %}
1.155 + interface(MEMORY_INTER) %{
1.156 + base($reg);
1.157 + index(0x4);
1.158 + scale(0x0);
1.159 + disp(0x0);
1.160 + %}
1.161 +%}
1.162 +
1.163 +// Indirect Memory Plus Short Offset Operand
1.164 +operand indOffset8Narrow(rRegN reg, immL8 off)
1.165 +%{
1.166 + predicate(Universe::narrow_oop_shift() == 0);
1.167 + constraint(ALLOC_IN_RC(ptr_reg));
1.168 + match(AddP (DecodeN reg) off);
1.169 +
1.170 + format %{ "[$reg + $off (8-bit)]" %}
1.171 + interface(MEMORY_INTER) %{
1.172 + base($reg);
1.173 + index(0x4);
1.174 + scale(0x0);
1.175 + disp($off);
1.176 + %}
1.177 +%}
1.178 +
1.179 +// Indirect Memory Plus Long Offset Operand
1.180 +operand indOffset32Narrow(rRegN reg, immL32 off)
1.181 +%{
1.182 + predicate(Universe::narrow_oop_shift() == 0);
1.183 + constraint(ALLOC_IN_RC(ptr_reg));
1.184 + match(AddP (DecodeN reg) off);
1.185 +
1.186 + format %{ "[$reg + $off (32-bit)]" %}
1.187 + interface(MEMORY_INTER) %{
1.188 + base($reg);
1.189 + index(0x4);
1.190 + scale(0x0);
1.191 + disp($off);
1.192 + %}
1.193 +%}
1.194 +
1.195 +// Indirect Memory Plus Index Register Plus Offset Operand
1.196 +operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off)
1.197 +%{
1.198 + predicate(Universe::narrow_oop_shift() == 0);
1.199 + constraint(ALLOC_IN_RC(ptr_reg));
1.200 + match(AddP (AddP (DecodeN reg) lreg) off);
1.201 +
1.202 + op_cost(10);
1.203 + format %{"[$reg + $off + $lreg]" %}
1.204 + interface(MEMORY_INTER) %{
1.205 + base($reg);
1.206 + index($lreg);
1.207 + scale(0x0);
1.208 + disp($off);
1.209 + %}
1.210 +%}
1.211 +
1.212 +// Indirect Memory Plus Index Register Plus Offset Operand
1.213 +operand indIndexNarrow(rRegN reg, rRegL lreg)
1.214 +%{
1.215 + predicate(Universe::narrow_oop_shift() == 0);
1.216 + constraint(ALLOC_IN_RC(ptr_reg));
1.217 + match(AddP (DecodeN reg) lreg);
1.218 +
1.219 + op_cost(10);
1.220 + format %{"[$reg + $lreg]" %}
1.221 + interface(MEMORY_INTER) %{
1.222 + base($reg);
1.223 + index($lreg);
1.224 + scale(0x0);
1.225 + disp(0x0);
1.226 + %}
1.227 +%}
1.228 +
1.229 +// Indirect Memory Times Scale Plus Index Register
1.230 +operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale)
1.231 +%{
1.232 + predicate(Universe::narrow_oop_shift() == 0);
1.233 + constraint(ALLOC_IN_RC(ptr_reg));
1.234 + match(AddP (DecodeN reg) (LShiftL lreg scale));
1.235 +
1.236 + op_cost(10);
1.237 + format %{"[$reg + $lreg << $scale]" %}
1.238 + interface(MEMORY_INTER) %{
1.239 + base($reg);
1.240 + index($lreg);
1.241 + scale($scale);
1.242 + disp(0x0);
1.243 + %}
1.244 +%}
1.245 +
1.246 +// Indirect Memory Times Scale Plus Index Register Plus Offset Operand
1.247 +operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
1.248 +%{
1.249 + predicate(Universe::narrow_oop_shift() == 0);
1.250 + constraint(ALLOC_IN_RC(ptr_reg));
1.251 + match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
1.252 +
1.253 + op_cost(10);
1.254 + format %{"[$reg + $off + $lreg << $scale]" %}
1.255 + interface(MEMORY_INTER) %{
1.256 + base($reg);
1.257 + index($lreg);
1.258 + scale($scale);
1.259 + disp($off);
1.260 + %}
1.261 +%}
1.262 +
1.263 +// Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
1.264 +operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
1.265 +%{
1.266 + constraint(ALLOC_IN_RC(ptr_reg));
1.267 + predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
1.268 + match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
1.269 +
1.270 + op_cost(10);
1.271 + format %{"[$reg + $off + $idx << $scale]" %}
1.272 + interface(MEMORY_INTER) %{
1.273 + base($reg);
1.274 + index($idx);
1.275 + scale($scale);
1.276 + disp($off);
1.277 + %}
1.278 +%}
1.279 +
1.280 +
1.281 //----------Special Memory Operands--------------------------------------------
1.282 // Stack Slot Operand - This operand is used for loading and storing temporary
1.283 // values on the stack where a match requires a value to
1.284 @@ -5488,7 +5614,10 @@
1.285
1.286 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
1.287 indIndexScale, indIndexScaleOffset, indPosIndexScaleOffset,
1.288 - indNarrowOopOffset);
1.289 + indCompressedOopOffset,
1.290 + indirectNarrow, indOffset8Narrow, indOffset32Narrow,
1.291 + indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
1.292 + indIndexScaleOffsetNarrow, indPosIndexScaleOffsetNarrow);
1.293
1.294 //----------PIPELINE-----------------------------------------------------------
1.295 // Rules which define the behavior of the target architectures pipeline.
1.296 @@ -6234,9 +6363,7 @@
1.297 ins_cost(125); // XXX
1.298 format %{ "movl $dst, $mem\t# compressed ptr" %}
1.299 ins_encode %{
1.300 - Address addr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
1.301 - Register dst = as_Register($dst$$reg);
1.302 - __ movl(dst, addr);
1.303 + __ movl($dst$$Register, $mem$$Address);
1.304 %}
1.305 ins_pipe(ialu_reg_mem); // XXX
1.306 %}
1.307 @@ -6262,9 +6389,7 @@
1.308 ins_cost(125); // XXX
1.309 format %{ "movl $dst, $mem\t# compressed klass ptr" %}
1.310 ins_encode %{
1.311 - Address addr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
1.312 - Register dst = as_Register($dst$$reg);
1.313 - __ movl(dst, addr);
1.314 + __ movl($dst$$Register, $mem$$Address);
1.315 %}
1.316 ins_pipe(ialu_reg_mem); // XXX
1.317 %}
1.318 @@ -6418,6 +6543,102 @@
1.319 ins_pipe(ialu_reg_reg_fat);
1.320 %}
1.321
1.322 +instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
1.323 +%{
1.324 + match(Set dst mem);
1.325 +
1.326 + ins_cost(110);
1.327 + format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %}
1.328 + opcode(0x8D);
1.329 + ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
1.330 + ins_pipe(ialu_reg_reg_fat);
1.331 +%}
1.332 +
1.333 +// Load Effective Address which uses Narrow (32-bits) oop
1.334 +instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem)
1.335 +%{
1.336 + predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0));
1.337 + match(Set dst mem);
1.338 +
1.339 + ins_cost(110);
1.340 + format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %}
1.341 + opcode(0x8D);
1.342 + ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
1.343 + ins_pipe(ialu_reg_reg_fat);
1.344 +%}
1.345 +
1.346 +instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem)
1.347 +%{
1.348 + predicate(Universe::narrow_oop_shift() == 0);
1.349 + match(Set dst mem);
1.350 +
1.351 + ins_cost(110); // XXX
1.352 + format %{ "leaq $dst, $mem\t# ptr off8narrow" %}
1.353 + opcode(0x8D);
1.354 + ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
1.355 + ins_pipe(ialu_reg_reg_fat);
1.356 +%}
1.357 +
1.358 +instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem)
1.359 +%{
1.360 + predicate(Universe::narrow_oop_shift() == 0);
1.361 + match(Set dst mem);
1.362 +
1.363 + ins_cost(110);
1.364 + format %{ "leaq $dst, $mem\t# ptr off32narrow" %}
1.365 + opcode(0x8D);
1.366 + ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
1.367 + ins_pipe(ialu_reg_reg_fat);
1.368 +%}
1.369 +
1.370 +instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem)
1.371 +%{
1.372 + predicate(Universe::narrow_oop_shift() == 0);
1.373 + match(Set dst mem);
1.374 +
1.375 + ins_cost(110);
1.376 + format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %}
1.377 + opcode(0x8D);
1.378 + ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
1.379 + ins_pipe(ialu_reg_reg_fat);
1.380 +%}
1.381 +
1.382 +instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem)
1.383 +%{
1.384 + predicate(Universe::narrow_oop_shift() == 0);
1.385 + match(Set dst mem);
1.386 +
1.387 + ins_cost(110);
1.388 + format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %}
1.389 + opcode(0x8D);
1.390 + ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
1.391 + ins_pipe(ialu_reg_reg_fat);
1.392 +%}
1.393 +
1.394 +instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem)
1.395 +%{
1.396 + predicate(Universe::narrow_oop_shift() == 0);
1.397 + match(Set dst mem);
1.398 +
1.399 + ins_cost(110);
1.400 + format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %}
1.401 + opcode(0x8D);
1.402 + ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
1.403 + ins_pipe(ialu_reg_reg_fat);
1.404 +%}
1.405 +
1.406 +instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
1.407 +%{
1.408 + predicate(Universe::narrow_oop_shift() == 0);
1.409 + match(Set dst mem);
1.410 +
1.411 + ins_cost(110);
1.412 + format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %}
1.413 + opcode(0x8D);
1.414 + ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
1.415 + ins_pipe(ialu_reg_reg_fat);
1.416 +%}
1.417 +
1.418 instruct loadConI(rRegI dst, immI src)
1.419 %{
1.420 match(Set dst src);
1.421 @@ -6528,8 +6749,7 @@
1.422 effect(KILL cr);
1.423 format %{ "xorq $dst, $src\t# compressed NULL ptr" %}
1.424 ins_encode %{
1.425 - Register dst = $dst$$Register;
1.426 - __ xorq(dst, dst);
1.427 + __ xorq($dst$$Register, $dst$$Register);
1.428 %}
1.429 ins_pipe(ialu_reg);
1.430 %}
1.431 @@ -6541,11 +6761,10 @@
1.432 format %{ "movl $dst, $src\t# compressed ptr" %}
1.433 ins_encode %{
1.434 address con = (address)$src$$constant;
1.435 - Register dst = $dst$$Register;
1.436 if (con == NULL) {
1.437 ShouldNotReachHere();
1.438 } else {
1.439 - __ set_narrow_oop(dst, (jobject)$src$$constant);
1.440 + __ set_narrow_oop($dst$$Register, (jobject)$src$$constant);
1.441 }
1.442 %}
1.443 ins_pipe(ialu_reg_fat); // XXX
1.444 @@ -6794,12 +7013,25 @@
1.445 ins_pipe(ialu_mem_reg);
1.446 %}
1.447
1.448 +instruct storeImmP0(memory mem, immP0 zero)
1.449 +%{
1.450 + predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
1.451 + match(Set mem (StoreP mem zero));
1.452 +
1.453 + ins_cost(125); // XXX
1.454 + format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %}
1.455 + ins_encode %{
1.456 + __ movq($mem$$Address, r12);
1.457 + %}
1.458 + ins_pipe(ialu_mem_reg);
1.459 +%}
1.460 +
1.461 // Store NULL Pointer, mark word, or other simple pointer constant.
1.462 instruct storeImmP(memory mem, immP31 src)
1.463 %{
1.464 match(Set mem (StoreP mem src));
1.465
1.466 - ins_cost(125); // XXX
1.467 + ins_cost(150); // XXX
1.468 format %{ "movq $mem, $src\t# ptr" %}
1.469 opcode(0xC7); /* C7 /0 */
1.470 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
1.471 @@ -6814,14 +7046,55 @@
1.472 ins_cost(125); // XXX
1.473 format %{ "movl $mem, $src\t# compressed ptr" %}
1.474 ins_encode %{
1.475 - Address addr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
1.476 - Register src = as_Register($src$$reg);
1.477 - __ movl(addr, src);
1.478 + __ movl($mem$$Address, $src$$Register);
1.479 %}
1.480 ins_pipe(ialu_mem_reg);
1.481 %}
1.482
1.483 +instruct storeImmN0(memory mem, immN0 zero)
1.484 +%{
1.485 + predicate(Universe::narrow_oop_base() == NULL);
1.486 + match(Set mem (StoreN mem zero));
1.487 +
1.488 + ins_cost(125); // XXX
1.489 + format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %}
1.490 + ins_encode %{
1.491 + __ movl($mem$$Address, r12);
1.492 + %}
1.493 + ins_pipe(ialu_mem_reg);
1.494 +%}
1.495 +
1.496 +instruct storeImmN(memory mem, immN src)
1.497 +%{
1.498 + match(Set mem (StoreN mem src));
1.499 +
1.500 + ins_cost(150); // XXX
1.501 + format %{ "movl $mem, $src\t# compressed ptr" %}
1.502 + ins_encode %{
1.503 + address con = (address)$src$$constant;
1.504 + if (con == NULL) {
1.505 + __ movl($mem$$Address, (int32_t)0);
1.506 + } else {
1.507 + __ set_narrow_oop($mem$$Address, (jobject)$src$$constant);
1.508 + }
1.509 + %}
1.510 + ins_pipe(ialu_mem_imm);
1.511 +%}
1.512 +
1.513 // Store Integer Immediate
1.514 +instruct storeImmI0(memory mem, immI0 zero)
1.515 +%{
1.516 + predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
1.517 + match(Set mem (StoreI mem zero));
1.518 +
1.519 + ins_cost(125); // XXX
1.520 + format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %}
1.521 + ins_encode %{
1.522 + __ movl($mem$$Address, r12);
1.523 + %}
1.524 + ins_pipe(ialu_mem_reg);
1.525 +%}
1.526 +
1.527 instruct storeImmI(memory mem, immI src)
1.528 %{
1.529 match(Set mem (StoreI mem src));
1.530 @@ -6834,6 +7107,19 @@
1.531 %}
1.532
1.533 // Store Long Immediate
1.534 +instruct storeImmL0(memory mem, immL0 zero)
1.535 +%{
1.536 + predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
1.537 + match(Set mem (StoreL mem zero));
1.538 +
1.539 + ins_cost(125); // XXX
1.540 + format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %}
1.541 + ins_encode %{
1.542 + __ movq($mem$$Address, r12);
1.543 + %}
1.544 + ins_pipe(ialu_mem_reg);
1.545 +%}
1.546 +
1.547 instruct storeImmL(memory mem, immL32 src)
1.548 %{
1.549 match(Set mem (StoreL mem src));
1.550 @@ -6846,6 +7132,19 @@
1.551 %}
1.552
1.553 // Store Short/Char Immediate
1.554 +instruct storeImmC0(memory mem, immI0 zero)
1.555 +%{
1.556 + predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
1.557 + match(Set mem (StoreC mem zero));
1.558 +
1.559 + ins_cost(125); // XXX
1.560 + format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %}
1.561 + ins_encode %{
1.562 + __ movw($mem$$Address, r12);
1.563 + %}
1.564 + ins_pipe(ialu_mem_reg);
1.565 +%}
1.566 +
1.567 instruct storeImmI16(memory mem, immI16 src)
1.568 %{
1.569 predicate(UseStoreImmI16);
1.570 @@ -6859,6 +7158,19 @@
1.571 %}
1.572
1.573 // Store Byte Immediate
1.574 +instruct storeImmB0(memory mem, immI0 zero)
1.575 +%{
1.576 + predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
1.577 + match(Set mem (StoreB mem zero));
1.578 +
1.579 + ins_cost(125); // XXX
1.580 + format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %}
1.581 + ins_encode %{
1.582 + __ movb($mem$$Address, r12);
1.583 + %}
1.584 + ins_pipe(ialu_mem_reg);
1.585 +%}
1.586 +
1.587 instruct storeImmB(memory mem, immI8 src)
1.588 %{
1.589 match(Set mem (StoreB mem src));
1.590 @@ -6898,6 +7210,19 @@
1.591 %}
1.592
1.593 // Store CMS card-mark Immediate
1.594 +instruct storeImmCM0_reg(memory mem, immI0 zero)
1.595 +%{
1.596 + predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
1.597 + match(Set mem (StoreCM mem zero));
1.598 +
1.599 + ins_cost(125); // XXX
1.600 + format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %}
1.601 + ins_encode %{
1.602 + __ movb($mem$$Address, r12);
1.603 + %}
1.604 + ins_pipe(ialu_mem_reg);
1.605 +%}
1.606 +
1.607 instruct storeImmCM0(memory mem, immI0 src)
1.608 %{
1.609 match(Set mem (StoreCM mem src));
1.610 @@ -6931,6 +7256,19 @@
1.611 %}
1.612
1.613 // Store immediate Float value (it is faster than store from XMM register)
1.614 +instruct storeF0(memory mem, immF0 zero)
1.615 +%{
1.616 + predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
1.617 + match(Set mem (StoreF mem zero));
1.618 +
1.619 + ins_cost(25); // XXX
1.620 + format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %}
1.621 + ins_encode %{
1.622 + __ movl($mem$$Address, r12);
1.623 + %}
1.624 + ins_pipe(ialu_mem_reg);
1.625 +%}
1.626 +
1.627 instruct storeF_imm(memory mem, immF src)
1.628 %{
1.629 match(Set mem (StoreF mem src));
1.630 @@ -6957,6 +7295,7 @@
1.631 // Store immediate double 0.0 (it is faster than store from XMM register)
1.632 instruct storeD0_imm(memory mem, immD0 src)
1.633 %{
1.634 + predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
1.635 match(Set mem (StoreD mem src));
1.636
1.637 ins_cost(50);
1.638 @@ -6966,6 +7305,19 @@
1.639 ins_pipe(ialu_mem_imm);
1.640 %}
1.641
1.642 +instruct storeD0(memory mem, immD0 zero)
1.643 +%{
1.644 + predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
1.645 + match(Set mem (StoreD mem zero));
1.646 +
1.647 + ins_cost(25); // XXX
1.648 + format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %}
1.649 + ins_encode %{
1.650 + __ movq($mem$$Address, r12);
1.651 + %}
1.652 + ins_pipe(ialu_mem_reg);
1.653 +%}
1.654 +
1.655 instruct storeSSI(stackSlotI dst, rRegI src)
1.656 %{
1.657 match(Set dst src);
1.658 @@ -7192,9 +7544,7 @@
1.659 effect(KILL cr);
1.660 format %{ "encode_heap_oop_not_null $dst,$src" %}
1.661 ins_encode %{
1.662 - Register s = $src$$Register;
1.663 - Register d = $dst$$Register;
1.664 - __ encode_heap_oop_not_null(d, s);
1.665 + __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
1.666 %}
1.667 ins_pipe(ialu_reg_long);
1.668 %}
1.669 @@ -7224,7 +7574,11 @@
1.670 ins_encode %{
1.671 Register s = $src$$Register;
1.672 Register d = $dst$$Register;
1.673 - __ decode_heap_oop_not_null(d, s);
1.674 + if (s != d) {
1.675 + __ decode_heap_oop_not_null(d, s);
1.676 + } else {
1.677 + __ decode_heap_oop_not_null(d);
1.678 + }
1.679 %}
1.680 ins_pipe(ialu_reg_long);
1.681 %}
1.682 @@ -11389,8 +11743,9 @@
1.683
1.684 // This will generate a signed flags result. This should be OK since
1.685 // any compare to a zero should be eq/neq.
1.686 -instruct testP_reg_mem(rFlagsReg cr, memory op, immP0 zero)
1.687 -%{
1.688 +instruct testP_mem(rFlagsReg cr, memory op, immP0 zero)
1.689 +%{
1.690 + predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
1.691 match(Set cr (CmpP (LoadP op) zero));
1.692
1.693 ins_cost(500); // XXX
1.694 @@ -11401,13 +11756,24 @@
1.695 ins_pipe(ialu_cr_reg_imm);
1.696 %}
1.697
1.698 +instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero)
1.699 +%{
1.700 + predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
1.701 + match(Set cr (CmpP (LoadP mem) zero));
1.702 +
1.703 + format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %}
1.704 + ins_encode %{
1.705 + __ cmpq(r12, $mem$$Address);
1.706 + %}
1.707 + ins_pipe(ialu_cr_reg_mem);
1.708 +%}
1.709
1.710 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
1.711 %{
1.712 match(Set cr (CmpN op1 op2));
1.713
1.714 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
1.715 - ins_encode %{ __ cmpl(as_Register($op1$$reg), as_Register($op2$$reg)); %}
1.716 + ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %}
1.717 ins_pipe(ialu_cr_reg_reg);
1.718 %}
1.719
1.720 @@ -11415,11 +11781,30 @@
1.721 %{
1.722 match(Set cr (CmpN src (LoadN mem)));
1.723
1.724 - ins_cost(500); // XXX
1.725 - format %{ "cmpl $src, mem\t# compressed ptr" %}
1.726 + format %{ "cmpl $src, $mem\t# compressed ptr" %}
1.727 ins_encode %{
1.728 - Address adr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
1.729 - __ cmpl(as_Register($src$$reg), adr);
1.730 + __ cmpl($src$$Register, $mem$$Address);
1.731 + %}
1.732 + ins_pipe(ialu_cr_reg_mem);
1.733 +%}
1.734 +
1.735 +instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{
1.736 + match(Set cr (CmpN op1 op2));
1.737 +
1.738 + format %{ "cmpl $op1, $op2\t# compressed ptr" %}
1.739 + ins_encode %{
1.740 + __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant);
1.741 + %}
1.742 + ins_pipe(ialu_cr_reg_imm);
1.743 +%}
1.744 +
1.745 +instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src)
1.746 +%{
1.747 + match(Set cr (CmpN src (LoadN mem)));
1.748 +
1.749 + format %{ "cmpl $mem, $src\t# compressed ptr" %}
1.750 + ins_encode %{
1.751 + __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant);
1.752 %}
1.753 ins_pipe(ialu_cr_reg_mem);
1.754 %}
1.755 @@ -11432,15 +11817,27 @@
1.756 ins_pipe(ialu_cr_reg_imm);
1.757 %}
1.758
1.759 -instruct testN_reg_mem(rFlagsReg cr, memory mem, immN0 zero)
1.760 -%{
1.761 +instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero)
1.762 +%{
1.763 + predicate(Universe::narrow_oop_base() != NULL);
1.764 match(Set cr (CmpN (LoadN mem) zero));
1.765
1.766 ins_cost(500); // XXX
1.767 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %}
1.768 ins_encode %{
1.769 - Address addr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
1.770 - __ cmpl(addr, (int)0xFFFFFFFF);
1.771 + __ cmpl($mem$$Address, (int)0xFFFFFFFF);
1.772 + %}
1.773 + ins_pipe(ialu_cr_reg_mem);
1.774 +%}
1.775 +
1.776 +instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero)
1.777 +%{
1.778 + predicate(Universe::narrow_oop_base() == NULL);
1.779 + match(Set cr (CmpN (LoadN mem) zero));
1.780 +
1.781 + format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %}
1.782 + ins_encode %{
1.783 + __ cmpl(r12, $mem$$Address);
1.784 %}
1.785 ins_pipe(ialu_cr_reg_mem);
1.786 %}
1.787 @@ -11472,7 +11869,6 @@
1.788 %{
1.789 match(Set cr (CmpL op1 (LoadL op2)));
1.790
1.791 - ins_cost(500); // XXX
1.792 format %{ "cmpq $op1, $op2" %}
1.793 opcode(0x3B); /* Opcode 3B /r */
1.794 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
1.795 @@ -11756,7 +12152,6 @@
1.796 rdi_RegP result)
1.797 %{
1.798 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
1.799 - predicate(!UseCompressedOops); // decoding oop kills condition codes
1.800 effect(KILL rcx, KILL result);
1.801
1.802 ins_cost(1000);
