1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/src/cpu/x86/vm/x86.ad Tue Dec 20 00:55:02 2011 -0800
1.3 @@ -0,0 +1,777 @@
1.4 +//
1.5 +// Copyright (c) 2011, Oracle and/or its affiliates. All rights reserved.
1.6 +// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
1.7 +//
1.8 +// This code is free software; you can redistribute it and/or modify it
1.9 +// under the terms of the GNU General Public License version 2 only, as
1.10 +// published by the Free Software Foundation.
1.11 +//
1.12 +// This code is distributed in the hope that it will be useful, but WITHOUT
1.13 +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1.14 +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1.15 +// version 2 for more details (a copy is included in the LICENSE file that
1.16 +// accompanied this code).
1.17 +//
1.18 +// You should have received a copy of the GNU General Public License version
1.19 +// 2 along with this work; if not, write to the Free Software Foundation,
1.20 +// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
1.21 +//
1.22 +// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
1.23 +// or visit www.oracle.com if you need additional information or have any
1.24 +// questions.
1.25 +//
1.26 +//
1.27 +
1.28 +// X86 Common Architecture Description File
1.29 +
1.30 +source %{
1.31 + // Float masks come from different places depending on platform.
1.32 +#ifdef _LP64
1.33 + static address float_signmask() { return StubRoutines::x86::float_sign_mask(); }
1.34 + static address float_signflip() { return StubRoutines::x86::float_sign_flip(); }
1.35 + static address double_signmask() { return StubRoutines::x86::double_sign_mask(); }
1.36 + static address double_signflip() { return StubRoutines::x86::double_sign_flip(); }
1.37 +#else
1.38 + static address float_signmask() { return (address)float_signmask_pool; }
1.39 + static address float_signflip() { return (address)float_signflip_pool; }
1.40 + static address double_signmask() { return (address)double_signmask_pool; }
1.41 + static address double_signflip() { return (address)double_signflip_pool; }
1.42 +#endif
1.43 +%}
1.44 +
1.45 +// INSTRUCTIONS -- Platform independent definitions (same for 32- and 64-bit)
1.46 +
1.47 +instruct addF_reg(regF dst, regF src) %{
1.48 + predicate((UseSSE>=1) && (UseAVX == 0));
1.49 + match(Set dst (AddF dst src));
1.50 +
1.51 + format %{ "addss $dst, $src" %}
1.52 + ins_cost(150);
1.53 + ins_encode %{
1.54 + __ addss($dst$$XMMRegister, $src$$XMMRegister);
1.55 + %}
1.56 + ins_pipe(pipe_slow);
1.57 +%}
1.58 +
1.59 +instruct addF_mem(regF dst, memory src) %{
1.60 + predicate((UseSSE>=1) && (UseAVX == 0));
1.61 + match(Set dst (AddF dst (LoadF src)));
1.62 +
1.63 + format %{ "addss $dst, $src" %}
1.64 + ins_cost(150);
1.65 + ins_encode %{
1.66 + __ addss($dst$$XMMRegister, $src$$Address);
1.67 + %}
1.68 + ins_pipe(pipe_slow);
1.69 +%}
1.70 +
1.71 +instruct addF_imm(regF dst, immF con) %{
1.72 + predicate((UseSSE>=1) && (UseAVX == 0));
1.73 + match(Set dst (AddF dst con));
1.74 + format %{ "addss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
1.75 + ins_cost(150);
1.76 + ins_encode %{
1.77 + __ addss($dst$$XMMRegister, $constantaddress($con));
1.78 + %}
1.79 + ins_pipe(pipe_slow);
1.80 +%}
1.81 +
1.82 +instruct vaddF_reg(regF dst, regF src1, regF src2) %{
1.83 + predicate(UseAVX > 0);
1.84 + match(Set dst (AddF src1 src2));
1.85 +
1.86 + format %{ "vaddss $dst, $src1, $src2" %}
1.87 + ins_cost(150);
1.88 + ins_encode %{
1.89 + __ vaddss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister);
1.90 + %}
1.91 + ins_pipe(pipe_slow);
1.92 +%}
1.93 +
1.94 +instruct vaddF_mem(regF dst, regF src1, memory src2) %{
1.95 + predicate(UseAVX > 0);
1.96 + match(Set dst (AddF src1 (LoadF src2)));
1.97 +
1.98 + format %{ "vaddss $dst, $src1, $src2" %}
1.99 + ins_cost(150);
1.100 + ins_encode %{
1.101 + __ vaddss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address);
1.102 + %}
1.103 + ins_pipe(pipe_slow);
1.104 +%}
1.105 +
1.106 +instruct vaddF_imm(regF dst, regF src, immF con) %{
1.107 + predicate(UseAVX > 0);
1.108 + match(Set dst (AddF src con));
1.109 +
1.110 + format %{ "vaddss $dst, $src, [$constantaddress]\t# load from constant table: float=$con" %}
1.111 + ins_cost(150);
1.112 + ins_encode %{
1.113 + __ vaddss($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con));
1.114 + %}
1.115 + ins_pipe(pipe_slow);
1.116 +%}
1.117 +
1.118 +instruct addD_reg(regD dst, regD src) %{
1.119 + predicate((UseSSE>=2) && (UseAVX == 0));
1.120 + match(Set dst (AddD dst src));
1.121 +
1.122 + format %{ "addsd $dst, $src" %}
1.123 + ins_cost(150);
1.124 + ins_encode %{
1.125 + __ addsd($dst$$XMMRegister, $src$$XMMRegister);
1.126 + %}
1.127 + ins_pipe(pipe_slow);
1.128 +%}
1.129 +
1.130 +instruct addD_mem(regD dst, memory src) %{
1.131 + predicate((UseSSE>=2) && (UseAVX == 0));
1.132 + match(Set dst (AddD dst (LoadD src)));
1.133 +
1.134 + format %{ "addsd $dst, $src" %}
1.135 + ins_cost(150);
1.136 + ins_encode %{
1.137 + __ addsd($dst$$XMMRegister, $src$$Address);
1.138 + %}
1.139 + ins_pipe(pipe_slow);
1.140 +%}
1.141 +
1.142 +instruct addD_imm(regD dst, immD con) %{
1.143 + predicate((UseSSE>=2) && (UseAVX == 0));
1.144 + match(Set dst (AddD dst con));
1.145 + format %{ "addsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
1.146 + ins_cost(150);
1.147 + ins_encode %{
1.148 + __ addsd($dst$$XMMRegister, $constantaddress($con));
1.149 + %}
1.150 + ins_pipe(pipe_slow);
1.151 +%}
1.152 +
1.153 +instruct vaddD_reg(regD dst, regD src1, regD src2) %{
1.154 + predicate(UseAVX > 0);
1.155 + match(Set dst (AddD src1 src2));
1.156 +
1.157 + format %{ "vaddsd $dst, $src1, $src2" %}
1.158 + ins_cost(150);
1.159 + ins_encode %{
1.160 + __ vaddsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister);
1.161 + %}
1.162 + ins_pipe(pipe_slow);
1.163 +%}
1.164 +
1.165 +instruct vaddD_mem(regD dst, regD src1, memory src2) %{
1.166 + predicate(UseAVX > 0);
1.167 + match(Set dst (AddD src1 (LoadD src2)));
1.168 +
1.169 + format %{ "vaddsd $dst, $src1, $src2" %}
1.170 + ins_cost(150);
1.171 + ins_encode %{
1.172 + __ vaddsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address);
1.173 + %}
1.174 + ins_pipe(pipe_slow);
1.175 +%}
1.176 +
1.177 +instruct vaddD_imm(regD dst, regD src, immD con) %{
1.178 + predicate(UseAVX > 0);
1.179 + match(Set dst (AddD src con));
1.180 +
1.181 + format %{ "vaddsd $dst, $src, [$constantaddress]\t# load from constant table: double=$con" %}
1.182 + ins_cost(150);
1.183 + ins_encode %{
1.184 + __ vaddsd($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con));
1.185 + %}
1.186 + ins_pipe(pipe_slow);
1.187 +%}
1.188 +
1.189 +instruct subF_reg(regF dst, regF src) %{
1.190 + predicate((UseSSE>=1) && (UseAVX == 0));
1.191 + match(Set dst (SubF dst src));
1.192 +
1.193 + format %{ "subss $dst, $src" %}
1.194 + ins_cost(150);
1.195 + ins_encode %{
1.196 + __ subss($dst$$XMMRegister, $src$$XMMRegister);
1.197 + %}
1.198 + ins_pipe(pipe_slow);
1.199 +%}
1.200 +
1.201 +instruct subF_mem(regF dst, memory src) %{
1.202 + predicate((UseSSE>=1) && (UseAVX == 0));
1.203 + match(Set dst (SubF dst (LoadF src)));
1.204 +
1.205 + format %{ "subss $dst, $src" %}
1.206 + ins_cost(150);
1.207 + ins_encode %{
1.208 + __ subss($dst$$XMMRegister, $src$$Address);
1.209 + %}
1.210 + ins_pipe(pipe_slow);
1.211 +%}
1.212 +
1.213 +instruct subF_imm(regF dst, immF con) %{
1.214 + predicate((UseSSE>=1) && (UseAVX == 0));
1.215 + match(Set dst (SubF dst con));
1.216 + format %{ "subss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
1.217 + ins_cost(150);
1.218 + ins_encode %{
1.219 + __ subss($dst$$XMMRegister, $constantaddress($con));
1.220 + %}
1.221 + ins_pipe(pipe_slow);
1.222 +%}
1.223 +
1.224 +instruct vsubF_reg(regF dst, regF src1, regF src2) %{
1.225 + predicate(UseAVX > 0);
1.226 + match(Set dst (SubF src1 src2));
1.227 +
1.228 + format %{ "vsubss $dst, $src1, $src2" %}
1.229 + ins_cost(150);
1.230 + ins_encode %{
1.231 + __ vsubss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister);
1.232 + %}
1.233 + ins_pipe(pipe_slow);
1.234 +%}
1.235 +
1.236 +instruct vsubF_mem(regF dst, regF src1, memory src2) %{
1.237 + predicate(UseAVX > 0);
1.238 + match(Set dst (SubF src1 (LoadF src2)));
1.239 +
1.240 + format %{ "vsubss $dst, $src1, $src2" %}
1.241 + ins_cost(150);
1.242 + ins_encode %{
1.243 + __ vsubss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address);
1.244 + %}
1.245 + ins_pipe(pipe_slow);
1.246 +%}
1.247 +
1.248 +instruct vsubF_imm(regF dst, regF src, immF con) %{
1.249 + predicate(UseAVX > 0);
1.250 + match(Set dst (SubF src con));
1.251 +
1.252 + format %{ "vsubss $dst, $src, [$constantaddress]\t# load from constant table: float=$con" %}
1.253 + ins_cost(150);
1.254 + ins_encode %{
1.255 + __ vsubss($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con));
1.256 + %}
1.257 + ins_pipe(pipe_slow);
1.258 +%}
1.259 +
1.260 +instruct subD_reg(regD dst, regD src) %{
1.261 + predicate((UseSSE>=2) && (UseAVX == 0));
1.262 + match(Set dst (SubD dst src));
1.263 +
1.264 + format %{ "subsd $dst, $src" %}
1.265 + ins_cost(150);
1.266 + ins_encode %{
1.267 + __ subsd($dst$$XMMRegister, $src$$XMMRegister);
1.268 + %}
1.269 + ins_pipe(pipe_slow);
1.270 +%}
1.271 +
1.272 +instruct subD_mem(regD dst, memory src) %{
1.273 + predicate((UseSSE>=2) && (UseAVX == 0));
1.274 + match(Set dst (SubD dst (LoadD src)));
1.275 +
1.276 + format %{ "subsd $dst, $src" %}
1.277 + ins_cost(150);
1.278 + ins_encode %{
1.279 + __ subsd($dst$$XMMRegister, $src$$Address);
1.280 + %}
1.281 + ins_pipe(pipe_slow);
1.282 +%}
1.283 +
1.284 +instruct subD_imm(regD dst, immD con) %{
1.285 + predicate((UseSSE>=2) && (UseAVX == 0));
1.286 + match(Set dst (SubD dst con));
1.287 + format %{ "subsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
1.288 + ins_cost(150);
1.289 + ins_encode %{
1.290 + __ subsd($dst$$XMMRegister, $constantaddress($con));
1.291 + %}
1.292 + ins_pipe(pipe_slow);
1.293 +%}
1.294 +
1.295 +instruct vsubD_reg(regD dst, regD src1, regD src2) %{
1.296 + predicate(UseAVX > 0);
1.297 + match(Set dst (SubD src1 src2));
1.298 +
1.299 + format %{ "vsubsd $dst, $src1, $src2" %}
1.300 + ins_cost(150);
1.301 + ins_encode %{
1.302 + __ vsubsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister);
1.303 + %}
1.304 + ins_pipe(pipe_slow);
1.305 +%}
1.306 +
1.307 +instruct vsubD_mem(regD dst, regD src1, memory src2) %{
1.308 + predicate(UseAVX > 0);
1.309 + match(Set dst (SubD src1 (LoadD src2)));
1.310 +
1.311 + format %{ "vsubsd $dst, $src1, $src2" %}
1.312 + ins_cost(150);
1.313 + ins_encode %{
1.314 + __ vsubsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address);
1.315 + %}
1.316 + ins_pipe(pipe_slow);
1.317 +%}
1.318 +
1.319 +instruct vsubD_imm(regD dst, regD src, immD con) %{
1.320 + predicate(UseAVX > 0);
1.321 + match(Set dst (SubD src con));
1.322 +
1.323 + format %{ "vsubsd $dst, $src, [$constantaddress]\t# load from constant table: double=$con" %}
1.324 + ins_cost(150);
1.325 + ins_encode %{
1.326 + __ vsubsd($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con));
1.327 + %}
1.328 + ins_pipe(pipe_slow);
1.329 +%}
1.330 +
1.331 +instruct mulF_reg(regF dst, regF src) %{
1.332 + predicate((UseSSE>=1) && (UseAVX == 0));
1.333 + match(Set dst (MulF dst src));
1.334 +
1.335 + format %{ "mulss $dst, $src" %}
1.336 + ins_cost(150);
1.337 + ins_encode %{
1.338 + __ mulss($dst$$XMMRegister, $src$$XMMRegister);
1.339 + %}
1.340 + ins_pipe(pipe_slow);
1.341 +%}
1.342 +
1.343 +instruct mulF_mem(regF dst, memory src) %{
1.344 + predicate((UseSSE>=1) && (UseAVX == 0));
1.345 + match(Set dst (MulF dst (LoadF src)));
1.346 +
1.347 + format %{ "mulss $dst, $src" %}
1.348 + ins_cost(150);
1.349 + ins_encode %{
1.350 + __ mulss($dst$$XMMRegister, $src$$Address);
1.351 + %}
1.352 + ins_pipe(pipe_slow);
1.353 +%}
1.354 +
1.355 +instruct mulF_imm(regF dst, immF con) %{
1.356 + predicate((UseSSE>=1) && (UseAVX == 0));
1.357 + match(Set dst (MulF dst con));
1.358 + format %{ "mulss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
1.359 + ins_cost(150);
1.360 + ins_encode %{
1.361 + __ mulss($dst$$XMMRegister, $constantaddress($con));
1.362 + %}
1.363 + ins_pipe(pipe_slow);
1.364 +%}
1.365 +
1.366 +instruct vmulF_reg(regF dst, regF src1, regF src2) %{
1.367 + predicate(UseAVX > 0);
1.368 + match(Set dst (MulF src1 src2));
1.369 +
1.370 + format %{ "vmulss $dst, $src1, $src2" %}
1.371 + ins_cost(150);
1.372 + ins_encode %{
1.373 + __ vmulss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister);
1.374 + %}
1.375 + ins_pipe(pipe_slow);
1.376 +%}
1.377 +
1.378 +instruct vmulF_mem(regF dst, regF src1, memory src2) %{
1.379 + predicate(UseAVX > 0);
1.380 + match(Set dst (MulF src1 (LoadF src2)));
1.381 +
1.382 + format %{ "vmulss $dst, $src1, $src2" %}
1.383 + ins_cost(150);
1.384 + ins_encode %{
1.385 + __ vmulss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address);
1.386 + %}
1.387 + ins_pipe(pipe_slow);
1.388 +%}
1.389 +
1.390 +instruct vmulF_imm(regF dst, regF src, immF con) %{
1.391 + predicate(UseAVX > 0);
1.392 + match(Set dst (MulF src con));
1.393 +
1.394 + format %{ "vmulss $dst, $src, [$constantaddress]\t# load from constant table: float=$con" %}
1.395 + ins_cost(150);
1.396 + ins_encode %{
1.397 + __ vmulss($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con));
1.398 + %}
1.399 + ins_pipe(pipe_slow);
1.400 +%}
1.401 +
1.402 +instruct mulD_reg(regD dst, regD src) %{
1.403 + predicate((UseSSE>=2) && (UseAVX == 0));
1.404 + match(Set dst (MulD dst src));
1.405 +
1.406 + format %{ "mulsd $dst, $src" %}
1.407 + ins_cost(150);
1.408 + ins_encode %{
1.409 + __ mulsd($dst$$XMMRegister, $src$$XMMRegister);
1.410 + %}
1.411 + ins_pipe(pipe_slow);
1.412 +%}
1.413 +
1.414 +instruct mulD_mem(regD dst, memory src) %{
1.415 + predicate((UseSSE>=2) && (UseAVX == 0));
1.416 + match(Set dst (MulD dst (LoadD src)));
1.417 +
1.418 + format %{ "mulsd $dst, $src" %}
1.419 + ins_cost(150);
1.420 + ins_encode %{
1.421 + __ mulsd($dst$$XMMRegister, $src$$Address);
1.422 + %}
1.423 + ins_pipe(pipe_slow);
1.424 +%}
1.425 +
1.426 +instruct mulD_imm(regD dst, immD con) %{
1.427 + predicate((UseSSE>=2) && (UseAVX == 0));
1.428 + match(Set dst (MulD dst con));
1.429 + format %{ "mulsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
1.430 + ins_cost(150);
1.431 + ins_encode %{
1.432 + __ mulsd($dst$$XMMRegister, $constantaddress($con));
1.433 + %}
1.434 + ins_pipe(pipe_slow);
1.435 +%}
1.436 +
1.437 +instruct vmulD_reg(regD dst, regD src1, regD src2) %{
1.438 + predicate(UseAVX > 0);
1.439 + match(Set dst (MulD src1 src2));
1.440 +
1.441 + format %{ "vmulsd $dst, $src1, $src2" %}
1.442 + ins_cost(150);
1.443 + ins_encode %{
1.444 + __ vmulsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister);
1.445 + %}
1.446 + ins_pipe(pipe_slow);
1.447 +%}
1.448 +
1.449 +instruct vmulD_mem(regD dst, regD src1, memory src2) %{
1.450 + predicate(UseAVX > 0);
1.451 + match(Set dst (MulD src1 (LoadD src2)));
1.452 +
1.453 + format %{ "vmulsd $dst, $src1, $src2" %}
1.454 + ins_cost(150);
1.455 + ins_encode %{
1.456 + __ vmulsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address);
1.457 + %}
1.458 + ins_pipe(pipe_slow);
1.459 +%}
1.460 +
1.461 +instruct vmulD_imm(regD dst, regD src, immD con) %{
1.462 + predicate(UseAVX > 0);
1.463 + match(Set dst (MulD src con));
1.464 +
1.465 + format %{ "vmulsd $dst, $src, [$constantaddress]\t# load from constant table: double=$con" %}
1.466 + ins_cost(150);
1.467 + ins_encode %{
1.468 + __ vmulsd($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con));
1.469 + %}
1.470 + ins_pipe(pipe_slow);
1.471 +%}
1.472 +
1.473 +instruct divF_reg(regF dst, regF src) %{
1.474 + predicate((UseSSE>=1) && (UseAVX == 0));
1.475 + match(Set dst (DivF dst src));
1.476 +
1.477 + format %{ "divss $dst, $src" %}
1.478 + ins_cost(150);
1.479 + ins_encode %{
1.480 + __ divss($dst$$XMMRegister, $src$$XMMRegister);
1.481 + %}
1.482 + ins_pipe(pipe_slow);
1.483 +%}
1.484 +
1.485 +instruct divF_mem(regF dst, memory src) %{
1.486 + predicate((UseSSE>=1) && (UseAVX == 0));
1.487 + match(Set dst (DivF dst (LoadF src)));
1.488 +
1.489 + format %{ "divss $dst, $src" %}
1.490 + ins_cost(150);
1.491 + ins_encode %{
1.492 + __ divss($dst$$XMMRegister, $src$$Address);
1.493 + %}
1.494 + ins_pipe(pipe_slow);
1.495 +%}
1.496 +
1.497 +instruct divF_imm(regF dst, immF con) %{
1.498 + predicate((UseSSE>=1) && (UseAVX == 0));
1.499 + match(Set dst (DivF dst con));
1.500 + format %{ "divss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
1.501 + ins_cost(150);
1.502 + ins_encode %{
1.503 + __ divss($dst$$XMMRegister, $constantaddress($con));
1.504 + %}
1.505 + ins_pipe(pipe_slow);
1.506 +%}
1.507 +
1.508 +instruct vdivF_reg(regF dst, regF src1, regF src2) %{
1.509 + predicate(UseAVX > 0);
1.510 + match(Set dst (DivF src1 src2));
1.511 +
1.512 + format %{ "vdivss $dst, $src1, $src2" %}
1.513 + ins_cost(150);
1.514 + ins_encode %{
1.515 + __ vdivss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister);
1.516 + %}
1.517 + ins_pipe(pipe_slow);
1.518 +%}
1.519 +
1.520 +instruct vdivF_mem(regF dst, regF src1, memory src2) %{
1.521 + predicate(UseAVX > 0);
1.522 + match(Set dst (DivF src1 (LoadF src2)));
1.523 +
1.524 + format %{ "vdivss $dst, $src1, $src2" %}
1.525 + ins_cost(150);
1.526 + ins_encode %{
1.527 + __ vdivss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address);
1.528 + %}
1.529 + ins_pipe(pipe_slow);
1.530 +%}
1.531 +
1.532 +instruct vdivF_imm(regF dst, regF src, immF con) %{
1.533 + predicate(UseAVX > 0);
1.534 + match(Set dst (DivF src con));
1.535 +
1.536 + format %{ "vdivss $dst, $src, [$constantaddress]\t# load from constant table: float=$con" %}
1.537 + ins_cost(150);
1.538 + ins_encode %{
1.539 + __ vdivss($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con));
1.540 + %}
1.541 + ins_pipe(pipe_slow);
1.542 +%}
1.543 +
1.544 +instruct divD_reg(regD dst, regD src) %{
1.545 + predicate((UseSSE>=2) && (UseAVX == 0));
1.546 + match(Set dst (DivD dst src));
1.547 +
1.548 + format %{ "divsd $dst, $src" %}
1.549 + ins_cost(150);
1.550 + ins_encode %{
1.551 + __ divsd($dst$$XMMRegister, $src$$XMMRegister);
1.552 + %}
1.553 + ins_pipe(pipe_slow);
1.554 +%}
1.555 +
1.556 +instruct divD_mem(regD dst, memory src) %{
1.557 + predicate((UseSSE>=2) && (UseAVX == 0));
1.558 + match(Set dst (DivD dst (LoadD src)));
1.559 +
1.560 + format %{ "divsd $dst, $src" %}
1.561 + ins_cost(150);
1.562 + ins_encode %{
1.563 + __ divsd($dst$$XMMRegister, $src$$Address);
1.564 + %}
1.565 + ins_pipe(pipe_slow);
1.566 +%}
1.567 +
1.568 +instruct divD_imm(regD dst, immD con) %{
1.569 + predicate((UseSSE>=2) && (UseAVX == 0));
1.570 + match(Set dst (DivD dst con));
1.571 + format %{ "divsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
1.572 + ins_cost(150);
1.573 + ins_encode %{
1.574 + __ divsd($dst$$XMMRegister, $constantaddress($con));
1.575 + %}
1.576 + ins_pipe(pipe_slow);
1.577 +%}
1.578 +
1.579 +instruct vdivD_reg(regD dst, regD src1, regD src2) %{
1.580 + predicate(UseAVX > 0);
1.581 + match(Set dst (DivD src1 src2));
1.582 +
1.583 + format %{ "vdivsd $dst, $src1, $src2" %}
1.584 + ins_cost(150);
1.585 + ins_encode %{
1.586 + __ vdivsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister);
1.587 + %}
1.588 + ins_pipe(pipe_slow);
1.589 +%}
1.590 +
1.591 +instruct vdivD_mem(regD dst, regD src1, memory src2) %{
1.592 + predicate(UseAVX > 0);
1.593 + match(Set dst (DivD src1 (LoadD src2)));
1.594 +
1.595 + format %{ "vdivsd $dst, $src1, $src2" %}
1.596 + ins_cost(150);
1.597 + ins_encode %{
1.598 + __ vdivsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address);
1.599 + %}
1.600 + ins_pipe(pipe_slow);
1.601 +%}
1.602 +
1.603 +instruct vdivD_imm(regD dst, regD src, immD con) %{
1.604 + predicate(UseAVX > 0);
1.605 + match(Set dst (DivD src con));
1.606 +
1.607 + format %{ "vdivsd $dst, $src, [$constantaddress]\t# load from constant table: double=$con" %}
1.608 + ins_cost(150);
1.609 + ins_encode %{
1.610 + __ vdivsd($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con));
1.611 + %}
1.612 + ins_pipe(pipe_slow);
1.613 +%}
1.614 +
1.615 +instruct absF_reg(regF dst) %{
1.616 + predicate((UseSSE>=1) && (UseAVX == 0));
1.617 + match(Set dst (AbsF dst));
1.618 + ins_cost(150);
1.619 + format %{ "andps $dst, [0x7fffffff]\t# abs float by sign masking" %}
1.620 + ins_encode %{
1.621 + __ andps($dst$$XMMRegister, ExternalAddress(float_signmask()));
1.622 + %}
1.623 + ins_pipe(pipe_slow);
1.624 +%}
1.625 +
1.626 +instruct vabsF_reg(regF dst, regF src) %{
1.627 + predicate(UseAVX > 0);
1.628 + match(Set dst (AbsF src));
1.629 + ins_cost(150);
1.630 + format %{ "vandps $dst, $src, [0x7fffffff]\t# abs float by sign masking" %}
1.631 + ins_encode %{
1.632 + __ vandps($dst$$XMMRegister, $src$$XMMRegister,
1.633 + ExternalAddress(float_signmask()));
1.634 + %}
1.635 + ins_pipe(pipe_slow);
1.636 +%}
1.637 +
1.638 +instruct absD_reg(regD dst) %{
1.639 + predicate((UseSSE>=2) && (UseAVX == 0));
1.640 + match(Set dst (AbsD dst));
1.641 + ins_cost(150);
1.642 + format %{ "andpd $dst, [0x7fffffffffffffff]\t"
1.643 + "# abs double by sign masking" %}
1.644 + ins_encode %{
1.645 + __ andpd($dst$$XMMRegister, ExternalAddress(double_signmask()));
1.646 + %}
1.647 + ins_pipe(pipe_slow);
1.648 +%}
1.649 +
1.650 +instruct vabsD_reg(regD dst, regD src) %{
1.651 + predicate(UseAVX > 0);
1.652 + match(Set dst (AbsD src));
1.653 + ins_cost(150);
1.654 + format %{ "vandpd $dst, $src, [0x7fffffffffffffff]\t"
1.655 + "# abs double by sign masking" %}
1.656 + ins_encode %{
1.657 + __ vandpd($dst$$XMMRegister, $src$$XMMRegister,
1.658 + ExternalAddress(double_signmask()));
1.659 + %}
1.660 + ins_pipe(pipe_slow);
1.661 +%}
1.662 +
1.663 +instruct negF_reg(regF dst) %{
1.664 + predicate((UseSSE>=1) && (UseAVX == 0));
1.665 + match(Set dst (NegF dst));
1.666 + ins_cost(150);
1.667 + format %{ "xorps $dst, [0x80000000]\t# neg float by sign flipping" %}
1.668 + ins_encode %{
1.669 + __ xorps($dst$$XMMRegister, ExternalAddress(float_signflip()));
1.670 + %}
1.671 + ins_pipe(pipe_slow);
1.672 +%}
1.673 +
1.674 +instruct vnegF_reg(regF dst, regF src) %{
1.675 + predicate(UseAVX > 0);
1.676 + match(Set dst (NegF src));
1.677 + ins_cost(150);
1.678 + format %{ "vxorps $dst, $src, [0x80000000]\t# neg float by sign flipping" %}
1.679 + ins_encode %{
1.680 + __ vxorps($dst$$XMMRegister, $src$$XMMRegister,
1.681 + ExternalAddress(float_signflip()));
1.682 + %}
1.683 + ins_pipe(pipe_slow);
1.684 +%}
1.685 +
1.686 +instruct negD_reg(regD dst) %{
1.687 + predicate((UseSSE>=2) && (UseAVX == 0));
1.688 + match(Set dst (NegD dst));
1.689 + ins_cost(150);
1.690 + format %{ "xorpd $dst, [0x8000000000000000]\t"
1.691 + "# neg double by sign flipping" %}
1.692 + ins_encode %{
1.693 + __ xorpd($dst$$XMMRegister, ExternalAddress(double_signflip()));
1.694 + %}
1.695 + ins_pipe(pipe_slow);
1.696 +%}
1.697 +
1.698 +instruct vnegD_reg(regD dst, regD src) %{
1.699 + predicate(UseAVX > 0);
1.700 + match(Set dst (NegD src));
1.701 + ins_cost(150);
1.702 + format %{ "vxorpd $dst, $src, [0x8000000000000000]\t"
1.703 + "# neg double by sign flipping" %}
1.704 + ins_encode %{
1.705 + __ vxorpd($dst$$XMMRegister, $src$$XMMRegister,
1.706 + ExternalAddress(double_signflip()));
1.707 + %}
1.708 + ins_pipe(pipe_slow);
1.709 +%}
1.710 +
1.711 +instruct sqrtF_reg(regF dst, regF src) %{
1.712 + predicate(UseSSE>=1);
1.713 + match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
1.714 +
1.715 + format %{ "sqrtss $dst, $src" %}
1.716 + ins_cost(150);
1.717 + ins_encode %{
1.718 + __ sqrtss($dst$$XMMRegister, $src$$XMMRegister);
1.719 + %}
1.720 + ins_pipe(pipe_slow);
1.721 +%}
1.722 +
1.723 +instruct sqrtF_mem(regF dst, memory src) %{
1.724 + predicate(UseSSE>=1);
1.725 + match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF src)))));
1.726 +
1.727 + format %{ "sqrtss $dst, $src" %}
1.728 + ins_cost(150);
1.729 + ins_encode %{
1.730 + __ sqrtss($dst$$XMMRegister, $src$$Address);
1.731 + %}
1.732 + ins_pipe(pipe_slow);
1.733 +%}
1.734 +
1.735 +instruct sqrtF_imm(regF dst, immF con) %{
1.736 + predicate(UseSSE>=1);
1.737 + match(Set dst (ConvD2F (SqrtD (ConvF2D con))));
1.738 + format %{ "sqrtss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
1.739 + ins_cost(150);
1.740 + ins_encode %{
1.741 + __ sqrtss($dst$$XMMRegister, $constantaddress($con));
1.742 + %}
1.743 + ins_pipe(pipe_slow);
1.744 +%}
1.745 +
1.746 +instruct sqrtD_reg(regD dst, regD src) %{
1.747 + predicate(UseSSE>=2);
1.748 + match(Set dst (SqrtD src));
1.749 +
1.750 + format %{ "sqrtsd $dst, $src" %}
1.751 + ins_cost(150);
1.752 + ins_encode %{
1.753 + __ sqrtsd($dst$$XMMRegister, $src$$XMMRegister);
1.754 + %}
1.755 + ins_pipe(pipe_slow);
1.756 +%}
1.757 +
1.758 +instruct sqrtD_mem(regD dst, memory src) %{
1.759 + predicate(UseSSE>=2);
1.760 + match(Set dst (SqrtD (LoadD src)));
1.761 +
1.762 + format %{ "sqrtsd $dst, $src" %}
1.763 + ins_cost(150);
1.764 + ins_encode %{
1.765 + __ sqrtsd($dst$$XMMRegister, $src$$Address);
1.766 + %}
1.767 + ins_pipe(pipe_slow);
1.768 +%}
1.769 +
1.770 +instruct sqrtD_imm(regD dst, immD con) %{
1.771 + predicate(UseSSE>=2);
1.772 + match(Set dst (SqrtD con));
1.773 + format %{ "sqrtsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
1.774 + ins_cost(150);
1.775 + ins_encode %{
1.776 + __ sqrtsd($dst$$XMMRegister, $constantaddress($con));
1.777 + %}
1.778 + ins_pipe(pipe_slow);
1.779 +%}
1.780 +
