1.1 --- a/src/cpu/x86/vm/assembler_x86.cpp Mon Dec 19 14:16:23 2011 -0800
1.2 +++ b/src/cpu/x86/vm/assembler_x86.cpp Tue Dec 20 00:55:02 2011 -0800
1.3 @@ -2932,6 +2932,161 @@
1.4 emit_operand(dst, src);
1.5 }
1.6
1.7 +// AVX 3-operands non destructive source instructions (encoded with VEX prefix)
1.8 +
1.9 +void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
1.10 + assert(VM_Version::supports_avx(), "");
1.11 + InstructionMark im(this);
1.12 + vex_prefix(dst, nds, src, VEX_SIMD_F2);
1.13 + emit_byte(0x58);
1.14 + emit_operand(dst, src);
1.15 +}
1.16 +
1.17 +void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1.18 + assert(VM_Version::supports_avx(), "");
1.19 + int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F2);
1.20 + emit_byte(0x58);
1.21 + emit_byte(0xC0 | encode);
1.22 +}
1.23 +
1.24 +void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
1.25 + assert(VM_Version::supports_avx(), "");
1.26 + InstructionMark im(this);
1.27 + vex_prefix(dst, nds, src, VEX_SIMD_F3);
1.28 + emit_byte(0x58);
1.29 + emit_operand(dst, src);
1.30 +}
1.31 +
1.32 +void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1.33 + assert(VM_Version::supports_avx(), "");
1.34 + int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F3);
1.35 + emit_byte(0x58);
1.36 + emit_byte(0xC0 | encode);
1.37 +}
1.38 +
1.39 +void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src) {
1.40 + assert(VM_Version::supports_avx(), "");
1.41 + InstructionMark im(this);
1.42 + vex_prefix(dst, nds, src, VEX_SIMD_66); // 128-bit vector
1.43 + emit_byte(0x54);
1.44 + emit_operand(dst, src);
1.45 +}
1.46 +
1.47 +void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src) {
1.48 + assert(VM_Version::supports_avx(), "");
1.49 + InstructionMark im(this);
1.50 + vex_prefix(dst, nds, src, VEX_SIMD_NONE); // 128-bit vector
1.51 + emit_byte(0x54);
1.52 + emit_operand(dst, src);
1.53 +}
1.54 +
1.55 +void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
1.56 + assert(VM_Version::supports_avx(), "");
1.57 + InstructionMark im(this);
1.58 + vex_prefix(dst, nds, src, VEX_SIMD_F2);
1.59 + emit_byte(0x5E);
1.60 + emit_operand(dst, src);
1.61 +}
1.62 +
1.63 +void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1.64 + assert(VM_Version::supports_avx(), "");
1.65 + int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F2);
1.66 + emit_byte(0x5E);
1.67 + emit_byte(0xC0 | encode);
1.68 +}
1.69 +
1.70 +void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
1.71 + assert(VM_Version::supports_avx(), "");
1.72 + InstructionMark im(this);
1.73 + vex_prefix(dst, nds, src, VEX_SIMD_F3);
1.74 + emit_byte(0x5E);
1.75 + emit_operand(dst, src);
1.76 +}
1.77 +
1.78 +void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1.79 + assert(VM_Version::supports_avx(), "");
1.80 + int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F3);
1.81 + emit_byte(0x5E);
1.82 + emit_byte(0xC0 | encode);
1.83 +}
1.84 +
1.85 +void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
1.86 + assert(VM_Version::supports_avx(), "");
1.87 + InstructionMark im(this);
1.88 + vex_prefix(dst, nds, src, VEX_SIMD_F2);
1.89 + emit_byte(0x59);
1.90 + emit_operand(dst, src);
1.91 +}
1.92 +
1.93 +void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1.94 + assert(VM_Version::supports_avx(), "");
1.95 + int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F2);
1.96 + emit_byte(0x59);
1.97 + emit_byte(0xC0 | encode);
1.98 +}
1.99 +
1.100 +void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
1.101 + InstructionMark im(this);
1.102 + vex_prefix(dst, nds, src, VEX_SIMD_F3);
1.103 + emit_byte(0x59);
1.104 + emit_operand(dst, src);
1.105 +}
1.106 +
1.107 +void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1.108 + assert(VM_Version::supports_avx(), "");
1.109 + int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F3);
1.110 + emit_byte(0x59);
1.111 + emit_byte(0xC0 | encode);
1.112 +}
1.113 +
1.114 +
1.115 +void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
1.116 + assert(VM_Version::supports_avx(), "");
1.117 + InstructionMark im(this);
1.118 + vex_prefix(dst, nds, src, VEX_SIMD_F2);
1.119 + emit_byte(0x5C);
1.120 + emit_operand(dst, src);
1.121 +}
1.122 +
1.123 +void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1.124 + assert(VM_Version::supports_avx(), "");
1.125 + int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F2);
1.126 + emit_byte(0x5C);
1.127 + emit_byte(0xC0 | encode);
1.128 +}
1.129 +
1.130 +void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
1.131 + assert(VM_Version::supports_avx(), "");
1.132 + InstructionMark im(this);
1.133 + vex_prefix(dst, nds, src, VEX_SIMD_F3);
1.134 + emit_byte(0x5C);
1.135 + emit_operand(dst, src);
1.136 +}
1.137 +
1.138 +void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1.139 + assert(VM_Version::supports_avx(), "");
1.140 + int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F3);
1.141 + emit_byte(0x5C);
1.142 + emit_byte(0xC0 | encode);
1.143 +}
1.144 +
1.145 +void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src) {
1.146 + assert(VM_Version::supports_avx(), "");
1.147 + InstructionMark im(this);
1.148 + vex_prefix(dst, nds, src, VEX_SIMD_66); // 128-bit vector
1.149 + emit_byte(0x57);
1.150 + emit_operand(dst, src);
1.151 +}
1.152 +
1.153 +void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src) {
1.154 + assert(VM_Version::supports_avx(), "");
1.155 + InstructionMark im(this);
1.156 + vex_prefix(dst, nds, src, VEX_SIMD_NONE); // 128-bit vector
1.157 + emit_byte(0x57);
1.158 + emit_operand(dst, src);
1.159 +}
1.160 +
1.161 +
1.162 #ifndef _LP64
1.163 // 32bit only pieces of the assembler
1.164
1.165 @@ -7235,6 +7390,157 @@
1.166 }
1.167 }
1.168
1.169 +void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
1.170 + if (reachable(src)) {
1.171 + Assembler::ucomisd(dst, as_Address(src));
1.172 + } else {
1.173 + lea(rscratch1, src);
1.174 + Assembler::ucomisd(dst, Address(rscratch1, 0));
1.175 + }
1.176 +}
1.177 +
1.178 +void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
1.179 + if (reachable(src)) {
1.180 + Assembler::ucomiss(dst, as_Address(src));
1.181 + } else {
1.182 + lea(rscratch1, src);
1.183 + Assembler::ucomiss(dst, Address(rscratch1, 0));
1.184 + }
1.185 +}
1.186 +
1.187 +void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
1.188 + // Used in sign-bit flipping with aligned address.
1.189 + assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1.190 + if (reachable(src)) {
1.191 + Assembler::xorpd(dst, as_Address(src));
1.192 + } else {
1.193 + lea(rscratch1, src);
1.194 + Assembler::xorpd(dst, Address(rscratch1, 0));
1.195 + }
1.196 +}
1.197 +
1.198 +void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
1.199 + // Used in sign-bit flipping with aligned address.
1.200 + assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1.201 + if (reachable(src)) {
1.202 + Assembler::xorps(dst, as_Address(src));
1.203 + } else {
1.204 + lea(rscratch1, src);
1.205 + Assembler::xorps(dst, Address(rscratch1, 0));
1.206 + }
1.207 +}
1.208 +
1.209 +// AVX 3-operands instructions
1.210 +
1.211 +void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
1.212 + if (reachable(src)) {
1.213 + vaddsd(dst, nds, as_Address(src));
1.214 + } else {
1.215 + lea(rscratch1, src);
1.216 + vaddsd(dst, nds, Address(rscratch1, 0));
1.217 + }
1.218 +}
1.219 +
1.220 +void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
1.221 + if (reachable(src)) {
1.222 + vaddss(dst, nds, as_Address(src));
1.223 + } else {
1.224 + lea(rscratch1, src);
1.225 + vaddss(dst, nds, Address(rscratch1, 0));
1.226 + }
1.227 +}
1.228 +
1.229 +void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
1.230 + if (reachable(src)) {
1.231 + vandpd(dst, nds, as_Address(src));
1.232 + } else {
1.233 + lea(rscratch1, src);
1.234 + vandpd(dst, nds, Address(rscratch1, 0));
1.235 + }
1.236 +}
1.237 +
1.238 +void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
1.239 + if (reachable(src)) {
1.240 + vandps(dst, nds, as_Address(src));
1.241 + } else {
1.242 + lea(rscratch1, src);
1.243 + vandps(dst, nds, Address(rscratch1, 0));
1.244 + }
1.245 +}
1.246 +
1.247 +void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
1.248 + if (reachable(src)) {
1.249 + vdivsd(dst, nds, as_Address(src));
1.250 + } else {
1.251 + lea(rscratch1, src);
1.252 + vdivsd(dst, nds, Address(rscratch1, 0));
1.253 + }
1.254 +}
1.255 +
1.256 +void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
1.257 + if (reachable(src)) {
1.258 + vdivss(dst, nds, as_Address(src));
1.259 + } else {
1.260 + lea(rscratch1, src);
1.261 + vdivss(dst, nds, Address(rscratch1, 0));
1.262 + }
1.263 +}
1.264 +
1.265 +void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
1.266 + if (reachable(src)) {
1.267 + vmulsd(dst, nds, as_Address(src));
1.268 + } else {
1.269 + lea(rscratch1, src);
1.270 + vmulsd(dst, nds, Address(rscratch1, 0));
1.271 + }
1.272 +}
1.273 +
1.274 +void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
1.275 + if (reachable(src)) {
1.276 + vmulss(dst, nds, as_Address(src));
1.277 + } else {
1.278 + lea(rscratch1, src);
1.279 + vmulss(dst, nds, Address(rscratch1, 0));
1.280 + }
1.281 +}
1.282 +
1.283 +void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
1.284 + if (reachable(src)) {
1.285 + vsubsd(dst, nds, as_Address(src));
1.286 + } else {
1.287 + lea(rscratch1, src);
1.288 + vsubsd(dst, nds, Address(rscratch1, 0));
1.289 + }
1.290 +}
1.291 +
1.292 +void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
1.293 + if (reachable(src)) {
1.294 + vsubss(dst, nds, as_Address(src));
1.295 + } else {
1.296 + lea(rscratch1, src);
1.297 + vsubss(dst, nds, Address(rscratch1, 0));
1.298 + }
1.299 +}
1.300 +
1.301 +void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
1.302 + if (reachable(src)) {
1.303 + vxorpd(dst, nds, as_Address(src));
1.304 + } else {
1.305 + lea(rscratch1, src);
1.306 + vxorpd(dst, nds, Address(rscratch1, 0));
1.307 + }
1.308 +}
1.309 +
1.310 +void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
1.311 + if (reachable(src)) {
1.312 + vxorps(dst, nds, as_Address(src));
1.313 + } else {
1.314 + lea(rscratch1, src);
1.315 + vxorps(dst, nds, Address(rscratch1, 0));
1.316 + }
1.317 +}
1.318 +
1.319 +
1.320 //////////////////////////////////////////////////////////////////////////////////
1.321 #ifndef SERIALGC
1.322
1.323 @@ -8119,46 +8425,6 @@
1.324 }
1.325
1.326
1.327 -void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
1.328 - if (reachable(src)) {
1.329 - Assembler::ucomisd(dst, as_Address(src));
1.330 - } else {
1.331 - lea(rscratch1, src);
1.332 - Assembler::ucomisd(dst, Address(rscratch1, 0));
1.333 - }
1.334 -}
1.335 -
1.336 -void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
1.337 - if (reachable(src)) {
1.338 - Assembler::ucomiss(dst, as_Address(src));
1.339 - } else {
1.340 - lea(rscratch1, src);
1.341 - Assembler::ucomiss(dst, Address(rscratch1, 0));
1.342 - }
1.343 -}
1.344 -
1.345 -void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
1.346 - // Used in sign-bit flipping with aligned address.
1.347 - assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1.348 - if (reachable(src)) {
1.349 - Assembler::xorpd(dst, as_Address(src));
1.350 - } else {
1.351 - lea(rscratch1, src);
1.352 - Assembler::xorpd(dst, Address(rscratch1, 0));
1.353 - }
1.354 -}
1.355 -
1.356 -void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
1.357 - // Used in sign-bit flipping with aligned address.
1.358 - assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1.359 - if (reachable(src)) {
1.360 - Assembler::xorps(dst, as_Address(src));
1.361 - } else {
1.362 - lea(rscratch1, src);
1.363 - Assembler::xorps(dst, Address(rscratch1, 0));
1.364 - }
1.365 -}
1.366 -
1.367 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
1.368 if (VM_Version::supports_cmov()) {
1.369 cmovl(cc, dst, src);
