src/cpu/mips/vm/mips_64.ad

changeset 9450
5df11fc40ae4
parent 9260
ba3aac24b68d
child 9458
076aa91d2dd8
     1.1 --- a/src/cpu/mips/vm/mips_64.ad	Thu Dec 27 11:59:22 2018 +0800
     1.2 +++ b/src/cpu/mips/vm/mips_64.ad	Thu Dec 27 12:24:53 2018 +0800
     1.3 @@ -704,7 +704,7 @@
     1.4  }
     1.5  
     1.6  // Vector ideal reg
     1.7 -const int Matcher::vector_ideal_reg(int size) {
     1.8 +const uint Matcher::vector_ideal_reg(int size) {
     1.9    assert(MaxVectorSize == 8, "");
    1.10    switch(size) {
    1.11      case  8: return Op_VecD;
    1.12 @@ -714,7 +714,7 @@
    1.13  }
    1.14  
    1.15  // Only lowest bits of xmm reg are used for vector shift count.
    1.16 -const int Matcher::vector_shift_count_ideal_reg(int size) {
    1.17 +const uint Matcher::vector_shift_count_ideal_reg(int size) {
    1.18    fatal("vector shift is not supported");
    1.19    return Node::NotAMachineReg;
    1.20  }

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