src/cpu/mips/vm/mips_64.ad

changeset 331
592fd7ca9efb
parent 330
71b95a0448a7
child 332
0b618b424c57
     1.1 --- a/src/cpu/mips/vm/mips_64.ad	Wed Feb 22 22:02:26 2017 +0800
     1.2 +++ b/src/cpu/mips/vm/mips_64.ad	Wed Feb 22 22:24:24 2017 +0800
     1.3 @@ -3608,6 +3608,15 @@
     1.4    interface(CONST_INTER);
     1.5  %}
     1.6  
     1.7 +operand immI_MaxI() %{
     1.8 +  predicate(n->get_int() == 2147483647);
     1.9 +  match(ConI);
    1.10 +
    1.11 +  op_cost(0);
    1.12 +  format %{ %}
    1.13 +  interface(CONST_INTER);
    1.14 +%}
    1.15 +
    1.16  // Valid scale values for addressing modes
    1.17  operand immI2() %{
    1.18    predicate(0 <= n->get_int() && (n->get_int() <= 3));
    1.19 @@ -11052,6 +11061,20 @@
    1.20    ins_pipe( ialu_regL_regL );
    1.21  %}
    1.22  
    1.23 +instruct slrL_Reg_immI_0_31_and_max_int(mRegI dst, mRegL src, immI_0_31 shift, immI_MaxI max_int) %{
    1.24 +  match(Set dst (AndI (ConvL2I (URShiftL src shift)) max_int));
    1.25 +  ins_cost(80);
    1.26 +  format %{ "dext    $dst, $src, $shift, 31 @ slrL_Reg_immI_0_31_and_max_int" %}
    1.27 +  ins_encode %{
    1.28 +    Register src_reg = as_Register($src$$reg);
    1.29 +    Register dst_reg = as_Register($dst$$reg);
    1.30 +    int        shamt = $shift$$constant;
    1.31 +
    1.32 +    __ dext(dst_reg, src_reg, shamt, 31);
    1.33 +  %}
    1.34 +  ins_pipe( ialu_regL_regL );
    1.35 +%}
    1.36 +
    1.37  instruct slrL_P2XReg_immI_0_31(mRegL dst, mRegP src, immI_0_31 shift) %{
    1.38    match(Set dst (URShiftL (CastP2X src) shift));
    1.39    ins_cost(80);

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