1.1 --- a/src/cpu/mips/vm/mips_64.ad Thu Aug 03 16:06:12 2017 +0800
1.2 +++ b/src/cpu/mips/vm/mips_64.ad Mon Aug 07 09:58:19 2017 +0800
1.3 @@ -8130,6 +8130,108 @@
1.4 ins_pipe( pipe_slow );
1.5 %}
1.6
1.7 +instruct cmovP_cmpU_reg_reg(mRegP dst, mRegP src, mRegI tmp1, mRegI tmp2, cmpOpU cop ) %{
1.8 + match(Set dst (CMoveP (Binary cop (CmpU tmp1 tmp2)) (Binary dst src)));
1.9 + ins_cost(80);
1.10 + format %{
1.11 + "CMPU$cop $tmp1,$tmp2\t @cmovP_cmpU_reg_reg\n\t"
1.12 + "CMOV $dst,$src\t @cmovP_cmpU_reg_reg"
1.13 + %}
1.14 + ins_encode %{
1.15 + Register op1 = $tmp1$$Register;
1.16 + Register op2 = $tmp2$$Register;
1.17 + Register dst = $dst$$Register;
1.18 + Register src = $src$$Register;
1.19 + int flag = $cop$$cmpcode;
1.20 +
1.21 + switch(flag)
1.22 + {
1.23 + case 0x01: //equal
1.24 + __ subu32(AT, op1, op2);
1.25 + __ movz(dst, src, AT);
1.26 + break;
1.27 +
1.28 + case 0x02: //not_equal
1.29 + __ subu32(AT, op1, op2);
1.30 + __ movn(dst, src, AT);
1.31 + break;
1.32 +
1.33 + case 0x03: //above
1.34 + __ sltu(AT, op2, op1);
1.35 + __ movn(dst, src, AT);
1.36 + break;
1.37 +
1.38 + case 0x04: //above_equal
1.39 + __ sltu(AT, op1, op2);
1.40 + __ movz(dst, src, AT);
1.41 + break;
1.42 +
1.43 + case 0x05: //below
1.44 + __ sltu(AT, op1, op2);
1.45 + __ movn(dst, src, AT);
1.46 + break;
1.47 +
1.48 + case 0x06: //below_equal
1.49 + __ sltu(AT, op2, op1);
1.50 + __ movz(dst, src, AT);
1.51 + break;
1.52 +
1.53 + default:
1.54 + Unimplemented();
1.55 + }
1.56 + %}
1.57 +
1.58 + ins_pipe( pipe_slow );
1.59 +%}
1.60 +
1.61 +instruct cmovP_cmpF_reg_reg(mRegP dst, mRegP src, regF tmp1, regF tmp2, cmpOp cop ) %{
1.62 + match(Set dst (CMoveP (Binary cop (CmpF tmp1 tmp2)) (Binary dst src)));
1.63 + ins_cost(80);
1.64 + format %{
1.65 + "CMP$cop $tmp1, $tmp2\t @cmovP_cmpF_reg_reg\n"
1.66 + "\tCMOV $dst,$src \t @cmovP_cmpF_reg_reg"
1.67 + %}
1.68 +
1.69 + ins_encode %{
1.70 + FloatRegister reg_op1 = $tmp1$$FloatRegister;
1.71 + FloatRegister reg_op2 = $tmp2$$FloatRegister;
1.72 + Register dst = $dst$$Register;
1.73 + Register src = $src$$Register;
1.74 + int flag = $cop$$cmpcode;
1.75 +
1.76 + switch(flag)
1.77 + {
1.78 + case 0x01: //equal
1.79 + __ c_eq_s(reg_op1, reg_op2);
1.80 + __ movt(dst, src);
1.81 + break;
1.82 + case 0x02: //not_equal
1.83 + __ c_eq_s(reg_op1, reg_op2);
1.84 + __ movf(dst, src);
1.85 + break;
1.86 + case 0x03: //greater
1.87 + __ c_ole_s(reg_op1, reg_op2);
1.88 + __ movf(dst, src);
1.89 + break;
1.90 + case 0x04: //greater_equal
1.91 + __ c_olt_s(reg_op1, reg_op2);
1.92 + __ movf(dst, src);
1.93 + break;
1.94 + case 0x05: //less
1.95 + __ c_ult_s(reg_op1, reg_op2);
1.96 + __ movt(dst, src);
1.97 + break;
1.98 + case 0x06: //less_equal
1.99 + __ c_ule_s(reg_op1, reg_op2);
1.100 + __ movt(dst, src);
1.101 + break;
1.102 + default:
1.103 + Unimplemented();
1.104 + }
1.105 + %}
1.106 + ins_pipe( pipe_slow );
1.107 +%}
1.108 +
1.109 instruct cmovP_cmpN_reg_reg(mRegP dst, mRegP src, mRegN tmp1, mRegN tmp2, cmpOpU cop ) %{
1.110 match(Set dst (CMoveP (Binary cop (CmpN tmp1 tmp2)) (Binary dst src)));
1.111 ins_cost(80);
1.112 @@ -8664,6 +8766,60 @@
1.113 ins_pipe( pipe_slow );
1.114 %}
1.115
1.116 +instruct cmovN_cmpL_reg_reg(mRegN dst, mRegN src, mRegL tmp1, mRegL tmp2, cmpOp cop) %{
1.117 + match(Set dst (CMoveN (Binary cop (CmpL tmp1 tmp2)) (Binary dst src)));
1.118 + ins_cost(80);
1.119 + format %{
1.120 + "CMP$cop $tmp1, $tmp2\t @cmovN_cmpL_reg_reg\n"
1.121 + "\tCMOV $dst,$src \t @cmovN_cmpL_reg_reg"
1.122 + %}
1.123 + ins_encode %{
1.124 + Register opr1 = as_Register($tmp1$$reg);
1.125 + Register opr2 = as_Register($tmp2$$reg);
1.126 + Register dst = $dst$$Register;
1.127 + Register src = $src$$Register;
1.128 + int flag = $cop$$cmpcode;
1.129 +
1.130 + switch(flag)
1.131 + {
1.132 + case 0x01: //equal
1.133 + __ subu(AT, opr1, opr2);
1.134 + __ movz(dst, src, AT);
1.135 + break;
1.136 +
1.137 + case 0x02: //not_equal
1.138 + __ subu(AT, opr1, opr2);
1.139 + __ movn(dst, src, AT);
1.140 + break;
1.141 +
1.142 + case 0x03: //greater
1.143 + __ slt(AT, opr2, opr1);
1.144 + __ movn(dst, src, AT);
1.145 + break;
1.146 +
1.147 + case 0x04: //greater_equal
1.148 + __ slt(AT, opr1, opr2);
1.149 + __ movz(dst, src, AT);
1.150 + break;
1.151 +
1.152 + case 0x05: //less
1.153 + __ slt(AT, opr1, opr2);
1.154 + __ movn(dst, src, AT);
1.155 + break;
1.156 +
1.157 + case 0x06: //less_equal
1.158 + __ slt(AT, opr2, opr1);
1.159 + __ movz(dst, src, AT);
1.160 + break;
1.161 +
1.162 + default:
1.163 + Unimplemented();
1.164 + }
1.165 + %}
1.166 +
1.167 + ins_pipe( pipe_slow );
1.168 +%}
1.169 +
1.170 instruct cmovN_cmpI_reg_reg(mRegN dst, mRegN src, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{
1.171 match(Set dst (CMoveN (Binary cop (CmpI tmp1 tmp2)) (Binary dst src)));
1.172 ins_cost(80);
1.173 @@ -8718,6 +8874,107 @@
1.174 ins_pipe( pipe_slow );
1.175 %}
1.176
1.177 +instruct cmovL_cmpU_reg_reg(mRegL dst, mRegL src, mRegI tmp1, mRegI tmp2, cmpOpU cop ) %{
1.178 + match(Set dst (CMoveL (Binary cop (CmpU tmp1 tmp2)) (Binary dst src)));
1.179 + ins_cost(80);
1.180 + format %{
1.181 + "CMPU$cop $tmp1,$tmp2\t @cmovL_cmpU_reg_reg\n\t"
1.182 + "CMOV $dst,$src\t @cmovL_cmpU_reg_reg"
1.183 + %}
1.184 + ins_encode %{
1.185 + Register op1 = $tmp1$$Register;
1.186 + Register op2 = $tmp2$$Register;
1.187 + Register dst = $dst$$Register;
1.188 + Register src = $src$$Register;
1.189 + int flag = $cop$$cmpcode;
1.190 +
1.191 + switch(flag)
1.192 + {
1.193 + case 0x01: //equal
1.194 + __ subu32(AT, op1, op2);
1.195 + __ movz(dst, src, AT);
1.196 + break;
1.197 +
1.198 + case 0x02: //not_equal
1.199 + __ subu32(AT, op1, op2);
1.200 + __ movn(dst, src, AT);
1.201 + break;
1.202 +
1.203 + case 0x03: //above
1.204 + __ sltu(AT, op2, op1);
1.205 + __ movn(dst, src, AT);
1.206 + break;
1.207 +
1.208 + case 0x04: //above_equal
1.209 + __ sltu(AT, op1, op2);
1.210 + __ movz(dst, src, AT);
1.211 + break;
1.212 +
1.213 + case 0x05: //below
1.214 + __ sltu(AT, op1, op2);
1.215 + __ movn(dst, src, AT);
1.216 + break;
1.217 +
1.218 + case 0x06: //below_equal
1.219 + __ sltu(AT, op2, op1);
1.220 + __ movz(dst, src, AT);
1.221 + break;
1.222 +
1.223 + default:
1.224 + Unimplemented();
1.225 + }
1.226 + %}
1.227 +
1.228 + ins_pipe( pipe_slow );
1.229 +%}
1.230 +
1.231 +instruct cmovL_cmpF_reg_reg(mRegL dst, mRegL src, regF tmp1, regF tmp2, cmpOp cop ) %{
1.232 + match(Set dst (CMoveL (Binary cop (CmpF tmp1 tmp2)) (Binary dst src)));
1.233 + ins_cost(80);
1.234 + format %{
1.235 + "CMP$cop $tmp1, $tmp2\t @cmovL_cmpF_reg_reg\n"
1.236 + "\tCMOV $dst,$src \t @cmovL_cmpF_reg_reg"
1.237 + %}
1.238 +
1.239 + ins_encode %{
1.240 + FloatRegister reg_op1 = $tmp1$$FloatRegister;
1.241 + FloatRegister reg_op2 = $tmp2$$FloatRegister;
1.242 + Register dst = $dst$$Register;
1.243 + Register src = $src$$Register;
1.244 + int flag = $cop$$cmpcode;
1.245 +
1.246 + switch(flag)
1.247 + {
1.248 + case 0x01: //equal
1.249 + __ c_eq_s(reg_op1, reg_op2);
1.250 + __ movt(dst, src);
1.251 + break;
1.252 + case 0x02: //not_equal
1.253 + __ c_eq_s(reg_op1, reg_op2);
1.254 + __ movf(dst, src);
1.255 + break;
1.256 + case 0x03: //greater
1.257 + __ c_ole_s(reg_op1, reg_op2);
1.258 + __ movf(dst, src);
1.259 + break;
1.260 + case 0x04: //greater_equal
1.261 + __ c_olt_s(reg_op1, reg_op2);
1.262 + __ movf(dst, src);
1.263 + break;
1.264 + case 0x05: //less
1.265 + __ c_ult_s(reg_op1, reg_op2);
1.266 + __ movt(dst, src);
1.267 + break;
1.268 + case 0x06: //less_equal
1.269 + __ c_ule_s(reg_op1, reg_op2);
1.270 + __ movt(dst, src);
1.271 + break;
1.272 + default:
1.273 + Unimplemented();
1.274 + }
1.275 + %}
1.276 + ins_pipe( pipe_slow );
1.277 +%}
1.278
1.279 instruct cmovL_cmpI_reg_reg(mRegL dst, mRegL src, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{
1.280 match(Set dst (CMoveL (Binary cop (CmpI tmp1 tmp2)) (Binary dst src)));
