1.1 --- a/src/cpu/mips/vm/mips_64.ad Fri Sep 01 10:28:22 2017 +0800
1.2 +++ b/src/cpu/mips/vm/mips_64.ad Thu Sep 07 09:12:16 2017 +0800
1.3 @@ -32,84 +32,84 @@
1.4
1.5 // format:
1.6 // reg_def name (call convention, c-call convention, ideal type, encoding);
1.7 -// call convention :
1.8 -// NS = No-Save
1.9 -// SOC = Save-On-Call
1.10 -// SOE = Save-On-Entry
1.11 -// AS = Always-Save
1.12 -// ideal type :
1.13 -// see opto/opcodes.hpp for more info
1.14 +// call convention :
1.15 +// NS = No-Save
1.16 +// SOC = Save-On-Call
1.17 +// SOE = Save-On-Entry
1.18 +// AS = Always-Save
1.19 +// ideal type :
1.20 +// see opto/opcodes.hpp for more info
1.21 // reg_class name (reg, ...);
1.22 -// alloc_class name (reg, ...);
1.23 +// alloc_class name (reg, ...);
1.24 register %{
1.25
1.26 // General Registers
1.27 // Integer Registers
1.28 - reg_def R0 ( NS, NS, Op_RegI, 0, VMRegImpl::Bad());
1.29 - reg_def AT ( NS, NS, Op_RegI, 1, AT->as_VMReg());
1.30 - reg_def AT_H ( NS, NS, Op_RegI, 1, AT->as_VMReg()->next());
1.31 - reg_def V0 (SOC, SOC, Op_RegI, 2, V0->as_VMReg());
1.32 - reg_def V0_H (SOC, SOC, Op_RegI, 2, V0->as_VMReg()->next());
1.33 - reg_def V1 (SOC, SOC, Op_RegI, 3, V1->as_VMReg());
1.34 - reg_def V1_H (SOC, SOC, Op_RegI, 3, V1->as_VMReg()->next());
1.35 - reg_def A0 (SOC, SOC, Op_RegI, 4, A0->as_VMReg());
1.36 - reg_def A0_H (SOC, SOC, Op_RegI, 4, A0->as_VMReg()->next());
1.37 - reg_def A1 (SOC, SOC, Op_RegI, 5, A1->as_VMReg());
1.38 - reg_def A1_H (SOC, SOC, Op_RegI, 5, A1->as_VMReg()->next());
1.39 - reg_def A2 (SOC, SOC, Op_RegI, 6, A2->as_VMReg());
1.40 - reg_def A2_H (SOC, SOC, Op_RegI, 6, A2->as_VMReg()->next());
1.41 - reg_def A3 (SOC, SOC, Op_RegI, 7, A3->as_VMReg());
1.42 - reg_def A3_H (SOC, SOC, Op_RegI, 7, A3->as_VMReg()->next());
1.43 - reg_def A4 (SOC, SOC, Op_RegI, 8, A4->as_VMReg());
1.44 - reg_def A4_H (SOC, SOC, Op_RegI, 8, A4->as_VMReg()->next());
1.45 - reg_def A5 (SOC, SOC, Op_RegI, 9, A5->as_VMReg());
1.46 - reg_def A5_H (SOC, SOC, Op_RegI, 9, A5->as_VMReg()->next());
1.47 - reg_def A6 (SOC, SOC, Op_RegI, 10, A6->as_VMReg());
1.48 - reg_def A6_H (SOC, SOC, Op_RegI, 10, A6->as_VMReg()->next());
1.49 - reg_def A7 (SOC, SOC, Op_RegI, 11, A7->as_VMReg());
1.50 - reg_def A7_H (SOC, SOC, Op_RegI, 11, A7->as_VMReg()->next());
1.51 - reg_def T0 (SOC, SOC, Op_RegI, 12, T0->as_VMReg());
1.52 - reg_def T0_H (SOC, SOC, Op_RegI, 12, T0->as_VMReg()->next());
1.53 - reg_def T1 (SOC, SOC, Op_RegI, 13, T1->as_VMReg());
1.54 - reg_def T1_H (SOC, SOC, Op_RegI, 13, T1->as_VMReg()->next());
1.55 - reg_def T2 (SOC, SOC, Op_RegI, 14, T2->as_VMReg());
1.56 - reg_def T2_H (SOC, SOC, Op_RegI, 14, T2->as_VMReg()->next());
1.57 - reg_def T3 (SOC, SOC, Op_RegI, 15, T3->as_VMReg());
1.58 - reg_def T3_H (SOC, SOC, Op_RegI, 15, T3->as_VMReg()->next());
1.59 - reg_def S0 (SOC, SOE, Op_RegI, 16, S0->as_VMReg());
1.60 - reg_def S0_H (SOC, SOE, Op_RegI, 16, S0->as_VMReg()->next());
1.61 - reg_def S1 (SOC, SOE, Op_RegI, 17, S1->as_VMReg());
1.62 - reg_def S1_H (SOC, SOE, Op_RegI, 17, S1->as_VMReg()->next());
1.63 - reg_def S2 (SOC, SOE, Op_RegI, 18, S2->as_VMReg());
1.64 - reg_def S2_H (SOC, SOE, Op_RegI, 18, S2->as_VMReg()->next());
1.65 - reg_def S3 (SOC, SOE, Op_RegI, 19, S3->as_VMReg());
1.66 - reg_def S3_H (SOC, SOE, Op_RegI, 19, S3->as_VMReg()->next());
1.67 - reg_def S4 (SOC, SOE, Op_RegI, 20, S4->as_VMReg());
1.68 - reg_def S4_H (SOC, SOE, Op_RegI, 20, S4->as_VMReg()->next());
1.69 - reg_def S5 (SOC, SOE, Op_RegI, 21, S5->as_VMReg());
1.70 - reg_def S5_H (SOC, SOE, Op_RegI, 21, S5->as_VMReg()->next());
1.71 - reg_def S6 (SOC, SOE, Op_RegI, 22, S6->as_VMReg());
1.72 - reg_def S6_H (SOC, SOE, Op_RegI, 22, S6->as_VMReg()->next());
1.73 - reg_def S7 (SOC, SOE, Op_RegI, 23, S7->as_VMReg());
1.74 - reg_def S7_H (SOC, SOE, Op_RegI, 23, S7->as_VMReg()->next());
1.75 - reg_def T8 (SOC, SOC, Op_RegI, 24, T8->as_VMReg());
1.76 - reg_def T8_H (SOC, SOC, Op_RegI, 24, T8->as_VMReg()->next());
1.77 - reg_def T9 (SOC, SOC, Op_RegI, 25, T9->as_VMReg());
1.78 - reg_def T9_H (SOC, SOC, Op_RegI, 25, T9->as_VMReg()->next());
1.79 + reg_def R0 ( NS, NS, Op_RegI, 0, VMRegImpl::Bad());
1.80 + reg_def AT ( NS, NS, Op_RegI, 1, AT->as_VMReg());
1.81 + reg_def AT_H ( NS, NS, Op_RegI, 1, AT->as_VMReg()->next());
1.82 + reg_def V0 (SOC, SOC, Op_RegI, 2, V0->as_VMReg());
1.83 + reg_def V0_H (SOC, SOC, Op_RegI, 2, V0->as_VMReg()->next());
1.84 + reg_def V1 (SOC, SOC, Op_RegI, 3, V1->as_VMReg());
1.85 + reg_def V1_H (SOC, SOC, Op_RegI, 3, V1->as_VMReg()->next());
1.86 + reg_def A0 (SOC, SOC, Op_RegI, 4, A0->as_VMReg());
1.87 + reg_def A0_H (SOC, SOC, Op_RegI, 4, A0->as_VMReg()->next());
1.88 + reg_def A1 (SOC, SOC, Op_RegI, 5, A1->as_VMReg());
1.89 + reg_def A1_H (SOC, SOC, Op_RegI, 5, A1->as_VMReg()->next());
1.90 + reg_def A2 (SOC, SOC, Op_RegI, 6, A2->as_VMReg());
1.91 + reg_def A2_H (SOC, SOC, Op_RegI, 6, A2->as_VMReg()->next());
1.92 + reg_def A3 (SOC, SOC, Op_RegI, 7, A3->as_VMReg());
1.93 + reg_def A3_H (SOC, SOC, Op_RegI, 7, A3->as_VMReg()->next());
1.94 + reg_def A4 (SOC, SOC, Op_RegI, 8, A4->as_VMReg());
1.95 + reg_def A4_H (SOC, SOC, Op_RegI, 8, A4->as_VMReg()->next());
1.96 + reg_def A5 (SOC, SOC, Op_RegI, 9, A5->as_VMReg());
1.97 + reg_def A5_H (SOC, SOC, Op_RegI, 9, A5->as_VMReg()->next());
1.98 + reg_def A6 (SOC, SOC, Op_RegI, 10, A6->as_VMReg());
1.99 + reg_def A6_H (SOC, SOC, Op_RegI, 10, A6->as_VMReg()->next());
1.100 + reg_def A7 (SOC, SOC, Op_RegI, 11, A7->as_VMReg());
1.101 + reg_def A7_H (SOC, SOC, Op_RegI, 11, A7->as_VMReg()->next());
1.102 + reg_def T0 (SOC, SOC, Op_RegI, 12, T0->as_VMReg());
1.103 + reg_def T0_H (SOC, SOC, Op_RegI, 12, T0->as_VMReg()->next());
1.104 + reg_def T1 (SOC, SOC, Op_RegI, 13, T1->as_VMReg());
1.105 + reg_def T1_H (SOC, SOC, Op_RegI, 13, T1->as_VMReg()->next());
1.106 + reg_def T2 (SOC, SOC, Op_RegI, 14, T2->as_VMReg());
1.107 + reg_def T2_H (SOC, SOC, Op_RegI, 14, T2->as_VMReg()->next());
1.108 + reg_def T3 (SOC, SOC, Op_RegI, 15, T3->as_VMReg());
1.109 + reg_def T3_H (SOC, SOC, Op_RegI, 15, T3->as_VMReg()->next());
1.110 + reg_def S0 (SOC, SOE, Op_RegI, 16, S0->as_VMReg());
1.111 + reg_def S0_H (SOC, SOE, Op_RegI, 16, S0->as_VMReg()->next());
1.112 + reg_def S1 (SOC, SOE, Op_RegI, 17, S1->as_VMReg());
1.113 + reg_def S1_H (SOC, SOE, Op_RegI, 17, S1->as_VMReg()->next());
1.114 + reg_def S2 (SOC, SOE, Op_RegI, 18, S2->as_VMReg());
1.115 + reg_def S2_H (SOC, SOE, Op_RegI, 18, S2->as_VMReg()->next());
1.116 + reg_def S3 (SOC, SOE, Op_RegI, 19, S3->as_VMReg());
1.117 + reg_def S3_H (SOC, SOE, Op_RegI, 19, S3->as_VMReg()->next());
1.118 + reg_def S4 (SOC, SOE, Op_RegI, 20, S4->as_VMReg());
1.119 + reg_def S4_H (SOC, SOE, Op_RegI, 20, S4->as_VMReg()->next());
1.120 + reg_def S5 (SOC, SOE, Op_RegI, 21, S5->as_VMReg());
1.121 + reg_def S5_H (SOC, SOE, Op_RegI, 21, S5->as_VMReg()->next());
1.122 + reg_def S6 (SOC, SOE, Op_RegI, 22, S6->as_VMReg());
1.123 + reg_def S6_H (SOC, SOE, Op_RegI, 22, S6->as_VMReg()->next());
1.124 + reg_def S7 (SOC, SOE, Op_RegI, 23, S7->as_VMReg());
1.125 + reg_def S7_H (SOC, SOE, Op_RegI, 23, S7->as_VMReg()->next());
1.126 + reg_def T8 (SOC, SOC, Op_RegI, 24, T8->as_VMReg());
1.127 + reg_def T8_H (SOC, SOC, Op_RegI, 24, T8->as_VMReg()->next());
1.128 + reg_def T9 (SOC, SOC, Op_RegI, 25, T9->as_VMReg());
1.129 + reg_def T9_H (SOC, SOC, Op_RegI, 25, T9->as_VMReg()->next());
1.130
1.131 // Special Registers
1.132 - reg_def K0 ( NS, NS, Op_RegI, 26, K0->as_VMReg());
1.133 - reg_def K1 ( NS, NS, Op_RegI, 27, K1->as_VMReg());
1.134 - reg_def GP ( NS, NS, Op_RegI, 28, GP->as_VMReg());
1.135 - reg_def GP_H ( NS, NS, Op_RegI, 28, GP->as_VMReg()->next());
1.136 - reg_def SP ( NS, NS, Op_RegI, 29, SP->as_VMReg());
1.137 - reg_def SP_H ( NS, NS, Op_RegI, 29, SP->as_VMReg()->next());
1.138 - reg_def FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
1.139 - reg_def FP_H ( NS, NS, Op_RegI, 30, FP->as_VMReg()->next());
1.140 - reg_def RA ( NS, NS, Op_RegI, 31, RA->as_VMReg());
1.141 - reg_def RA_H ( NS, NS, Op_RegI, 31, RA->as_VMReg()->next());
1.142 -
1.143 -// Floating registers.
1.144 + reg_def K0 ( NS, NS, Op_RegI, 26, K0->as_VMReg());
1.145 + reg_def K1 ( NS, NS, Op_RegI, 27, K1->as_VMReg());
1.146 + reg_def GP ( NS, NS, Op_RegI, 28, GP->as_VMReg());
1.147 + reg_def GP_H ( NS, NS, Op_RegI, 28, GP->as_VMReg()->next());
1.148 + reg_def SP ( NS, NS, Op_RegI, 29, SP->as_VMReg());
1.149 + reg_def SP_H ( NS, NS, Op_RegI, 29, SP->as_VMReg()->next());
1.150 + reg_def FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
1.151 + reg_def FP_H ( NS, NS, Op_RegI, 30, FP->as_VMReg()->next());
1.152 + reg_def RA ( NS, NS, Op_RegI, 31, RA->as_VMReg());
1.153 + reg_def RA_H ( NS, NS, Op_RegI, 31, RA->as_VMReg()->next());
1.154 +
1.155 +// Floating registers.
1.156 reg_def F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
1.157 reg_def F0_H ( SOC, SOC, Op_RegF, 0, F0->as_VMReg()->next());
1.158 reg_def F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
1.159 @@ -182,7 +182,7 @@
1.160 reg_def MIPS_FLAG (SOC, SOC, Op_RegFlags, 1, as_Register(1)->as_VMReg());
1.161 //S6 is used for get_thread(S6)
1.162 //S5 is uesd for heapbase of compressed oop
1.163 -alloc_class chunk0(
1.164 +alloc_class chunk0(
1.165 S7, S7_H,
1.166 S0, S0_H,
1.167 S1, S1_H,
1.168 @@ -207,7 +207,7 @@
1.169 A1, A1_H,
1.170 A0, A0_H,
1.171 T0, T0_H,
1.172 - GP, GP_H
1.173 + GP, GP_H
1.174 RA, RA_H,
1.175 SP, SP_H, // stack_pointer
1.176 FP, FP_H // frame_pointer
1.177 @@ -313,7 +313,7 @@
1.178
1.179 reg_class no_Ax_int_reg( S7, S0, S1, S2, S4, S3, T8, T2, T3, T1, V1, V0, T0 );
1.180
1.181 -reg_class p_reg(
1.182 +reg_class p_reg(
1.183 S7, S7_H,
1.184 S0, S0_H,
1.185 S1, S1_H,
1.186 @@ -335,7 +335,7 @@
1.187 T0, T0_H
1.188 );
1.189
1.190 -reg_class no_T8_p_reg(
1.191 +reg_class no_T8_p_reg(
1.192 S7, S7_H,
1.193 S0, S0_H,
1.194 S1, S1_H,
1.195 @@ -356,7 +356,7 @@
1.196 T0, T0_H
1.197 );
1.198
1.199 -reg_class long_reg(
1.200 +reg_class long_reg(
1.201 S7, S7_H,
1.202 S0, S0_H,
1.203 S1, S1_H,
1.204 @@ -393,33 +393,33 @@
1.205 F7, F7_H,
1.206 F8, F8_H,
1.207 F9, F9_H,
1.208 - F10, F10_H,
1.209 - F11, F11_H,
1.210 - F12, F12_H,
1.211 - F13, F13_H,
1.212 - F14, F14_H,
1.213 - F15, F15_H,
1.214 - F16, F16_H,
1.215 - F17, F17_H,
1.216 - F18, F18_H,
1.217 - F19, F19_H,
1.218 - F20, F20_H,
1.219 - F21, F21_H,
1.220 - F22, F22_H,
1.221 - F23, F23_H,
1.222 - F24, F24_H,
1.223 - F25, F25_H,
1.224 - F26, F26_H,
1.225 - F27, F27_H,
1.226 - F28, F28_H,
1.227 - F29, F29_H,
1.228 + F10, F10_H,
1.229 + F11, F11_H,
1.230 + F12, F12_H,
1.231 + F13, F13_H,
1.232 + F14, F14_H,
1.233 + F15, F15_H,
1.234 + F16, F16_H,
1.235 + F17, F17_H,
1.236 + F18, F18_H,
1.237 + F19, F19_H,
1.238 + F20, F20_H,
1.239 + F21, F21_H,
1.240 + F22, F22_H,
1.241 + F23, F23_H,
1.242 + F24, F24_H,
1.243 + F25, F25_H,
1.244 + F26, F26_H,
1.245 + F27, F27_H,
1.246 + F28, F28_H,
1.247 + F29, F29_H,
1.248 F31, F31_H);
1.249
1.250 reg_class flt_arg0( F12 );
1.251 reg_class dbl_arg0( F12, F12_H );
1.252 reg_class dbl_arg1( F14, F14_H );
1.253
1.254 -%}
1.255 +%}
1.256
1.257 //----------DEFINITION BLOCK---------------------------------------------------
1.258 // Define name --> value mappings to inform the ADLC of an integer valued name
1.259 @@ -433,17 +433,17 @@
1.260 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
1.261 //
1.262 definitions %{
1.263 - int_def DEFAULT_COST ( 100, 100);
1.264 - int_def HUGE_COST (1000000, 1000000);
1.265 -
1.266 - // Memory refs are twice as expensive as run-of-the-mill.
1.267 - int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
1.268 -
1.269 - // Branches are even more expensive.
1.270 - int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
1.271 - // we use jr instruction to construct call, so more expensive
1.272 - // by yjl 2/28/2006
1.273 - int_def CALL_COST ( 500, DEFAULT_COST * 5);
1.274 + int_def DEFAULT_COST ( 100, 100);
1.275 + int_def HUGE_COST (1000000, 1000000);
1.276 +
1.277 + // Memory refs are twice as expensive as run-of-the-mill.
1.278 + int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
1.279 +
1.280 + // Branches are even more expensive.
1.281 + int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
1.282 + // we use jr instruction to construct call, so more expensive
1.283 + // by yjl 2/28/2006
1.284 + int_def CALL_COST ( 500, DEFAULT_COST * 5);
1.285 /*
1.286 int_def EQUAL ( 1, 1 );
1.287 int_def NOT_EQUAL ( 2, 2 );
1.288 @@ -453,7 +453,7 @@
1.289 int_def LESS_EQUAL ( 6, 6 );
1.290 */
1.291 %}
1.292 -
1.293 +
1.294
1.295
1.296 //----------SOURCE BLOCK-------------------------------------------------------
1.297 @@ -469,7 +469,7 @@
1.298 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
1.299
1.300 class CallStubImpl {
1.301 -
1.302 +
1.303 //--------------------------------------------------------------
1.304 //---< Used for optimization in Compile::shorten_branches >---
1.305 //--------------------------------------------------------------
1.306 @@ -479,9 +479,9 @@
1.307 static uint size_call_trampoline() {
1.308 return 0; // no call trampolines on this platform
1.309 }
1.310 -
1.311 +
1.312 // number of relocations needed by a call trampoline stub
1.313 - static uint reloc_call_trampoline() {
1.314 + static uint reloc_call_trampoline() {
1.315 return 0; // no call trampolines on this platform
1.316 }
1.317 };
1.318 @@ -499,7 +499,6 @@
1.319 // a call be deoptimization. (4932387)
1.320 // Note that this value is also credited (in output.cpp) to
1.321 // the size of the code section.
1.322 -// return NativeJump::instruction_size;
1.323 int size = NativeCall::instruction_size;
1.324 return round_to(size, 16);
1.325 }
1.326 @@ -529,7 +528,7 @@
1.327 #define RELOC_IMM64 Assembler::imm_operand
1.328 #define RELOC_DISP32 Assembler::disp32_operand
1.329
1.330 -
1.331 +
1.332 #define __ _masm.
1.333
1.334
1.335 @@ -647,7 +646,8 @@
1.336 }
1.337
1.338 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1.339 - if( Assembler::is_simm16(offset) ) return true;
1.340 + if( Assembler::is_simm16(offset) )
1.341 + return true;
1.342 else {
1.343 assert(false, "Not implemented yet !" );
1.344 Unimplemented();
1.345 @@ -766,23 +766,23 @@
1.346 bool Matcher::can_be_java_arg( int reg ) {
1.347 /* Refer to: [sharedRuntime_mips_64.cpp] SharedRuntime::java_calling_convention() */
1.348 if ( reg == T0_num || reg == T0_H_num
1.349 - || reg == A0_num || reg == A0_H_num
1.350 - || reg == A1_num || reg == A1_H_num
1.351 - || reg == A2_num || reg == A2_H_num
1.352 - || reg == A3_num || reg == A3_H_num
1.353 - || reg == A4_num || reg == A4_H_num
1.354 - || reg == A5_num || reg == A5_H_num
1.355 - || reg == A6_num || reg == A6_H_num
1.356 + || reg == A0_num || reg == A0_H_num
1.357 + || reg == A1_num || reg == A1_H_num
1.358 + || reg == A2_num || reg == A2_H_num
1.359 + || reg == A3_num || reg == A3_H_num
1.360 + || reg == A4_num || reg == A4_H_num
1.361 + || reg == A5_num || reg == A5_H_num
1.362 + || reg == A6_num || reg == A6_H_num
1.363 || reg == A7_num || reg == A7_H_num )
1.364 return true;
1.365
1.366 if ( reg == F12_num || reg == F12_H_num
1.367 - || reg == F13_num || reg == F13_H_num
1.368 - || reg == F14_num || reg == F14_H_num
1.369 - || reg == F15_num || reg == F15_H_num
1.370 - || reg == F16_num || reg == F16_H_num
1.371 - || reg == F17_num || reg == F17_H_num
1.372 - || reg == F18_num || reg == F18_H_num
1.373 + || reg == F13_num || reg == F13_H_num
1.374 + || reg == F14_num || reg == F14_H_num
1.375 + || reg == F15_num || reg == F15_H_num
1.376 + || reg == F16_num || reg == F16_H_num
1.377 + || reg == F17_num || reg == F17_H_num
1.378 + || reg == F18_num || reg == F18_H_num
1.379 || reg == F19_num || reg == F19_H_num )
1.380 return true;
1.381
1.382 @@ -888,7 +888,7 @@
1.383 //nop
1.384 //jalr
1.385 //nop
1.386 - return 24;
1.387 + return 24;
1.388 }
1.389
1.390 int MachCallDynamicJavaNode::ret_addr_offset() {
1.391 @@ -903,7 +903,7 @@
1.392 //nop
1.393 //jalr T9
1.394 //nop
1.395 - return 4 * 4 + 4 * 6;
1.396 + return 4 * 4 + 4 * 6;
1.397 }
1.398
1.399 //=============================================================================
1.400 @@ -955,15 +955,15 @@
1.401 __ sd(AT, Address(SP, dst_offset));
1.402 #ifndef PRODUCT
1.403 } else {
1.404 - if(!do_size){
1.405 - if (size != 0) st->print("\n\t");
1.406 - st->print("ld AT, [SP + #%d]\t# 64-bit mem-mem spill 1\n\t"
1.407 - "sd AT, [SP + #%d]",
1.408 - src_offset, dst_offset);
1.409 - }
1.410 + if(!do_size){
1.411 + if (size != 0) st->print("\n\t");
1.412 + st->print("ld AT, [SP + #%d]\t# 64-bit mem-mem spill 1\n\t"
1.413 + "sd AT, [SP + #%d]",
1.414 + src_offset, dst_offset);
1.415 + }
1.416 #endif
1.417 }
1.418 - size += 8;
1.419 + size += 8;
1.420 } else {
1.421 // 32-bit
1.422 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1.423 @@ -977,15 +977,15 @@
1.424 __ sw(AT, Address(SP, dst_offset));
1.425 #ifndef PRODUCT
1.426 } else {
1.427 - if(!do_size){
1.428 - if (size != 0) st->print("\n\t");
1.429 - st->print("lw AT, [SP + #%d] spill 2\n\t"
1.430 - "sw AT, [SP + #%d]\n\t",
1.431 - src_offset, dst_offset);
1.432 - }
1.433 + if(!do_size){
1.434 + if (size != 0) st->print("\n\t");
1.435 + st->print("lw AT, [SP + #%d] spill 2\n\t"
1.436 + "sw AT, [SP + #%d]\n\t",
1.437 + src_offset, dst_offset);
1.438 + }
1.439 #endif
1.440 }
1.441 - size += 8;
1.442 + size += 8;
1.443 }
1.444 return size;
1.445 } else if (dst_first_rc == rc_int) {
1.446 @@ -999,15 +999,15 @@
1.447 __ ld(as_Register(Matcher::_regEncode[dst_first]), Address(SP, offset));
1.448 #ifndef PRODUCT
1.449 } else {
1.450 - if(!do_size){
1.451 - if (size != 0) st->print("\n\t");
1.452 - st->print("ld %s, [SP + #%d]\t# spill 3",
1.453 - Matcher::regName[dst_first],
1.454 - offset);
1.455 - }
1.456 + if(!do_size){
1.457 + if (size != 0) st->print("\n\t");
1.458 + st->print("ld %s, [SP + #%d]\t# spill 3",
1.459 + Matcher::regName[dst_first],
1.460 + offset);
1.461 + }
1.462 #endif
1.463 }
1.464 - size += 4;
1.465 + size += 4;
1.466 } else {
1.467 // 32-bit
1.468 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1.469 @@ -1020,21 +1020,21 @@
1.470 else
1.471 __ lwu(as_Register(Matcher::_regEncode[dst_first]), Address(SP, offset));
1.472 #ifndef PRODUCT
1.473 - } else {
1.474 - if(!do_size){
1.475 - if (size != 0) st->print("\n\t");
1.476 - if (this->ideal_reg() == Op_RegI)
1.477 - st->print("lw %s, [SP + #%d]\t# spill 4",
1.478 - Matcher::regName[dst_first],
1.479 - offset);
1.480 - else
1.481 - st->print("lwu %s, [SP + #%d]\t# spill 5",
1.482 - Matcher::regName[dst_first],
1.483 - offset);
1.484 - }
1.485 + } else {
1.486 + if(!do_size){
1.487 + if (size != 0) st->print("\n\t");
1.488 + if (this->ideal_reg() == Op_RegI)
1.489 + st->print("lw %s, [SP + #%d]\t# spill 4",
1.490 + Matcher::regName[dst_first],
1.491 + offset);
1.492 + else
1.493 + st->print("lwu %s, [SP + #%d]\t# spill 5",
1.494 + Matcher::regName[dst_first],
1.495 + offset);
1.496 + }
1.497 #endif
1.498 - }
1.499 - size += 4;
1.500 + }
1.501 + size += 4;
1.502 }
1.503 return size;
1.504 } else if (dst_first_rc == rc_float) {
1.505 @@ -1048,15 +1048,15 @@
1.506 __ ldc1( as_FloatRegister(Matcher::_regEncode[dst_first]), Address(SP, offset));
1.507 #ifndef PRODUCT
1.508 } else {
1.509 - if(!do_size){
1.510 - if (size != 0) st->print("\n\t");
1.511 - st->print("ldc1 %s, [SP + #%d]\t# spill 6",
1.512 - Matcher::regName[dst_first],
1.513 - offset);
1.514 - }
1.515 + if (!do_size) {
1.516 + if (size != 0) st->print("\n\t");
1.517 + st->print("ldc1 %s, [SP + #%d]\t# spill 6",
1.518 + Matcher::regName[dst_first],
1.519 + offset);
1.520 + }
1.521 #endif
1.522 }
1.523 - size += 4;
1.524 + size += 4;
1.525 } else {
1.526 // 32-bit
1.527 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1.528 @@ -1067,15 +1067,15 @@
1.529 __ lwc1( as_FloatRegister(Matcher::_regEncode[dst_first]), Address(SP, offset));
1.530 #ifndef PRODUCT
1.531 } else {
1.532 - if(!do_size){
1.533 - if (size != 0) st->print("\n\t");
1.534 - st->print("lwc1 %s, [SP + #%d]\t# spill 7",
1.535 - Matcher::regName[dst_first],
1.536 - offset);
1.537 - }
1.538 + if(!do_size){
1.539 + if (size != 0) st->print("\n\t");
1.540 + st->print("lwc1 %s, [SP + #%d]\t# spill 7",
1.541 + Matcher::regName[dst_first],
1.542 + offset);
1.543 + }
1.544 #endif
1.545 }
1.546 - size += 4;
1.547 + size += 4;
1.548 }
1.549 return size;
1.550 }
1.551 @@ -1092,15 +1092,15 @@
1.552 __ sd(as_Register(Matcher::_regEncode[src_first]), Address(SP, offset));
1.553 #ifndef PRODUCT
1.554 } else {
1.555 - if(!do_size){
1.556 - if (size != 0) st->print("\n\t");
1.557 - st->print("sd %s, [SP + #%d] # spill 8",
1.558 - Matcher::regName[src_first],
1.559 - offset);
1.560 - }
1.561 + if(!do_size){
1.562 + if (size != 0) st->print("\n\t");
1.563 + st->print("sd %s, [SP + #%d] # spill 8",
1.564 + Matcher::regName[src_first],
1.565 + offset);
1.566 + }
1.567 #endif
1.568 }
1.569 - size += 4;
1.570 + size += 4;
1.571 } else {
1.572 // 32-bit
1.573 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1.574 @@ -1111,14 +1111,14 @@
1.575 __ sw(as_Register(Matcher::_regEncode[src_first]), Address(SP, offset));
1.576 #ifndef PRODUCT
1.577 } else {
1.578 - if(!do_size){
1.579 - if (size != 0) st->print("\n\t");
1.580 - st->print("sw %s, [SP + #%d]\t# spill 9",
1.581 - Matcher::regName[src_first], offset);
1.582 - }
1.583 + if (!do_size) {
1.584 + if (size != 0) st->print("\n\t");
1.585 + st->print("sw %s, [SP + #%d]\t# spill 9",
1.586 + Matcher::regName[src_first], offset);
1.587 + }
1.588 #endif
1.589 }
1.590 - size += 4;
1.591 + size += 4;
1.592 }
1.593 return size;
1.594 } else if (dst_first_rc == rc_int) {
1.595 @@ -1132,15 +1132,15 @@
1.596 as_Register(Matcher::_regEncode[src_first]));
1.597 #ifndef PRODUCT
1.598 } else {
1.599 - if(!do_size){
1.600 - if (size != 0) st->print("\n\t");
1.601 - st->print("move(64bit) %s <-- %s\t# spill 10",
1.602 - Matcher::regName[dst_first],
1.603 - Matcher::regName[src_first]);
1.604 - }
1.605 + if(!do_size){
1.606 + if (size != 0) st->print("\n\t");
1.607 + st->print("move(64bit) %s <-- %s\t# spill 10",
1.608 + Matcher::regName[dst_first],
1.609 + Matcher::regName[src_first]);
1.610 + }
1.611 #endif
1.612 }
1.613 - size += 4;
1.614 + size += 4;
1.615 return size;
1.616 } else {
1.617 // 32-bit
1.618 @@ -1152,18 +1152,17 @@
1.619 __ move_u32(as_Register(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1.620 else
1.621 __ daddu(as_Register(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]), R0);
1.622 -
1.623 #ifndef PRODUCT
1.624 } else {
1.625 - if(!do_size){
1.626 - if (size != 0) st->print("\n\t");
1.627 - st->print("move(32-bit) %s <-- %s\t# spill 11",
1.628 - Matcher::regName[dst_first],
1.629 - Matcher::regName[src_first]);
1.630 - }
1.631 + if (!do_size) {
1.632 + if (size != 0) st->print("\n\t");
1.633 + st->print("move(32-bit) %s <-- %s\t# spill 11",
1.634 + Matcher::regName[dst_first],
1.635 + Matcher::regName[src_first]);
1.636 + }
1.637 #endif
1.638 }
1.639 - size += 4;
1.640 + size += 4;
1.641 return size;
1.642 }
1.643 } else if (dst_first_rc == rc_float) {
1.644 @@ -1176,15 +1175,15 @@
1.645 __ dmtc1(as_Register(Matcher::_regEncode[src_first]), as_FloatRegister(Matcher::_regEncode[dst_first]));
1.646 #ifndef PRODUCT
1.647 } else {
1.648 - if(!do_size){
1.649 - if (size != 0) st->print("\n\t");
1.650 - st->print("dmtc1 %s, %s\t# spill 12",
1.651 - Matcher::regName[dst_first],
1.652 - Matcher::regName[src_first]);
1.653 - }
1.654 + if(!do_size){
1.655 + if (size != 0) st->print("\n\t");
1.656 + st->print("dmtc1 %s, %s\t# spill 12",
1.657 + Matcher::regName[dst_first],
1.658 + Matcher::regName[src_first]);
1.659 + }
1.660 #endif
1.661 }
1.662 - size += 4;
1.663 + size += 4;
1.664 } else {
1.665 // 32-bit
1.666 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1.667 @@ -1194,15 +1193,15 @@
1.668 __ mtc1( as_Register(Matcher::_regEncode[src_first]), as_FloatRegister(Matcher::_regEncode[dst_first]) );
1.669 #ifndef PRODUCT
1.670 } else {
1.671 - if(!do_size){
1.672 - if (size != 0) st->print("\n\t");
1.673 - st->print("mtc1 %s, %s\t# spill 13",
1.674 - Matcher::regName[dst_first],
1.675 - Matcher::regName[src_first]);
1.676 - }
1.677 + if(!do_size){
1.678 + if (size != 0) st->print("\n\t");
1.679 + st->print("mtc1 %s, %s\t# spill 13",
1.680 + Matcher::regName[dst_first],
1.681 + Matcher::regName[src_first]);
1.682 + }
1.683 #endif
1.684 }
1.685 - size += 4;
1.686 + size += 4;
1.687 }
1.688 return size;
1.689 }
1.690 @@ -1219,15 +1218,15 @@
1.691 __ sdc1( as_FloatRegister(Matcher::_regEncode[src_first]), Address(SP, offset) );
1.692 #ifndef PRODUCT
1.693 } else {
1.694 - if(!do_size){
1.695 - if (size != 0) st->print("\n\t");
1.696 - st->print("sdc1 %s, [SP + #%d]\t# spill 14",
1.697 - Matcher::regName[src_first],
1.698 - offset);
1.699 - }
1.700 + if(!do_size){
1.701 + if (size != 0) st->print("\n\t");
1.702 + st->print("sdc1 %s, [SP + #%d]\t# spill 14",
1.703 + Matcher::regName[src_first],
1.704 + offset);
1.705 + }
1.706 #endif
1.707 }
1.708 - size += 4;
1.709 + size += 4;
1.710 } else {
1.711 // 32-bit
1.712 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1.713 @@ -1238,15 +1237,15 @@
1.714 __ swc1(as_FloatRegister(Matcher::_regEncode[src_first]), Address(SP, offset));
1.715 #ifndef PRODUCT
1.716 } else {
1.717 - if(!do_size){
1.718 - if (size != 0) st->print("\n\t");
1.719 - st->print("swc1 %s, [SP + #%d]\t# spill 15",
1.720 - Matcher::regName[src_first],
1.721 - offset);
1.722 - }
1.723 + if(!do_size){
1.724 + if (size != 0) st->print("\n\t");
1.725 + st->print("swc1 %s, [SP + #%d]\t# spill 15",
1.726 + Matcher::regName[src_first],
1.727 + offset);
1.728 + }
1.729 #endif
1.730 }
1.731 - size += 4;
1.732 + size += 4;
1.733 }
1.734 return size;
1.735 } else if (dst_first_rc == rc_int) {
1.736 @@ -1259,15 +1258,15 @@
1.737 __ dmfc1( as_Register(Matcher::_regEncode[dst_first]), as_FloatRegister(Matcher::_regEncode[src_first]));
1.738 #ifndef PRODUCT
1.739 } else {
1.740 - if(!do_size){
1.741 - if (size != 0) st->print("\n\t");
1.742 - st->print("dmfc1 %s, %s\t# spill 16",
1.743 - Matcher::regName[dst_first],
1.744 - Matcher::regName[src_first]);
1.745 - }
1.746 + if(!do_size){
1.747 + if (size != 0) st->print("\n\t");
1.748 + st->print("dmfc1 %s, %s\t# spill 16",
1.749 + Matcher::regName[dst_first],
1.750 + Matcher::regName[src_first]);
1.751 + }
1.752 #endif
1.753 }
1.754 - size += 4;
1.755 + size += 4;
1.756 } else {
1.757 // 32-bit
1.758 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1.759 @@ -1277,15 +1276,15 @@
1.760 __ mfc1( as_Register(Matcher::_regEncode[dst_first]), as_FloatRegister(Matcher::_regEncode[src_first]));
1.761 #ifndef PRODUCT
1.762 } else {
1.763 - if(!do_size){
1.764 - if (size != 0) st->print("\n\t");
1.765 - st->print("mfc1 %s, %s\t# spill 17",
1.766 - Matcher::regName[dst_first],
1.767 - Matcher::regName[src_first]);
1.768 - }
1.769 + if(!do_size){
1.770 + if (size != 0) st->print("\n\t");
1.771 + st->print("mfc1 %s, %s\t# spill 17",
1.772 + Matcher::regName[dst_first],
1.773 + Matcher::regName[src_first]);
1.774 + }
1.775 #endif
1.776 }
1.777 - size += 4;
1.778 + size += 4;
1.779 }
1.780 return size;
1.781 } else if (dst_first_rc == rc_float) {
1.782 @@ -1298,15 +1297,15 @@
1.783 __ mov_d( as_FloatRegister(Matcher::_regEncode[dst_first]), as_FloatRegister(Matcher::_regEncode[src_first]));
1.784 #ifndef PRODUCT
1.785 } else {
1.786 - if(!do_size){
1.787 - if (size != 0) st->print("\n\t");
1.788 - st->print("mov_d %s <-- %s\t# spill 18",
1.789 - Matcher::regName[dst_first],
1.790 - Matcher::regName[src_first]);
1.791 - }
1.792 + if(!do_size){
1.793 + if (size != 0) st->print("\n\t");
1.794 + st->print("mov_d %s <-- %s\t# spill 18",
1.795 + Matcher::regName[dst_first],
1.796 + Matcher::regName[src_first]);
1.797 + }
1.798 #endif
1.799 }
1.800 - size += 4;
1.801 + size += 4;
1.802 } else {
1.803 // 32-bit
1.804 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1.805 @@ -1316,15 +1315,15 @@
1.806 __ mov_s( as_FloatRegister(Matcher::_regEncode[dst_first]), as_FloatRegister(Matcher::_regEncode[src_first]));
1.807 #ifndef PRODUCT
1.808 } else {
1.809 - if(!do_size){
1.810 - if (size != 0) st->print("\n\t");
1.811 - st->print("mov_s %s <-- %s\t# spill 19",
1.812 - Matcher::regName[dst_first],
1.813 - Matcher::regName[src_first]);
1.814 - }
1.815 + if(!do_size){
1.816 + if (size != 0) st->print("\n\t");
1.817 + st->print("mov_s %s <-- %s\t# spill 19",
1.818 + Matcher::regName[dst_first],
1.819 + Matcher::regName[src_first]);
1.820 + }
1.821 #endif
1.822 }
1.823 - size += 4;
1.824 + size += 4;
1.825 }
1.826 return size;
1.827 }
1.828 @@ -1380,11 +1379,11 @@
1.829 st->print("daddiu SP, SP, %d # Rlease stack @ MachEpilogNode",framesize);
1.830 st->cr(); st->print("\t");
1.831 if (UseLoongsonISA) {
1.832 - st->print("gslq RA, FP, SP, %d # Restore FP & RA @ MachEpilogNode", -wordSize*2);
1.833 + st->print("gslq RA, FP, SP, %d # Restore FP & RA @ MachEpilogNode", -wordSize*2);
1.834 } else {
1.835 - st->print("ld RA, SP, %d # Restore RA @ MachEpilogNode", -wordSize);
1.836 - st->cr(); st->print("\t");
1.837 - st->print("ld FP, SP, %d # Restore FP @ MachEpilogNode", -wordSize*2);
1.838 + st->print("ld RA, SP, %d # Restore RA @ MachEpilogNode", -wordSize);
1.839 + st->cr(); st->print("\t");
1.840 + st->print("ld FP, SP, %d # Restore FP @ MachEpilogNode", -wordSize*2);
1.841 }
1.842
1.843 if( do_polling() && C->is_method_compilation() ) {
1.844 @@ -1451,20 +1450,6 @@
1.845 int reg = ra_->get_encode(this);
1.846
1.847 __ addi(as_Register(reg), SP, offset);
1.848 -/*
1.849 - if( offset >= 128 ) {
1.850 - emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1.851 - emit_rm(cbuf, 0x2, reg, 0x04);
1.852 - emit_rm(cbuf, 0x0, 0x04, SP_enc);
1.853 - emit_d32(cbuf, offset);
1.854 - }
1.855 - else {
1.856 - emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1.857 - emit_rm(cbuf, 0x1, reg, 0x04);
1.858 - emit_rm(cbuf, 0x0, 0x04, SP_enc);
1.859 - emit_d8(cbuf, offset);
1.860 - }
1.861 -*/
1.862 }
1.863
1.864
1.865 @@ -1479,13 +1464,9 @@
1.866 //nop
1.867 assert(NativeCall::instruction_size == 24, "in MachCallRuntimeNode::ret_addr_offset()");
1.868 return NativeCall::instruction_size;
1.869 -// return 16;
1.870 }
1.871
1.872
1.873 -
1.874 -
1.875 -
1.876 //=============================================================================
1.877 #ifndef PRODUCT
1.878 void MachNopNode::format( PhaseRegAlloc *, outputStream* st ) const {
1.879 @@ -1501,7 +1482,7 @@
1.880 }
1.881
1.882 uint MachNopNode::size(PhaseRegAlloc *) const {
1.883 - return 4 * _count;
1.884 + return 4 * _count;
1.885 }
1.886 const Pipeline* MachNopNode::pipeline() const {
1.887 return MachNode::pipeline_class();
1.888 @@ -1546,7 +1527,7 @@
1.889 }
1.890
1.891 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1.892 - return MachNode::size(ra_);
1.893 + return MachNode::size(ra_);
1.894 }
1.895
1.896
1.897 @@ -1613,14 +1594,14 @@
1.898 if (C->need_stack_bang(bangsize)) {
1.899 st->print_cr("# stack bang"); st->print("\t");
1.900 }
1.901 - if (UseLoongsonISA) {
1.902 - st->print("gssq RA, FP, %d(SP) @ MachPrologNode\n\t", -wordSize*2);
1.903 - } else {
1.904 - st->print("sd RA, %d(SP) @ MachPrologNode\n\t", -wordSize);
1.905 - st->print("sd FP, %d(SP) @ MachPrologNode\n\t", -wordSize*2);
1.906 - }
1.907 - st->print("daddiu FP, SP, -%d \n\t", wordSize*2);
1.908 - st->print("daddiu SP, SP, -%d \t",framesize);
1.909 + if (UseLoongsonISA) {
1.910 + st->print("gssq RA, FP, %d(SP) @ MachPrologNode\n\t", -wordSize*2);
1.911 + } else {
1.912 + st->print("sd RA, %d(SP) @ MachPrologNode\n\t", -wordSize);
1.913 + st->print("sd FP, %d(SP) @ MachPrologNode\n\t", -wordSize*2);
1.914 + }
1.915 + st->print("daddiu FP, SP, -%d \n\t", wordSize*2);
1.916 + st->print("daddiu SP, SP, -%d \t",framesize);
1.917 }
1.918 #endif
1.919
1.920 @@ -1639,10 +1620,10 @@
1.921 }
1.922
1.923 if (UseLoongsonISA) {
1.924 - __ gssq(RA, FP, SP, -wordSize*2);
1.925 + __ gssq(RA, FP, SP, -wordSize*2);
1.926 } else {
1.927 - __ sd(RA, SP, -wordSize);
1.928 - __ sd(FP, SP, -wordSize*2);
1.929 + __ sd(RA, SP, -wordSize);
1.930 + __ sd(FP, SP, -wordSize*2);
1.931 }
1.932 __ daddiu(FP, SP, -wordSize*2);
1.933 __ daddiu(SP, SP, -framesize);
1.934 @@ -1651,10 +1632,10 @@
1.935
1.936 C->set_frame_complete(cbuf.insts_size());
1.937 if (C->has_mach_constant_base_node()) {
1.938 - // NOTE: We set the table base offset here because users might be
1.939 - // emitted before MachConstantBaseNode.
1.940 - Compile::ConstantTable& constant_table = C->constant_table();
1.941 - constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1.942 + // NOTE: We set the table base offset here because users might be
1.943 + // emitted before MachConstantBaseNode.
1.944 + Compile::ConstantTable& constant_table = C->constant_table();
1.945 + constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1.946 }
1.947
1.948 }
1.949 @@ -1695,1627 +1676,1624 @@
1.950
1.951 //Load byte signed
1.952 enc_class load_B_enc (mRegI dst, memory mem) %{
1.953 - MacroAssembler _masm(&cbuf);
1.954 - int dst = $dst$$reg;
1.955 - int base = $mem$$base;
1.956 - int index = $mem$$index;
1.957 - int scale = $mem$$scale;
1.958 - int disp = $mem$$disp;
1.959 -
1.960 - if( index != 0 ) {
1.961 - if( Assembler::is_simm16(disp) ) {
1.962 - if( UseLoongsonISA ) {
1.963 - if (scale == 0) {
1.964 - __ gslbx(as_Register(dst), as_Register(base), as_Register(index), disp);
1.965 - } else {
1.966 - __ dsll(AT, as_Register(index), scale);
1.967 - __ gslbx(as_Register(dst), as_Register(base), AT, disp);
1.968 - }
1.969 - } else {
1.970 - if (scale == 0) {
1.971 - __ addu(AT, as_Register(base), as_Register(index));
1.972 - } else {
1.973 - __ dsll(AT, as_Register(index), scale);
1.974 - __ addu(AT, as_Register(base), AT);
1.975 - }
1.976 - __ lb(as_Register(dst), AT, disp);
1.977 - }
1.978 - } else {
1.979 - if (scale == 0) {
1.980 - __ addu(AT, as_Register(base), as_Register(index));
1.981 - } else {
1.982 - __ dsll(AT, as_Register(index), scale);
1.983 - __ addu(AT, as_Register(base), AT);
1.984 - }
1.985 - __ move(T9, disp);
1.986 - if( UseLoongsonISA ) {
1.987 - __ gslbx(as_Register(dst), AT, T9, 0);
1.988 - } else {
1.989 - __ addu(AT, AT, T9);
1.990 - __ lb(as_Register(dst), AT, 0);
1.991 - }
1.992 - }
1.993 - } else {
1.994 - if( Assembler::is_simm16(disp) ) {
1.995 - __ lb(as_Register(dst), as_Register(base), disp);
1.996 - } else {
1.997 - __ move(T9, disp);
1.998 - if( UseLoongsonISA ) {
1.999 - __ gslbx(as_Register(dst), as_Register(base), T9, 0);
1.1000 - } else {
1.1001 - __ addu(AT, as_Register(base), T9);
1.1002 - __ lb(as_Register(dst), AT, 0);
1.1003 - }
1.1004 - }
1.1005 - }
1.1006 + MacroAssembler _masm(&cbuf);
1.1007 + int dst = $dst$$reg;
1.1008 + int base = $mem$$base;
1.1009 + int index = $mem$$index;
1.1010 + int scale = $mem$$scale;
1.1011 + int disp = $mem$$disp;
1.1012 +
1.1013 + if( index != 0 ) {
1.1014 + if( Assembler::is_simm16(disp) ) {
1.1015 + if( UseLoongsonISA ) {
1.1016 + if (scale == 0) {
1.1017 + __ gslbx(as_Register(dst), as_Register(base), as_Register(index), disp);
1.1018 + } else {
1.1019 + __ dsll(AT, as_Register(index), scale);
1.1020 + __ gslbx(as_Register(dst), as_Register(base), AT, disp);
1.1021 + }
1.1022 + } else {
1.1023 + if (scale == 0) {
1.1024 + __ addu(AT, as_Register(base), as_Register(index));
1.1025 + } else {
1.1026 + __ dsll(AT, as_Register(index), scale);
1.1027 + __ addu(AT, as_Register(base), AT);
1.1028 + }
1.1029 + __ lb(as_Register(dst), AT, disp);
1.1030 + }
1.1031 + } else {
1.1032 + if (scale == 0) {
1.1033 + __ addu(AT, as_Register(base), as_Register(index));
1.1034 + } else {
1.1035 + __ dsll(AT, as_Register(index), scale);
1.1036 + __ addu(AT, as_Register(base), AT);
1.1037 + }
1.1038 + __ move(T9, disp);
1.1039 + if( UseLoongsonISA ) {
1.1040 + __ gslbx(as_Register(dst), AT, T9, 0);
1.1041 + } else {
1.1042 + __ addu(AT, AT, T9);
1.1043 + __ lb(as_Register(dst), AT, 0);
1.1044 + }
1.1045 + }
1.1046 + } else {
1.1047 + if( Assembler::is_simm16(disp) ) {
1.1048 + __ lb(as_Register(dst), as_Register(base), disp);
1.1049 + } else {
1.1050 + __ move(T9, disp);
1.1051 + if( UseLoongsonISA ) {
1.1052 + __ gslbx(as_Register(dst), as_Register(base), T9, 0);
1.1053 + } else {
1.1054 + __ addu(AT, as_Register(base), T9);
1.1055 + __ lb(as_Register(dst), AT, 0);
1.1056 + }
1.1057 + }
1.1058 + }
1.1059 %}
1.1060
1.1061 //Load byte unsigned
1.1062 enc_class load_UB_enc (mRegI dst, memory mem) %{
1.1063 - MacroAssembler _masm(&cbuf);
1.1064 - int dst = $dst$$reg;
1.1065 - int base = $mem$$base;
1.1066 - int index = $mem$$index;
1.1067 - int scale = $mem$$scale;
1.1068 - int disp = $mem$$disp;
1.1069 -
1.1070 - if( index != 0 ) {
1.1071 + MacroAssembler _masm(&cbuf);
1.1072 + int dst = $dst$$reg;
1.1073 + int base = $mem$$base;
1.1074 + int index = $mem$$index;
1.1075 + int scale = $mem$$scale;
1.1076 + int disp = $mem$$disp;
1.1077 +
1.1078 + if( index != 0 ) {
1.1079 + if (scale == 0) {
1.1080 + __ daddu(AT, as_Register(base), as_Register(index));
1.1081 + } else {
1.1082 + __ dsll(AT, as_Register(index), scale);
1.1083 + __ daddu(AT, as_Register(base), AT);
1.1084 + }
1.1085 + if( Assembler::is_simm16(disp) ) {
1.1086 + __ lbu(as_Register(dst), AT, disp);
1.1087 + } else {
1.1088 + __ move(T9, disp);
1.1089 + __ daddu(AT, AT, T9);
1.1090 + __ lbu(as_Register(dst), AT, 0);
1.1091 + }
1.1092 + } else {
1.1093 + if( Assembler::is_simm16(disp) ) {
1.1094 + __ lbu(as_Register(dst), as_Register(base), disp);
1.1095 + } else {
1.1096 + __ move(T9, disp);
1.1097 + __ daddu(AT, as_Register(base), T9);
1.1098 + __ lbu(as_Register(dst), AT, 0);
1.1099 + }
1.1100 + }
1.1101 + %}
1.1102 +
1.1103 + enc_class store_B_reg_enc (memory mem, mRegI src) %{
1.1104 + MacroAssembler _masm(&cbuf);
1.1105 + int src = $src$$reg;
1.1106 + int base = $mem$$base;
1.1107 + int index = $mem$$index;
1.1108 + int scale = $mem$$scale;
1.1109 + int disp = $mem$$disp;
1.1110 +
1.1111 + if( index != 0 ) {
1.1112 + if (scale == 0) {
1.1113 + if( Assembler::is_simm(disp, 8) ) {
1.1114 + if (UseLoongsonISA) {
1.1115 + __ gssbx(as_Register(src), as_Register(base), as_Register(index), disp);
1.1116 + } else {
1.1117 + __ addu(AT, as_Register(base), as_Register(index));
1.1118 + __ sb(as_Register(src), AT, disp);
1.1119 + }
1.1120 + } else if( Assembler::is_simm16(disp) ) {
1.1121 + __ addu(AT, as_Register(base), as_Register(index));
1.1122 + __ sb(as_Register(src), AT, disp);
1.1123 + } else {
1.1124 + __ addu(AT, as_Register(base), as_Register(index));
1.1125 + __ move(T9, disp);
1.1126 + if (UseLoongsonISA) {
1.1127 + __ gssbx(as_Register(src), AT, T9, 0);
1.1128 + } else {
1.1129 + __ addu(AT, AT, T9);
1.1130 + __ sb(as_Register(src), AT, 0);
1.1131 + }
1.1132 + }
1.1133 + } else {
1.1134 + __ dsll(AT, as_Register(index), scale);
1.1135 + if( Assembler::is_simm(disp, 8) ) {
1.1136 + if (UseLoongsonISA) {
1.1137 + __ gssbx(as_Register(src), AT, as_Register(base), disp);
1.1138 + } else {
1.1139 + __ addu(AT, as_Register(base), AT);
1.1140 + __ sb(as_Register(src), AT, disp);
1.1141 + }
1.1142 + } else if( Assembler::is_simm16(disp) ) {
1.1143 + __ addu(AT, as_Register(base), AT);
1.1144 + __ sb(as_Register(src), AT, disp);
1.1145 + } else {
1.1146 + __ addu(AT, as_Register(base), AT);
1.1147 + __ move(T9, disp);
1.1148 + if (UseLoongsonISA) {
1.1149 + __ gssbx(as_Register(src), AT, T9, 0);
1.1150 + } else {
1.1151 + __ addu(AT, AT, T9);
1.1152 + __ sb(as_Register(src), AT, 0);
1.1153 + }
1.1154 + }
1.1155 + }
1.1156 + } else {
1.1157 + if( Assembler::is_simm16(disp) ) {
1.1158 + __ sb(as_Register(src), as_Register(base), disp);
1.1159 + } else {
1.1160 + __ move(T9, disp);
1.1161 + if (UseLoongsonISA) {
1.1162 + __ gssbx(as_Register(src), as_Register(base), T9, 0);
1.1163 + } else {
1.1164 + __ addu(AT, as_Register(base), T9);
1.1165 + __ sb(as_Register(src), AT, 0);
1.1166 + }
1.1167 + }
1.1168 + }
1.1169 + %}
1.1170 +
1.1171 + enc_class store_B_immI_enc (memory mem, immI8 src) %{
1.1172 + MacroAssembler _masm(&cbuf);
1.1173 + int base = $mem$$base;
1.1174 + int index = $mem$$index;
1.1175 + int scale = $mem$$scale;
1.1176 + int disp = $mem$$disp;
1.1177 + int value = $src$$constant;
1.1178 +
1.1179 + if( index != 0 ) {
1.1180 + if (!UseLoongsonISA) {
1.1181 if (scale == 0) {
1.1182 - __ daddu(AT, as_Register(base), as_Register(index));
1.1183 - } else {
1.1184 - __ dsll(AT, as_Register(index), scale);
1.1185 - __ daddu(AT, as_Register(base), AT);
1.1186 - }
1.1187 - if( Assembler::is_simm16(disp) ) {
1.1188 - __ lbu(as_Register(dst), AT, disp);
1.1189 - } else {
1.1190 - __ move(T9, disp);
1.1191 - __ daddu(AT, AT, T9);
1.1192 - __ lbu(as_Register(dst), AT, 0);
1.1193 - }
1.1194 - } else {
1.1195 - if( Assembler::is_simm16(disp) ) {
1.1196 - __ lbu(as_Register(dst), as_Register(base), disp);
1.1197 - } else {
1.1198 - __ move(T9, disp);
1.1199 - __ daddu(AT, as_Register(base), T9);
1.1200 - __ lbu(as_Register(dst), AT, 0);
1.1201 - }
1.1202 - }
1.1203 - %}
1.1204 -
1.1205 - enc_class store_B_reg_enc (memory mem, mRegI src) %{
1.1206 - MacroAssembler _masm(&cbuf);
1.1207 - int src = $src$$reg;
1.1208 - int base = $mem$$base;
1.1209 - int index = $mem$$index;
1.1210 - int scale = $mem$$scale;
1.1211 - int disp = $mem$$disp;
1.1212 -
1.1213 - if( index != 0 ) {
1.1214 + __ daddu(AT, as_Register(base), as_Register(index));
1.1215 + } else {
1.1216 + __ dsll(AT, as_Register(index), scale);
1.1217 + __ daddu(AT, as_Register(base), AT);
1.1218 + }
1.1219 + if( Assembler::is_simm16(disp) ) {
1.1220 + if (value == 0) {
1.1221 + __ sb(R0, AT, disp);
1.1222 + } else {
1.1223 + __ move(T9, value);
1.1224 + __ sb(T9, AT, disp);
1.1225 + }
1.1226 + } else {
1.1227 + if (value == 0) {
1.1228 + __ move(T9, disp);
1.1229 + __ daddu(AT, AT, T9);
1.1230 + __ sb(R0, AT, 0);
1.1231 + } else {
1.1232 + __ move(T9, disp);
1.1233 + __ daddu(AT, AT, T9);
1.1234 + __ move(T9, value);
1.1235 + __ sb(T9, AT, 0);
1.1236 + }
1.1237 + }
1.1238 + } else {
1.1239 +
1.1240 if (scale == 0) {
1.1241 - if( Assembler::is_simm(disp, 8) ) {
1.1242 - if (UseLoongsonISA) {
1.1243 - __ gssbx(as_Register(src), as_Register(base), as_Register(index), disp);
1.1244 - } else {
1.1245 - __ addu(AT, as_Register(base), as_Register(index));
1.1246 - __ sb(as_Register(src), AT, disp);
1.1247 - }
1.1248 - } else if( Assembler::is_simm16(disp) ) {
1.1249 - __ addu(AT, as_Register(base), as_Register(index));
1.1250 - __ sb(as_Register(src), AT, disp);
1.1251 - } else {
1.1252 - __ addu(AT, as_Register(base), as_Register(index));
1.1253 + if( Assembler::is_simm(disp, 8) ) {
1.1254 + if (value == 0) {
1.1255 + __ gssbx(R0, as_Register(base), as_Register(index), disp);
1.1256 + } else {
1.1257 + __ move(T9, value);
1.1258 + __ gssbx(T9, as_Register(base), as_Register(index), disp);
1.1259 + }
1.1260 + } else if( Assembler::is_simm16(disp) ) {
1.1261 + __ daddu(AT, as_Register(base), as_Register(index));
1.1262 + if (value == 0) {
1.1263 + __ sb(R0, AT, disp);
1.1264 + } else {
1.1265 + __ move(T9, value);
1.1266 + __ sb(T9, AT, disp);
1.1267 + }
1.1268 + } else {
1.1269 + if (value == 0) {
1.1270 + __ daddu(AT, as_Register(base), as_Register(index));
1.1271 __ move(T9, disp);
1.1272 - if (UseLoongsonISA) {
1.1273 - __ gssbx(as_Register(src), AT, T9, 0);
1.1274 - } else {
1.1275 - __ addu(AT, AT, T9);
1.1276 - __ sb(as_Register(src), AT, 0);
1.1277 - }
1.1278 - }
1.1279 - } else {
1.1280 - __ dsll(AT, as_Register(index), scale);
1.1281 - if( Assembler::is_simm(disp, 8) ) {
1.1282 - if (UseLoongsonISA) {
1.1283 - __ gssbx(as_Register(src), AT, as_Register(base), disp);
1.1284 - } else {
1.1285 - __ addu(AT, as_Register(base), AT);
1.1286 - __ sb(as_Register(src), AT, disp);
1.1287 - }
1.1288 - } else if( Assembler::is_simm16(disp) ) {
1.1289 - __ addu(AT, as_Register(base), AT);
1.1290 - __ sb(as_Register(src), AT, disp);
1.1291 - } else {
1.1292 - __ addu(AT, as_Register(base), AT);
1.1293 + __ gssbx(R0, AT, T9, 0);
1.1294 + } else {
1.1295 + __ move(AT, disp);
1.1296 + __ move(T9, value);
1.1297 + __ daddu(AT, as_Register(base), AT);
1.1298 + __ gssbx(T9, AT, as_Register(index), 0);
1.1299 + }
1.1300 + }
1.1301 +
1.1302 + } else {
1.1303 +
1.1304 + if( Assembler::is_simm(disp, 8) ) {
1.1305 + __ dsll(AT, as_Register(index), scale);
1.1306 + if (value == 0) {
1.1307 + __ gssbx(R0, as_Register(base), AT, disp);
1.1308 + } else {
1.1309 + __ move(T9, value);
1.1310 + __ gssbx(T9, as_Register(base), AT, disp);
1.1311 + }
1.1312 + } else if( Assembler::is_simm16(disp) ) {
1.1313 + __ dsll(AT, as_Register(index), scale);
1.1314 + __ daddu(AT, as_Register(base), AT);
1.1315 + if (value == 0) {
1.1316 + __ sb(R0, AT, disp);
1.1317 + } else {
1.1318 + __ move(T9, value);
1.1319 + __ sb(T9, AT, disp);
1.1320 + }
1.1321 + } else {
1.1322 + __ dsll(AT, as_Register(index), scale);
1.1323 + if (value == 0) {
1.1324 + __ daddu(AT, as_Register(base), AT);
1.1325 __ move(T9, disp);
1.1326 - if (UseLoongsonISA) {
1.1327 - __ gssbx(as_Register(src), AT, T9, 0);
1.1328 - } else {
1.1329 - __ addu(AT, AT, T9);
1.1330 - __ sb(as_Register(src), AT, 0);
1.1331 - }
1.1332 - }
1.1333 - }
1.1334 - } else {
1.1335 - if( Assembler::is_simm16(disp) ) {
1.1336 - __ sb(as_Register(src), as_Register(base), disp);
1.1337 - } else {
1.1338 - __ move(T9, disp);
1.1339 - if (UseLoongsonISA) {
1.1340 - __ gssbx(as_Register(src), as_Register(base), T9, 0);
1.1341 - } else {
1.1342 - __ addu(AT, as_Register(base), T9);
1.1343 - __ sb(as_Register(src), AT, 0);
1.1344 - }
1.1345 - }
1.1346 - }
1.1347 - %}
1.1348 -
1.1349 - enc_class store_B_immI_enc (memory mem, immI8 src) %{
1.1350 - MacroAssembler _masm(&cbuf);
1.1351 - int base = $mem$$base;
1.1352 - int index = $mem$$index;
1.1353 - int scale = $mem$$scale;
1.1354 - int disp = $mem$$disp;
1.1355 - int value = $src$$constant;
1.1356 -
1.1357 - if( index != 0 ) {
1.1358 - if (!UseLoongsonISA) {
1.1359 - if (scale == 0) {
1.1360 - __ daddu(AT, as_Register(base), as_Register(index));
1.1361 - } else {
1.1362 - __ dsll(AT, as_Register(index), scale);
1.1363 - __ daddu(AT, as_Register(base), AT);
1.1364 - }
1.1365 - if( Assembler::is_simm16(disp) ) {
1.1366 - if (value == 0) {
1.1367 - __ sb(R0, AT, disp);
1.1368 - } else {
1.1369 - __ move(T9, value);
1.1370 - __ sb(T9, AT, disp);
1.1371 - }
1.1372 - } else {
1.1373 - if (value == 0) {
1.1374 - __ move(T9, disp);
1.1375 - __ daddu(AT, AT, T9);
1.1376 - __ sb(R0, AT, 0);
1.1377 - } else {
1.1378 - __ move(T9, disp);
1.1379 - __ daddu(AT, AT, T9);
1.1380 - __ move(T9, value);
1.1381 - __ sb(T9, AT, 0);
1.1382 - }
1.1383 - }
1.1384 - } else {
1.1385 -
1.1386 - if (scale == 0) {
1.1387 - if( Assembler::is_simm(disp, 8) ) {
1.1388 - if (value == 0) {
1.1389 - __ gssbx(R0, as_Register(base), as_Register(index), disp);
1.1390 - } else {
1.1391 - __ move(T9, value);
1.1392 - __ gssbx(T9, as_Register(base), as_Register(index), disp);
1.1393 - }
1.1394 - } else if( Assembler::is_simm16(disp) ) {
1.1395 - __ daddu(AT, as_Register(base), as_Register(index));
1.1396 - if (value == 0) {
1.1397 - __ sb(R0, AT, disp);
1.1398 - } else {
1.1399 - __ move(T9, value);
1.1400 - __ sb(T9, AT, disp);
1.1401 - }
1.1402 - } else {
1.1403 - if (value == 0) {
1.1404 - __ daddu(AT, as_Register(base), as_Register(index));
1.1405 - __ move(T9, disp);
1.1406 - __ gssbx(R0, AT, T9, 0);
1.1407 - } else {
1.1408 - __ move(AT, disp);
1.1409 - __ move(T9, value);
1.1410 - __ daddu(AT, as_Register(base), AT);
1.1411 - __ gssbx(T9, AT, as_Register(index), 0);
1.1412 - }
1.1413 - }
1.1414 -
1.1415 - } else {
1.1416 -
1.1417 - if( Assembler::is_simm(disp, 8) ) {
1.1418 - __ dsll(AT, as_Register(index), scale);
1.1419 - if (value == 0) {
1.1420 - __ gssbx(R0, as_Register(base), AT, disp);
1.1421 - } else {
1.1422 - __ move(T9, value);
1.1423 - __ gssbx(T9, as_Register(base), AT, disp);
1.1424 - }
1.1425 - } else if( Assembler::is_simm16(disp) ) {
1.1426 - __ dsll(AT, as_Register(index), scale);
1.1427 - __ daddu(AT, as_Register(base), AT);
1.1428 - if (value == 0) {
1.1429 - __ sb(R0, AT, disp);
1.1430 - } else {
1.1431 - __ move(T9, value);
1.1432 - __ sb(T9, AT, disp);
1.1433 - }
1.1434 - } else {
1.1435 - __ dsll(AT, as_Register(index), scale);
1.1436 - if (value == 0) {
1.1437 - __ daddu(AT, as_Register(base), AT);
1.1438 - __ move(T9, disp);
1.1439 - __ gssbx(R0, AT, T9, 0);
1.1440 - } else {
1.1441 - __ move(T9, disp);
1.1442 - __ daddu(AT, AT, T9);
1.1443 - __ move(T9, value);
1.1444 - __ gssbx(T9, as_Register(base), AT, 0);
1.1445 - }
1.1446 - }
1.1447 - }
1.1448 - }
1.1449 - } else {
1.1450 - if( Assembler::is_simm16(disp) ) {
1.1451 - if (value == 0) {
1.1452 - __ sb(R0, as_Register(base), disp);
1.1453 - } else {
1.1454 + __ gssbx(R0, AT, T9, 0);
1.1455 + } else {
1.1456 + __ move(T9, disp);
1.1457 + __ daddu(AT, AT, T9);
1.1458 + __ move(T9, value);
1.1459 + __ gssbx(T9, as_Register(base), AT, 0);
1.1460 + }
1.1461 + }
1.1462 + }
1.1463 + }
1.1464 + } else {
1.1465 + if( Assembler::is_simm16(disp) ) {
1.1466 + if (value == 0) {
1.1467 + __ sb(R0, as_Register(base), disp);
1.1468 + } else {
1.1469 + __ move(AT, value);
1.1470 + __ sb(AT, as_Register(base), disp);
1.1471 + }
1.1472 + } else {
1.1473 + if (value == 0) {
1.1474 + __ move(T9, disp);
1.1475 + if (UseLoongsonISA) {
1.1476 + __ gssbx(R0, as_Register(base), T9, 0);
1.1477 + } else {
1.1478 + __ daddu(AT, as_Register(base), T9);
1.1479 + __ sb(R0, AT, 0);
1.1480 + }
1.1481 + } else {
1.1482 + __ move(T9, disp);
1.1483 + if (UseLoongsonISA) {
1.1484 + __ move(AT, value);
1.1485 + __ gssbx(AT, as_Register(base), T9, 0);
1.1486 + } else {
1.1487 + __ daddu(AT, as_Register(base), T9);
1.1488 + __ move(T9, value);
1.1489 + __ sb(T9, AT, 0);
1.1490 + }
1.1491 + }
1.1492 + }
1.1493 + }
1.1494 + %}
1.1495 +
1.1496 +
1.1497 + enc_class store_B_immI_enc_sync (memory mem, immI8 src) %{
1.1498 + MacroAssembler _masm(&cbuf);
1.1499 + int base = $mem$$base;
1.1500 + int index = $mem$$index;
1.1501 + int scale = $mem$$scale;
1.1502 + int disp = $mem$$disp;
1.1503 + int value = $src$$constant;
1.1504 +
1.1505 + if( index != 0 ) {
1.1506 + if ( UseLoongsonISA ) {
1.1507 + if ( Assembler::is_simm(disp,8) ) {
1.1508 + if ( scale == 0 ) {
1.1509 + if ( value == 0 ) {
1.1510 + __ gssbx(R0, as_Register(base), as_Register(index), disp);
1.1511 + } else {
1.1512 __ move(AT, value);
1.1513 - __ sb(AT, as_Register(base), disp);
1.1514 - }
1.1515 - } else {
1.1516 - if (value == 0) {
1.1517 - __ move(T9, disp);
1.1518 - if (UseLoongsonISA) {
1.1519 - __ gssbx(R0, as_Register(base), T9, 0);
1.1520 - } else {
1.1521 - __ daddu(AT, as_Register(base), T9);
1.1522 - __ sb(R0, AT, 0);
1.1523 - }
1.1524 - } else {
1.1525 - __ move(T9, disp);
1.1526 - if (UseLoongsonISA) {
1.1527 - __ move(AT, value);
1.1528 - __ gssbx(AT, as_Register(base), T9, 0);
1.1529 - } else {
1.1530 - __ daddu(AT, as_Register(base), T9);
1.1531 - __ move(T9, value);
1.1532 - __ sb(T9, AT, 0);
1.1533 - }
1.1534 - }
1.1535 - }
1.1536 - }
1.1537 - %}
1.1538 -
1.1539 -
1.1540 - enc_class store_B_immI_enc_sync (memory mem, immI8 src) %{
1.1541 - MacroAssembler _masm(&cbuf);
1.1542 - int base = $mem$$base;
1.1543 - int index = $mem$$index;
1.1544 - int scale = $mem$$scale;
1.1545 - int disp = $mem$$disp;
1.1546 - int value = $src$$constant;
1.1547 -
1.1548 - if( index != 0 ) {
1.1549 - if ( UseLoongsonISA ) {
1.1550 - if ( Assembler::is_simm(disp,8) ) {
1.1551 - if ( scale == 0 ) {
1.1552 - if ( value == 0 ) {
1.1553 - __ gssbx(R0, as_Register(base), as_Register(index), disp);
1.1554 - } else {
1.1555 - __ move(AT, value);
1.1556 - __ gssbx(AT, as_Register(base), as_Register(index), disp);
1.1557 - }
1.1558 - } else {
1.1559 - __ dsll(AT, as_Register(index), scale);
1.1560 - if ( value == 0 ) {
1.1561 - __ gssbx(R0, as_Register(base), AT, disp);
1.1562 - } else {
1.1563 - __ move(T9, value);
1.1564 - __ gssbx(T9, as_Register(base), AT, disp);
1.1565 - }
1.1566 - }
1.1567 - } else if ( Assembler::is_simm16(disp) ) {
1.1568 - if ( scale == 0 ) {
1.1569 - __ daddu(AT, as_Register(base), as_Register(index));
1.1570 - if ( value == 0 ){
1.1571 - __ sb(R0, AT, disp);
1.1572 - } else {
1.1573 - __ move(T9, value);
1.1574 - __ sb(T9, AT, disp);
1.1575 - }
1.1576 - } else {
1.1577 - __ dsll(AT, as_Register(index), scale);
1.1578 - __ daddu(AT, as_Register(base), AT);
1.1579 - if ( value == 0 ) {
1.1580 - __ sb(R0, AT, disp);
1.1581 - } else {
1.1582 - __ move(T9, value);
1.1583 - __ sb(T9, AT, disp);
1.1584 - }
1.1585 - }
1.1586 - } else {
1.1587 - if ( scale == 0 ) {
1.1588 - __ move(AT, disp);
1.1589 - __ daddu(AT, as_Register(index), AT);
1.1590 - if ( value == 0 ) {
1.1591 - __ gssbx(R0, as_Register(base), AT, 0);
1.1592 - } else {
1.1593 - __ move(T9, value);
1.1594 - __ gssbx(T9, as_Register(base), AT, 0);
1.1595 - }
1.1596 - } else {
1.1597 - __ dsll(AT, as_Register(index), scale);
1.1598 - __ move(T9, disp);
1.1599 - __ daddu(AT, AT, T9);
1.1600 - if ( value == 0 ) {
1.1601 - __ gssbx(R0, as_Register(base), AT, 0);
1.1602 - } else {
1.1603 - __ move(T9, value);
1.1604 - __ gssbx(T9, as_Register(base), AT, 0);
1.1605 - }
1.1606 - }
1.1607 - }
1.1608 - } else { //not use loongson isa
1.1609 - if (scale == 0) {
1.1610 - __ daddu(AT, as_Register(base), as_Register(index));
1.1611 - } else {
1.1612 - __ dsll(AT, as_Register(index), scale);
1.1613 - __ daddu(AT, as_Register(base), AT);
1.1614 - }
1.1615 - if( Assembler::is_simm16(disp) ) {
1.1616 - if (value == 0) {
1.1617 - __ sb(R0, AT, disp);
1.1618 - } else {
1.1619 - __ move(T9, value);
1.1620 - __ sb(T9, AT, disp);
1.1621 - }
1.1622 - } else {
1.1623 - if (value == 0) {
1.1624 - __ move(T9, disp);
1.1625 - __ daddu(AT, AT, T9);
1.1626 - __ sb(R0, AT, 0);
1.1627 - } else {
1.1628 - __ move(T9, disp);
1.1629 - __ daddu(AT, AT, T9);
1.1630 - __ move(T9, value);
1.1631 - __ sb(T9, AT, 0);
1.1632 - }
1.1633 - }
1.1634 - }
1.1635 - } else {
1.1636 - if ( UseLoongsonISA ){
1.1637 - if ( Assembler::is_simm16(disp) ){
1.1638 - if ( value == 0 ) {
1.1639 - __ sb(R0, as_Register(base), disp);
1.1640 - } else {
1.1641 - __ move(AT, value);
1.1642 - __ sb(AT, as_Register(base), disp);
1.1643 - }
1.1644 - } else {
1.1645 - __ move(AT, disp);
1.1646 - if ( value == 0 ) {
1.1647 - __ gssbx(R0, as_Register(base), AT, 0);
1.1648 - } else {
1.1649 - __ move(T9, value);
1.1650 - __ gssbx(T9, as_Register(base), AT, 0);
1.1651 - }
1.1652 - }
1.1653 - } else {
1.1654 - if( Assembler::is_simm16(disp) ) {
1.1655 - if (value == 0) {
1.1656 - __ sb(R0, as_Register(base), disp);
1.1657 - } else {
1.1658 - __ move(AT, value);
1.1659 - __ sb(AT, as_Register(base), disp);
1.1660 - }
1.1661 - } else {
1.1662 - if (value == 0) {
1.1663 - __ move(T9, disp);
1.1664 - __ daddu(AT, as_Register(base), T9);
1.1665 - __ sb(R0, AT, 0);
1.1666 - } else {
1.1667 - __ move(T9, disp);
1.1668 - __ daddu(AT, as_Register(base), T9);
1.1669 - __ move(T9, value);
1.1670 - __ sb(T9, AT, 0);
1.1671 - }
1.1672 - }
1.1673 - }
1.1674 - }
1.1675 -
1.1676 - __ sync();
1.1677 + __ gssbx(AT, as_Register(base), as_Register(index), disp);
1.1678 + }
1.1679 + } else {
1.1680 + __ dsll(AT, as_Register(index), scale);
1.1681 + if ( value == 0 ) {
1.1682 + __ gssbx(R0, as_Register(base), AT, disp);
1.1683 + } else {
1.1684 + __ move(T9, value);
1.1685 + __ gssbx(T9, as_Register(base), AT, disp);
1.1686 + }
1.1687 + }
1.1688 + } else if ( Assembler::is_simm16(disp) ) {
1.1689 + if ( scale == 0 ) {
1.1690 + __ daddu(AT, as_Register(base), as_Register(index));
1.1691 + if ( value == 0 ){
1.1692 + __ sb(R0, AT, disp);
1.1693 + } else {
1.1694 + __ move(T9, value);
1.1695 + __ sb(T9, AT, disp);
1.1696 + }
1.1697 + } else {
1.1698 + __ dsll(AT, as_Register(index), scale);
1.1699 + __ daddu(AT, as_Register(base), AT);
1.1700 + if ( value == 0 ) {
1.1701 + __ sb(R0, AT, disp);
1.1702 + } else {
1.1703 + __ move(T9, value);
1.1704 + __ sb(T9, AT, disp);
1.1705 + }
1.1706 + }
1.1707 + } else {
1.1708 + if ( scale == 0 ) {
1.1709 + __ move(AT, disp);
1.1710 + __ daddu(AT, as_Register(index), AT);
1.1711 + if ( value == 0 ) {
1.1712 + __ gssbx(R0, as_Register(base), AT, 0);
1.1713 + } else {
1.1714 + __ move(T9, value);
1.1715 + __ gssbx(T9, as_Register(base), AT, 0);
1.1716 + }
1.1717 + } else {
1.1718 + __ dsll(AT, as_Register(index), scale);
1.1719 + __ move(T9, disp);
1.1720 + __ daddu(AT, AT, T9);
1.1721 + if ( value == 0 ) {
1.1722 + __ gssbx(R0, as_Register(base), AT, 0);
1.1723 + } else {
1.1724 + __ move(T9, value);
1.1725 + __ gssbx(T9, as_Register(base), AT, 0);
1.1726 + }
1.1727 + }
1.1728 + }
1.1729 + } else { //not use loongson isa
1.1730 + if (scale == 0) {
1.1731 + __ daddu(AT, as_Register(base), as_Register(index));
1.1732 + } else {
1.1733 + __ dsll(AT, as_Register(index), scale);
1.1734 + __ daddu(AT, as_Register(base), AT);
1.1735 + }
1.1736 + if( Assembler::is_simm16(disp) ) {
1.1737 + if (value == 0) {
1.1738 + __ sb(R0, AT, disp);
1.1739 + } else {
1.1740 + __ move(T9, value);
1.1741 + __ sb(T9, AT, disp);
1.1742 + }
1.1743 + } else {
1.1744 + if (value == 0) {
1.1745 + __ move(T9, disp);
1.1746 + __ daddu(AT, AT, T9);
1.1747 + __ sb(R0, AT, 0);
1.1748 + } else {
1.1749 + __ move(T9, disp);
1.1750 + __ daddu(AT, AT, T9);
1.1751 + __ move(T9, value);
1.1752 + __ sb(T9, AT, 0);
1.1753 + }
1.1754 + }
1.1755 + }
1.1756 + } else {
1.1757 + if ( UseLoongsonISA ){
1.1758 + if ( Assembler::is_simm16(disp) ){
1.1759 + if ( value == 0 ) {
1.1760 + __ sb(R0, as_Register(base), disp);
1.1761 + } else {
1.1762 + __ move(AT, value);
1.1763 + __ sb(AT, as_Register(base), disp);
1.1764 + }
1.1765 + } else {
1.1766 + __ move(AT, disp);
1.1767 + if ( value == 0 ) {
1.1768 + __ gssbx(R0, as_Register(base), AT, 0);
1.1769 + } else {
1.1770 + __ move(T9, value);
1.1771 + __ gssbx(T9, as_Register(base), AT, 0);
1.1772 + }
1.1773 + }
1.1774 + } else {
1.1775 + if( Assembler::is_simm16(disp) ) {
1.1776 + if (value == 0) {
1.1777 + __ sb(R0, as_Register(base), disp);
1.1778 + } else {
1.1779 + __ move(AT, value);
1.1780 + __ sb(AT, as_Register(base), disp);
1.1781 + }
1.1782 + } else {
1.1783 + if (value == 0) {
1.1784 + __ move(T9, disp);
1.1785 + __ daddu(AT, as_Register(base), T9);
1.1786 + __ sb(R0, AT, 0);
1.1787 + } else {
1.1788 + __ move(T9, disp);
1.1789 + __ daddu(AT, as_Register(base), T9);
1.1790 + __ move(T9, value);
1.1791 + __ sb(T9, AT, 0);
1.1792 + }
1.1793 + }
1.1794 + }
1.1795 + }
1.1796 +
1.1797 + __ sync();
1.1798 %}
1.1799
1.1800 // Load Short (16bit signed)
1.1801 enc_class load_S_enc (mRegI dst, memory mem) %{
1.1802 - MacroAssembler _masm(&cbuf);
1.1803 - int dst = $dst$$reg;
1.1804 - int base = $mem$$base;
1.1805 - int index = $mem$$index;
1.1806 - int scale = $mem$$scale;
1.1807 - int disp = $mem$$disp;
1.1808 -
1.1809 - if( index != 0 ) {
1.1810 - if ( UseLoongsonISA ) {
1.1811 - if ( Assembler::is_simm(disp, 8) ) {
1.1812 - if (scale == 0) {
1.1813 - __ gslhx(as_Register(dst), as_Register(base), as_Register(index), disp);
1.1814 - } else {
1.1815 - __ dsll(AT, as_Register(index), scale);
1.1816 - __ gslhx(as_Register(dst), as_Register(base), AT, disp);
1.1817 - }
1.1818 - } else if ( Assembler::is_simm16(disp) ) {
1.1819 - if (scale == 0) {
1.1820 - __ daddu(AT, as_Register(base), as_Register(index));
1.1821 - __ lh(as_Register(dst), AT, disp);
1.1822 - } else {
1.1823 - __ dsll(AT, as_Register(index), scale);
1.1824 - __ daddu(AT, as_Register(base), AT);
1.1825 - __ lh(as_Register(dst), AT, disp);
1.1826 - }
1.1827 - } else {
1.1828 - if (scale == 0) {
1.1829 - __ move(AT, disp);
1.1830 - __ daddu(AT, as_Register(index), AT);
1.1831 - __ gslhx(as_Register(dst), as_Register(base), AT, 0);
1.1832 - } else {
1.1833 - __ dsll(AT, as_Register(index), scale);
1.1834 - __ move(T9, disp);
1.1835 - __ daddu(AT, AT, T9);
1.1836 - __ gslhx(as_Register(dst), as_Register(base), AT, 0);
1.1837 - }
1.1838 - }
1.1839 - } else { // not use loongson isa
1.1840 - if (scale == 0) {
1.1841 - __ daddu(AT, as_Register(base), as_Register(index));
1.1842 - } else {
1.1843 - __ dsll(AT, as_Register(index), scale);
1.1844 - __ daddu(AT, as_Register(base), AT);
1.1845 - }
1.1846 - if( Assembler::is_simm16(disp) ) {
1.1847 - __ lh(as_Register(dst), AT, disp);
1.1848 - } else {
1.1849 - __ move(T9, disp);
1.1850 - __ daddu(AT, AT, T9);
1.1851 - __ lh(as_Register(dst), AT, 0);
1.1852 - }
1.1853 - }
1.1854 - } else { // index is 0
1.1855 - if ( UseLoongsonISA ) {
1.1856 - if ( Assembler::is_simm16(disp) ) {
1.1857 - __ lh(as_Register(dst), as_Register(base), disp);
1.1858 - } else {
1.1859 - __ move(T9, disp);
1.1860 - __ gslhx(as_Register(dst), as_Register(base), T9, 0);
1.1861 - }
1.1862 - } else { //not use loongson isa
1.1863 - if( Assembler::is_simm16(disp) ) {
1.1864 - __ lh(as_Register(dst), as_Register(base), disp);
1.1865 - } else {
1.1866 - __ move(T9, disp);
1.1867 - __ daddu(AT, as_Register(base), T9);
1.1868 - __ lh(as_Register(dst), AT, 0);
1.1869 - }
1.1870 - }
1.1871 - }
1.1872 + MacroAssembler _masm(&cbuf);
1.1873 + int dst = $dst$$reg;
1.1874 + int base = $mem$$base;
1.1875 + int index = $mem$$index;
1.1876 + int scale = $mem$$scale;
1.1877 + int disp = $mem$$disp;
1.1878 +
1.1879 + if( index != 0 ) {
1.1880 + if ( UseLoongsonISA ) {
1.1881 + if ( Assembler::is_simm(disp, 8) ) {
1.1882 + if (scale == 0) {
1.1883 + __ gslhx(as_Register(dst), as_Register(base), as_Register(index), disp);
1.1884 + } else {
1.1885 + __ dsll(AT, as_Register(index), scale);
1.1886 + __ gslhx(as_Register(dst), as_Register(base), AT, disp);
1.1887 + }
1.1888 + } else if ( Assembler::is_simm16(disp) ) {
1.1889 + if (scale == 0) {
1.1890 + __ daddu(AT, as_Register(base), as_Register(index));
1.1891 + __ lh(as_Register(dst), AT, disp);
1.1892 + } else {
1.1893 + __ dsll(AT, as_Register(index), scale);
1.1894 + __ daddu(AT, as_Register(base), AT);
1.1895 + __ lh(as_Register(dst), AT, disp);
1.1896 + }
1.1897 + } else {
1.1898 + if (scale == 0) {
1.1899 + __ move(AT, disp);
1.1900 + __ daddu(AT, as_Register(index), AT);
1.1901 + __ gslhx(as_Register(dst), as_Register(base), AT, 0);
1.1902 + } else {
1.1903 + __ dsll(AT, as_Register(index), scale);
1.1904 + __ move(T9, disp);
1.1905 + __ daddu(AT, AT, T9);
1.1906 + __ gslhx(as_Register(dst), as_Register(base), AT, 0);
1.1907 + }
1.1908 + }
1.1909 + } else { // not use loongson isa
1.1910 + if (scale == 0) {
1.1911 + __ daddu(AT, as_Register(base), as_Register(index));
1.1912 + } else {
1.1913 + __ dsll(AT, as_Register(index), scale);
1.1914 + __ daddu(AT, as_Register(base), AT);
1.1915 + }
1.1916 + if( Assembler::is_simm16(disp) ) {
1.1917 + __ lh(as_Register(dst), AT, disp);
1.1918 + } else {
1.1919 + __ move(T9, disp);
1.1920 + __ daddu(AT, AT, T9);
1.1921 + __ lh(as_Register(dst), AT, 0);
1.1922 + }
1.1923 + }
1.1924 + } else { // index is 0
1.1925 + if ( UseLoongsonISA ) {
1.1926 + if ( Assembler::is_simm16(disp) ) {
1.1927 + __ lh(as_Register(dst), as_Register(base), disp);
1.1928 + } else {
1.1929 + __ move(T9, disp);
1.1930 + __ gslhx(as_Register(dst), as_Register(base), T9, 0);
1.1931 + }
1.1932 + } else { //not use loongson isa
1.1933 + if( Assembler::is_simm16(disp) ) {
1.1934 + __ lh(as_Register(dst), as_Register(base), disp);
1.1935 + } else {
1.1936 + __ move(T9, disp);
1.1937 + __ daddu(AT, as_Register(base), T9);
1.1938 + __ lh(as_Register(dst), AT, 0);
1.1939 + }
1.1940 + }
1.1941 + }
1.1942 %}
1.1943
1.1944 // Load Char (16bit unsigned)
1.1945 enc_class load_C_enc (mRegI dst, memory mem) %{
1.1946 - MacroAssembler _masm(&cbuf);
1.1947 - int dst = $dst$$reg;
1.1948 - int base = $mem$$base;
1.1949 - int index = $mem$$index;
1.1950 - int scale = $mem$$scale;
1.1951 - int disp = $mem$$disp;
1.1952 -
1.1953 - if( index != 0 ) {
1.1954 - if (scale == 0) {
1.1955 - __ daddu(AT, as_Register(base), as_Register(index));
1.1956 - } else {
1.1957 - __ dsll(AT, as_Register(index), scale);
1.1958 - __ daddu(AT, as_Register(base), AT);
1.1959 - }
1.1960 - if( Assembler::is_simm16(disp) ) {
1.1961 - __ lhu(as_Register(dst), AT, disp);
1.1962 - } else {
1.1963 - __ move(T9, disp);
1.1964 - __ addu(AT, AT, T9);
1.1965 - __ lhu(as_Register(dst), AT, 0);
1.1966 - }
1.1967 - } else {
1.1968 - if( Assembler::is_simm16(disp) ) {
1.1969 - __ lhu(as_Register(dst), as_Register(base), disp);
1.1970 - } else {
1.1971 - __ move(T9, disp);
1.1972 - __ daddu(AT, as_Register(base), T9);
1.1973 - __ lhu(as_Register(dst), AT, 0);
1.1974 - }
1.1975 - }
1.1976 + MacroAssembler _masm(&cbuf);
1.1977 + int dst = $dst$$reg;
1.1978 + int base = $mem$$base;
1.1979 + int index = $mem$$index;
1.1980 + int scale = $mem$$scale;
1.1981 + int disp = $mem$$disp;
1.1982 +
1.1983 + if( index != 0 ) {
1.1984 + if (scale == 0) {
1.1985 + __ daddu(AT, as_Register(base), as_Register(index));
1.1986 + } else {
1.1987 + __ dsll(AT, as_Register(index), scale);
1.1988 + __ daddu(AT, as_Register(base), AT);
1.1989 + }
1.1990 + if( Assembler::is_simm16(disp) ) {
1.1991 + __ lhu(as_Register(dst), AT, disp);
1.1992 + } else {
1.1993 + __ move(T9, disp);
1.1994 + __ addu(AT, AT, T9);
1.1995 + __ lhu(as_Register(dst), AT, 0);
1.1996 + }
1.1997 + } else {
1.1998 + if( Assembler::is_simm16(disp) ) {
1.1999 + __ lhu(as_Register(dst), as_Register(base), disp);
1.2000 + } else {
1.2001 + __ move(T9, disp);
1.2002 + __ daddu(AT, as_Register(base), T9);
1.2003 + __ lhu(as_Register(dst), AT, 0);
1.2004 + }
1.2005 + }
1.2006 %}
1.2007
1.2008 // Store Char (16bit unsigned)
1.2009 enc_class store_C_reg_enc (memory mem, mRegI src) %{
1.2010 - MacroAssembler _masm(&cbuf);
1.2011 - int src = $src$$reg;
1.2012 - int base = $mem$$base;
1.2013 - int index = $mem$$index;
1.2014 - int scale = $mem$$scale;
1.2015 - int disp = $mem$$disp;
1.2016 -
1.2017 - if( index != 0 ) {
1.2018 - if( Assembler::is_simm16(disp) ) {
1.2019 - if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
1.2020 - if (scale == 0) {
1.2021 - __ gsshx(as_Register(src), as_Register(base), as_Register(index), disp);
1.2022 - } else {
1.2023 - __ dsll(AT, as_Register(index), scale);
1.2024 - __ gsshx(as_Register(src), as_Register(base), AT, disp);
1.2025 - }
1.2026 - } else {
1.2027 - if (scale == 0) {
1.2028 - __ addu(AT, as_Register(base), as_Register(index));
1.2029 - } else {
1.2030 - __ dsll(AT, as_Register(index), scale);
1.2031 - __ addu(AT, as_Register(base), AT);
1.2032 - }
1.2033 - __ sh(as_Register(src), AT, disp);
1.2034 - }
1.2035 - } else {
1.2036 - if (scale == 0) {
1.2037 - __ addu(AT, as_Register(base), as_Register(index));
1.2038 - } else {
1.2039 - __ dsll(AT, as_Register(index), scale);
1.2040 - __ addu(AT, as_Register(base), AT);
1.2041 - }
1.2042 - __ move(T9, disp);
1.2043 - if( UseLoongsonISA ) {
1.2044 - __ gsshx(as_Register(src), AT, T9, 0);
1.2045 - } else {
1.2046 - __ addu(AT, AT, T9);
1.2047 - __ sh(as_Register(src), AT, 0);
1.2048 - }
1.2049 - }
1.2050 - } else {
1.2051 - if( Assembler::is_simm16(disp) ) {
1.2052 - __ sh(as_Register(src), as_Register(base), disp);
1.2053 - } else {
1.2054 - __ move(T9, disp);
1.2055 - if( UseLoongsonISA ) {
1.2056 - __ gsshx(as_Register(src), as_Register(base), T9, 0);
1.2057 - } else {
1.2058 - __ addu(AT, as_Register(base), T9);
1.2059 - __ sh(as_Register(src), AT, 0);
1.2060 - }
1.2061 - }
1.2062 - }
1.2063 + MacroAssembler _masm(&cbuf);
1.2064 + int src = $src$$reg;
1.2065 + int base = $mem$$base;
1.2066 + int index = $mem$$index;
1.2067 + int scale = $mem$$scale;
1.2068 + int disp = $mem$$disp;
1.2069 +
1.2070 + if( index != 0 ) {
1.2071 + if( Assembler::is_simm16(disp) ) {
1.2072 + if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
1.2073 + if (scale == 0) {
1.2074 + __ gsshx(as_Register(src), as_Register(base), as_Register(index), disp);
1.2075 + } else {
1.2076 + __ dsll(AT, as_Register(index), scale);
1.2077 + __ gsshx(as_Register(src), as_Register(base), AT, disp);
1.2078 + }
1.2079 + } else {
1.2080 + if (scale == 0) {
1.2081 + __ addu(AT, as_Register(base), as_Register(index));
1.2082 + } else {
1.2083 + __ dsll(AT, as_Register(index), scale);
1.2084 + __ addu(AT, as_Register(base), AT);
1.2085 + }
1.2086 + __ sh(as_Register(src), AT, disp);
1.2087 + }
1.2088 + } else {
1.2089 + if (scale == 0) {
1.2090 + __ addu(AT, as_Register(base), as_Register(index));
1.2091 + } else {
1.2092 + __ dsll(AT, as_Register(index), scale);
1.2093 + __ addu(AT, as_Register(base), AT);
1.2094 + }
1.2095 + __ move(T9, disp);
1.2096 + if( UseLoongsonISA ) {
1.2097 + __ gsshx(as_Register(src), AT, T9, 0);
1.2098 + } else {
1.2099 + __ addu(AT, AT, T9);
1.2100 + __ sh(as_Register(src), AT, 0);
1.2101 + }
1.2102 + }
1.2103 + } else {
1.2104 + if( Assembler::is_simm16(disp) ) {
1.2105 + __ sh(as_Register(src), as_Register(base), disp);
1.2106 + } else {
1.2107 + __ move(T9, disp);
1.2108 + if( UseLoongsonISA ) {
1.2109 + __ gsshx(as_Register(src), as_Register(base), T9, 0);
1.2110 + } else {
1.2111 + __ addu(AT, as_Register(base), T9);
1.2112 + __ sh(as_Register(src), AT, 0);
1.2113 + }
1.2114 + }
1.2115 + }
1.2116 %}
1.2117
1.2118 enc_class store_C0_enc (memory mem) %{
1.2119 - MacroAssembler _masm(&cbuf);
1.2120 - int base = $mem$$base;
1.2121 - int index = $mem$$index;
1.2122 - int scale = $mem$$scale;
1.2123 - int disp = $mem$$disp;
1.2124 -
1.2125 - if( index != 0 ) {
1.2126 - if( Assembler::is_simm16(disp) ) {
1.2127 - if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
1.2128 - if (scale == 0) {
1.2129 - __ gsshx(R0, as_Register(base), as_Register(index), disp);
1.2130 - } else {
1.2131 - __ dsll(AT, as_Register(index), scale);
1.2132 - __ gsshx(R0, as_Register(base), AT, disp);
1.2133 - }
1.2134 - } else {
1.2135 - if (scale == 0) {
1.2136 - __ addu(AT, as_Register(base), as_Register(index));
1.2137 - } else {
1.2138 - __ dsll(AT, as_Register(index), scale);
1.2139 - __ addu(AT, as_Register(base), AT);
1.2140 - }
1.2141 - __ sh(R0, AT, disp);
1.2142 - }
1.2143 - } else {
1.2144 - if (scale == 0) {
1.2145 - __ addu(AT, as_Register(base), as_Register(index));
1.2146 - } else {
1.2147 - __ dsll(AT, as_Register(index), scale);
1.2148 - __ addu(AT, as_Register(base), AT);
1.2149 - }
1.2150 - __ move(T9, disp);
1.2151 - if( UseLoongsonISA ) {
1.2152 - __ gsshx(R0, AT, T9, 0);
1.2153 - } else {
1.2154 - __ addu(AT, AT, T9);
1.2155 - __ sh(R0, AT, 0);
1.2156 - }
1.2157 - }
1.2158 - } else {
1.2159 - if( Assembler::is_simm16(disp) ) {
1.2160 - __ sh(R0, as_Register(base), disp);
1.2161 - } else {
1.2162 - __ move(T9, disp);
1.2163 - if( UseLoongsonISA ) {
1.2164 - __ gsshx(R0, as_Register(base), T9, 0);
1.2165 - } else {
1.2166 - __ addu(AT, as_Register(base), T9);
1.2167 - __ sh(R0, AT, 0);
1.2168 - }
1.2169 - }
1.2170 - }
1.2171 + MacroAssembler _masm(&cbuf);
1.2172 + int base = $mem$$base;
1.2173 + int index = $mem$$index;
1.2174 + int scale = $mem$$scale;
1.2175 + int disp = $mem$$disp;
1.2176 +
1.2177 + if( index != 0 ) {
1.2178 + if( Assembler::is_simm16(disp) ) {
1.2179 + if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
1.2180 + if (scale == 0) {
1.2181 + __ gsshx(R0, as_Register(base), as_Register(index), disp);
1.2182 + } else {
1.2183 + __ dsll(AT, as_Register(index), scale);
1.2184 + __ gsshx(R0, as_Register(base), AT, disp);
1.2185 + }
1.2186 + } else {
1.2187 + if (scale == 0) {
1.2188 + __ addu(AT, as_Register(base), as_Register(index));
1.2189 + } else {
1.2190 + __ dsll(AT, as_Register(index), scale);
1.2191 + __ addu(AT, as_Register(base), AT);
1.2192 + }
1.2193 + __ sh(R0, AT, disp);
1.2194 + }
1.2195 + } else {
1.2196 + if (scale == 0) {
1.2197 + __ addu(AT, as_Register(base), as_Register(index));
1.2198 + } else {
1.2199 + __ dsll(AT, as_Register(index), scale);
1.2200 + __ addu(AT, as_Register(base), AT);
1.2201 + }
1.2202 + __ move(T9, disp);
1.2203 + if( UseLoongsonISA ) {
1.2204 + __ gsshx(R0, AT, T9, 0);
1.2205 + } else {
1.2206 + __ addu(AT, AT, T9);
1.2207 + __ sh(R0, AT, 0);
1.2208 + }
1.2209 + }
1.2210 + } else {
1.2211 + if( Assembler::is_simm16(disp) ) {
1.2212 + __ sh(R0, as_Register(base), disp);
1.2213 + } else {
1.2214 + __ move(T9, disp);
1.2215 + if( UseLoongsonISA ) {
1.2216 + __ gsshx(R0, as_Register(base), T9, 0);
1.2217 + } else {
1.2218 + __ addu(AT, as_Register(base), T9);
1.2219 + __ sh(R0, AT, 0);
1.2220 + }
1.2221 + }
1.2222 + }
1.2223 %}
1.2224
1.2225 enc_class load_I_enc (mRegI dst, memory mem) %{
1.2226 - MacroAssembler _masm(&cbuf);
1.2227 - int dst = $dst$$reg;
1.2228 - int base = $mem$$base;
1.2229 - int index = $mem$$index;
1.2230 - int scale = $mem$$scale;
1.2231 - int disp = $mem$$disp;
1.2232 -
1.2233 - if( index != 0 ) {
1.2234 - if( Assembler::is_simm16(disp) ) {
1.2235 - if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
1.2236 - if (scale == 0) {
1.2237 - __ gslwx(as_Register(dst), as_Register(base), as_Register(index), disp);
1.2238 - } else {
1.2239 - __ dsll(AT, as_Register(index), scale);
1.2240 - __ gslwx(as_Register(dst), as_Register(base), AT, disp);
1.2241 - }
1.2242 - } else {
1.2243 - if (scale == 0) {
1.2244 - __ addu(AT, as_Register(base), as_Register(index));
1.2245 - } else {
1.2246 - __ dsll(AT, as_Register(index), scale);
1.2247 - __ addu(AT, as_Register(base), AT);
1.2248 - }
1.2249 - __ lw(as_Register(dst), AT, disp);
1.2250 - }
1.2251 - } else {
1.2252 - if (scale == 0) {
1.2253 - __ addu(AT, as_Register(base), as_Register(index));
1.2254 - } else {
1.2255 - __ dsll(AT, as_Register(index), scale);
1.2256 - __ addu(AT, as_Register(base), AT);
1.2257 - }
1.2258 - __ move(T9, disp);
1.2259 - if( UseLoongsonISA ) {
1.2260 - __ gslwx(as_Register(dst), AT, T9, 0);
1.2261 - } else {
1.2262 - __ addu(AT, AT, T9);
1.2263 - __ lw(as_Register(dst), AT, 0);
1.2264 - }
1.2265 - }
1.2266 - } else {
1.2267 - if( Assembler::is_simm16(disp) ) {
1.2268 - __ lw(as_Register(dst), as_Register(base), disp);
1.2269 - } else {
1.2270 - __ move(T9, disp);
1.2271 - if( UseLoongsonISA ) {
1.2272 - __ gslwx(as_Register(dst), as_Register(base), T9, 0);
1.2273 - } else {
1.2274 - __ addu(AT, as_Register(base), T9);
1.2275 - __ lw(as_Register(dst), AT, 0);
1.2276 - }
1.2277 - }
1.2278 - }
1.2279 + MacroAssembler _masm(&cbuf);
1.2280 + int dst = $dst$$reg;
1.2281 + int base = $mem$$base;
1.2282 + int index = $mem$$index;
1.2283 + int scale = $mem$$scale;
1.2284 + int disp = $mem$$disp;
1.2285 +
1.2286 + if( index != 0 ) {
1.2287 + if( Assembler::is_simm16(disp) ) {
1.2288 + if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
1.2289 + if (scale == 0) {
1.2290 + __ gslwx(as_Register(dst), as_Register(base), as_Register(index), disp);
1.2291 + } else {
1.2292 + __ dsll(AT, as_Register(index), scale);
1.2293 + __ gslwx(as_Register(dst), as_Register(base), AT, disp);
1.2294 + }
1.2295 + } else {
1.2296 + if (scale == 0) {
1.2297 + __ addu(AT, as_Register(base), as_Register(index));
1.2298 + } else {
1.2299 + __ dsll(AT, as_Register(index), scale);
1.2300 + __ addu(AT, as_Register(base), AT);
1.2301 + }
1.2302 + __ lw(as_Register(dst), AT, disp);
1.2303 + }
1.2304 + } else {
1.2305 + if (scale == 0) {
1.2306 + __ addu(AT, as_Register(base), as_Register(index));
1.2307 + } else {
1.2308 + __ dsll(AT, as_Register(index), scale);
1.2309 + __ addu(AT, as_Register(base), AT);
1.2310 + }
1.2311 + __ move(T9, disp);
1.2312 + if( UseLoongsonISA ) {
1.2313 + __ gslwx(as_Register(dst), AT, T9, 0);
1.2314 + } else {
1.2315 + __ addu(AT, AT, T9);
1.2316 + __ lw(as_Register(dst), AT, 0);
1.2317 + }
1.2318 + }
1.2319 + } else {
1.2320 + if( Assembler::is_simm16(disp) ) {
1.2321 + __ lw(as_Register(dst), as_Register(base), disp);
1.2322 + } else {
1.2323 + __ move(T9, disp);
1.2324 + if( UseLoongsonISA ) {
1.2325 + __ gslwx(as_Register(dst), as_Register(base), T9, 0);
1.2326 + } else {
1.2327 + __ addu(AT, as_Register(base), T9);
1.2328 + __ lw(as_Register(dst), AT, 0);
1.2329 + }
1.2330 + }
1.2331 + }
1.2332 %}
1.2333
1.2334 enc_class store_I_reg_enc (memory mem, mRegI src) %{
1.2335 - MacroAssembler _masm(&cbuf);
1.2336 - int src = $src$$reg;
1.2337 - int base = $mem$$base;
1.2338 - int index = $mem$$index;
1.2339 - int scale = $mem$$scale;
1.2340 - int disp = $mem$$disp;
1.2341 -
1.2342 - if( index != 0 ) {
1.2343 - if( Assembler::is_simm16(disp) ) {
1.2344 - if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
1.2345 - if (scale == 0) {
1.2346 - __ gsswx(as_Register(src), as_Register(base), as_Register(index), disp);
1.2347 - } else {
1.2348 - __ dsll(AT, as_Register(index), scale);
1.2349 - __ gsswx(as_Register(src), as_Register(base), AT, disp);
1.2350 - }
1.2351 - } else {
1.2352 - if (scale == 0) {
1.2353 - __ addu(AT, as_Register(base), as_Register(index));
1.2354 - } else {
1.2355 - __ dsll(AT, as_Register(index), scale);
1.2356 - __ addu(AT, as_Register(base), AT);
1.2357 - }
1.2358 - __ sw(as_Register(src), AT, disp);
1.2359 - }
1.2360 - } else {
1.2361 - if (scale == 0) {
1.2362 - __ addu(AT, as_Register(base), as_Register(index));
1.2363 - } else {
1.2364 - __ dsll(AT, as_Register(index), scale);
1.2365 - __ addu(AT, as_Register(base), AT);
1.2366 - }
1.2367 - __ move(T9, disp);
1.2368 - if( UseLoongsonISA ) {
1.2369 - __ gsswx(as_Register(src), AT, T9, 0);
1.2370 - } else {
1.2371 - __ addu(AT, AT, T9);
1.2372 - __ sw(as_Register(src), AT, 0);
1.2373 - }
1.2374 - }
1.2375 - } else {
1.2376 - if( Assembler::is_simm16(disp) ) {
1.2377 - __ sw(as_Register(src), as_Register(base), disp);
1.2378 - } else {
1.2379 - __ move(T9, disp);
1.2380 - if( UseLoongsonISA ) {
1.2381 - __ gsswx(as_Register(src), as_Register(base), T9, 0);
1.2382 - } else {
1.2383 - __ addu(AT, as_Register(base), T9);
1.2384 - __ sw(as_Register(src), AT, 0);
1.2385 - }
1.2386 - }
1.2387 - }
1.2388 + MacroAssembler _masm(&cbuf);
1.2389 + int src = $src$$reg;
1.2390 + int base = $mem$$base;
1.2391 + int index = $mem$$index;
1.2392 + int scale = $mem$$scale;
1.2393 + int disp = $mem$$disp;
1.2394 +
1.2395 + if( index != 0 ) {
1.2396 + if( Assembler::is_simm16(disp) ) {
1.2397 + if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
1.2398 + if (scale == 0) {
1.2399 + __ gsswx(as_Register(src), as_Register(base), as_Register(index), disp);
1.2400 + } else {
1.2401 + __ dsll(AT, as_Register(index), scale);
1.2402 + __ gsswx(as_Register(src), as_Register(base), AT, disp);
1.2403 + }
1.2404 + } else {
1.2405 + if (scale == 0) {
1.2406 + __ addu(AT, as_Register(base), as_Register(index));
1.2407 + } else {
1.2408 + __ dsll(AT, as_Register(index), scale);
1.2409 + __ addu(AT, as_Register(base), AT);
1.2410 + }
1.2411 + __ sw(as_Register(src), AT, disp);
1.2412 + }
1.2413 + } else {
1.2414 + if (scale == 0) {
1.2415 + __ addu(AT, as_Register(base), as_Register(index));
1.2416 + } else {
1.2417 + __ dsll(AT, as_Register(index), scale);
1.2418 + __ addu(AT, as_Register(base), AT);
1.2419 + }
1.2420 + __ move(T9, disp);
1.2421 + if( UseLoongsonISA ) {
1.2422 + __ gsswx(as_Register(src), AT, T9, 0);
1.2423 + } else {
1.2424 + __ addu(AT, AT, T9);
1.2425 + __ sw(as_Register(src), AT, 0);
1.2426 + }
1.2427 + }
1.2428 + } else {
1.2429 + if( Assembler::is_simm16(disp) ) {
1.2430 + __ sw(as_Register(src), as_Register(base), disp);
1.2431 + } else {
1.2432 + __ move(T9, disp);
1.2433 + if( UseLoongsonISA ) {
1.2434 + __ gsswx(as_Register(src), as_Register(base), T9, 0);
1.2435 + } else {
1.2436 + __ addu(AT, as_Register(base), T9);
1.2437 + __ sw(as_Register(src), AT, 0);
1.2438 + }
1.2439 + }
1.2440 + }
1.2441 %}
1.2442
1.2443 enc_class store_I_immI_enc (memory mem, immI src) %{
1.2444 - MacroAssembler _masm(&cbuf);
1.2445 - int base = $mem$$base;
1.2446 - int index = $mem$$index;
1.2447 - int scale = $mem$$scale;
1.2448 - int disp = $mem$$disp;
1.2449 - int value = $src$$constant;
1.2450 -
1.2451 - if( index != 0 ) {
1.2452 - if ( UseLoongsonISA ) {
1.2453 - if ( Assembler::is_simm(disp, 8) ) {
1.2454 - if ( scale == 0 ) {
1.2455 - if ( value == 0 ) {
1.2456 - __ gsswx(R0, as_Register(base), as_Register(index), disp);
1.2457 - } else {
1.2458 - __ move(T9, value);
1.2459 - __ gsswx(T9, as_Register(base), as_Register(index), disp);
1.2460 - }
1.2461 - } else {
1.2462 - __ dsll(AT, as_Register(index), scale);
1.2463 - if ( value == 0 ) {
1.2464 - __ gsswx(R0, as_Register(base), AT, disp);
1.2465 - } else {
1.2466 - __ move(T9, value);
1.2467 - __ gsswx(T9, as_Register(base), AT, disp);
1.2468 - }
1.2469 - }
1.2470 - } else if ( Assembler::is_simm16(disp) ) {
1.2471 - if ( scale == 0 ) {
1.2472 - __ daddu(AT, as_Register(base), as_Register(index));
1.2473 - if ( value == 0 ) {
1.2474 - __ sw(R0, AT, disp);
1.2475 - } else {
1.2476 - __ move(T9, value);
1.2477 - __ sw(T9, AT, disp);
1.2478 - }
1.2479 - } else {
1.2480 - __ dsll(AT, as_Register(index), scale);
1.2481 - __ daddu(AT, as_Register(base), AT);
1.2482 - if ( value == 0 ) {
1.2483 - __ sw(R0, AT, disp);
1.2484 - } else {
1.2485 - __ move(T9, value);
1.2486 - __ sw(T9, AT, disp);
1.2487 - }
1.2488 - }
1.2489 - } else {
1.2490 - if ( scale == 0 ) {
1.2491 - __ move(T9, disp);
1.2492 - __ daddu(AT, as_Register(index), T9);
1.2493 - if ( value ==0 ) {
1.2494 - __ gsswx(R0, as_Register(base), AT, 0);
1.2495 - } else {
1.2496 - __ move(T9, value);
1.2497 - __ gsswx(T9, as_Register(base), AT, 0);
1.2498 - }
1.2499 - } else {
1.2500 - __ dsll(AT, as_Register(index), scale);
1.2501 - __ move(T9, disp);
1.2502 - __ daddu(AT, AT, T9);
1.2503 - if ( value == 0 ) {
1.2504 - __ gsswx(R0, as_Register(base), AT, 0);
1.2505 - } else {
1.2506 - __ move(T9, value);
1.2507 - __ gsswx(T9, as_Register(base), AT, 0);
1.2508 - }
1.2509 - }
1.2510 - }
1.2511 - } else { //not use loongson isa
1.2512 - if (scale == 0) {
1.2513 - __ daddu(AT, as_Register(base), as_Register(index));
1.2514 - } else {
1.2515 - __ dsll(AT, as_Register(index), scale);
1.2516 - __ daddu(AT, as_Register(base), AT);
1.2517 - }
1.2518 - if( Assembler::is_simm16(disp) ) {
1.2519 - if (value == 0) {
1.2520 - __ sw(R0, AT, disp);
1.2521 - } else {
1.2522 - __ move(T9, value);
1.2523 - __ sw(T9, AT, disp);
1.2524 - }
1.2525 - } else {
1.2526 - if (value == 0) {
1.2527 - __ move(T9, disp);
1.2528 - __ daddu(AT, AT, T9);
1.2529 - __ sw(R0, AT, 0);
1.2530 - } else {
1.2531 - __ move(T9, disp);
1.2532 - __ daddu(AT, AT, T9);
1.2533 - __ move(T9, value);
1.2534 - __ sw(T9, AT, 0);
1.2535 - }
1.2536 - }
1.2537 - }
1.2538 - } else {
1.2539 - if ( UseLoongsonISA ) {
1.2540 - if ( Assembler::is_simm16(disp) ) {
1.2541 - if ( value == 0 ) {
1.2542 - __ sw(R0, as_Register(base), disp);
1.2543 - } else {
1.2544 - __ move(AT, value);
1.2545 - __ sw(AT, as_Register(base), disp);
1.2546 - }
1.2547 - } else {
1.2548 - __ move(T9, disp);
1.2549 - if ( value == 0 ) {
1.2550 - __ gsswx(R0, as_Register(base), T9, 0);
1.2551 - } else {
1.2552 - __ move(AT, value);
1.2553 - __ gsswx(AT, as_Register(base), T9, 0);
1.2554 - }
1.2555 - }
1.2556 - } else {
1.2557 - if( Assembler::is_simm16(disp) ) {
1.2558 - if (value == 0) {
1.2559 - __ sw(R0, as_Register(base), disp);
1.2560 - } else {
1.2561 - __ move(AT, value);
1.2562 - __ sw(AT, as_Register(base), disp);
1.2563 - }
1.2564 - } else {
1.2565 - if (value == 0) {
1.2566 - __ move(T9, disp);
1.2567 - __ daddu(AT, as_Register(base), T9);
1.2568 - __ sw(R0, AT, 0);
1.2569 - } else {
1.2570 - __ move(T9, disp);
1.2571 - __ daddu(AT, as_Register(base), T9);
1.2572 - __ move(T9, value);
1.2573 - __ sw(T9, AT, 0);
1.2574 - }
1.2575 - }
1.2576 - }
1.2577 - }
1.2578 + MacroAssembler _masm(&cbuf);
1.2579 + int base = $mem$$base;
1.2580 + int index = $mem$$index;
1.2581 + int scale = $mem$$scale;
1.2582 + int disp = $mem$$disp;
1.2583 + int value = $src$$constant;
1.2584 +
1.2585 + if( index != 0 ) {
1.2586 + if ( UseLoongsonISA ) {
1.2587 + if ( Assembler::is_simm(disp, 8) ) {
1.2588 + if ( scale == 0 ) {
1.2589 + if ( value == 0 ) {
1.2590 + __ gsswx(R0, as_Register(base), as_Register(index), disp);
1.2591 + } else {
1.2592 + __ move(T9, value);
1.2593 + __ gsswx(T9, as_Register(base), as_Register(index), disp);
1.2594 + }
1.2595 + } else {
1.2596 + __ dsll(AT, as_Register(index), scale);
1.2597 + if ( value == 0 ) {
1.2598 + __ gsswx(R0, as_Register(base), AT, disp);
1.2599 + } else {
1.2600 + __ move(T9, value);
1.2601 + __ gsswx(T9, as_Register(base), AT, disp);
1.2602 + }
1.2603 + }
1.2604 + } else if ( Assembler::is_simm16(disp) ) {
1.2605 + if ( scale == 0 ) {
1.2606 + __ daddu(AT, as_Register(base), as_Register(index));
1.2607 + if ( value == 0 ) {
1.2608 + __ sw(R0, AT, disp);
1.2609 + } else {
1.2610 + __ move(T9, value);
1.2611 + __ sw(T9, AT, disp);
1.2612 + }
1.2613 + } else {
1.2614 + __ dsll(AT, as_Register(index), scale);
1.2615 + __ daddu(AT, as_Register(base), AT);
1.2616 + if ( value == 0 ) {
1.2617 + __ sw(R0, AT, disp);
1.2618 + } else {
1.2619 + __ move(T9, value);
1.2620 + __ sw(T9, AT, disp);
1.2621 + }
1.2622 + }
1.2623 + } else {
1.2624 + if ( scale == 0 ) {
1.2625 + __ move(T9, disp);
1.2626 + __ daddu(AT, as_Register(index), T9);
1.2627 + if ( value ==0 ) {
1.2628 + __ gsswx(R0, as_Register(base), AT, 0);
1.2629 + } else {
1.2630 + __ move(T9, value);
1.2631 + __ gsswx(T9, as_Register(base), AT, 0);
1.2632 + }
1.2633 + } else {
1.2634 + __ dsll(AT, as_Register(index), scale);
1.2635 + __ move(T9, disp);
1.2636 + __ daddu(AT, AT, T9);
1.2637 + if ( value == 0 ) {
1.2638 + __ gsswx(R0, as_Register(base), AT, 0);
1.2639 + } else {
1.2640 + __ move(T9, value);
1.2641 + __ gsswx(T9, as_Register(base), AT, 0);
1.2642 + }
1.2643 + }
1.2644 + }
1.2645 + } else { //not use loongson isa
1.2646 + if (scale == 0) {
1.2647 + __ daddu(AT, as_Register(base), as_Register(index));
1.2648 + } else {
1.2649 + __ dsll(AT, as_Register(index), scale);
1.2650 + __ daddu(AT, as_Register(base), AT);
1.2651 + }
1.2652 + if( Assembler::is_simm16(disp) ) {
1.2653 + if (value == 0) {
1.2654 + __ sw(R0, AT, disp);
1.2655 + } else {
1.2656 + __ move(T9, value);
1.2657 + __ sw(T9, AT, disp);
1.2658 + }
1.2659 + } else {
1.2660 + if (value == 0) {
1.2661 + __ move(T9, disp);
1.2662 + __ daddu(AT, AT, T9);
1.2663 + __ sw(R0, AT, 0);
1.2664 + } else {
1.2665 + __ move(T9, disp);
1.2666 + __ daddu(AT, AT, T9);
1.2667 + __ move(T9, value);
1.2668 + __ sw(T9, AT, 0);
1.2669 + }
1.2670 + }
1.2671 + }
1.2672 + } else {
1.2673 + if ( UseLoongsonISA ) {
1.2674 + if ( Assembler::is_simm16(disp) ) {
1.2675 + if ( value == 0 ) {
1.2676 + __ sw(R0, as_Register(base), disp);
1.2677 + } else {
1.2678 + __ move(AT, value);
1.2679 + __ sw(AT, as_Register(base), disp);
1.2680 + }
1.2681 + } else {
1.2682 + __ move(T9, disp);
1.2683 + if ( value == 0 ) {
1.2684 + __ gsswx(R0, as_Register(base), T9, 0);
1.2685 + } else {
1.2686 + __ move(AT, value);
1.2687 + __ gsswx(AT, as_Register(base), T9, 0);
1.2688 + }
1.2689 + }
1.2690 + } else {
1.2691 + if( Assembler::is_simm16(disp) ) {
1.2692 + if (value == 0) {
1.2693 + __ sw(R0, as_Register(base), disp);
1.2694 + } else {
1.2695 + __ move(AT, value);
1.2696 + __ sw(AT, as_Register(base), disp);
1.2697 + }
1.2698 + } else {
1.2699 + if (value == 0) {
1.2700 + __ move(T9, disp);
1.2701 + __ daddu(AT, as_Register(base), T9);
1.2702 + __ sw(R0, AT, 0);
1.2703 + } else {
1.2704 + __ move(T9, disp);
1.2705 + __ daddu(AT, as_Register(base), T9);
1.2706 + __ move(T9, value);
1.2707 + __ sw(T9, AT, 0);
1.2708 + }
1.2709 + }
1.2710 + }
1.2711 + }
1.2712 %}
1.2713
1.2714 enc_class load_N_enc (mRegN dst, memory mem) %{
1.2715 - MacroAssembler _masm(&cbuf);
1.2716 - int dst = $dst$$reg;
1.2717 - int base = $mem$$base;
1.2718 - int index = $mem$$index;
1.2719 - int scale = $mem$$scale;
1.2720 - int disp = $mem$$disp;
1.2721 - relocInfo::relocType disp_reloc = $mem->disp_reloc();
1.2722 - assert(disp_reloc == relocInfo::none, "cannot have disp");
1.2723 -
1.2724 - if( index != 0 ) {
1.2725 + MacroAssembler _masm(&cbuf);
1.2726 + int dst = $dst$$reg;
1.2727 + int base = $mem$$base;
1.2728 + int index = $mem$$index;
1.2729 + int scale = $mem$$scale;
1.2730 + int disp = $mem$$disp;
1.2731 + relocInfo::relocType disp_reloc = $mem->disp_reloc();
1.2732 + assert(disp_reloc == relocInfo::none, "cannot have disp");
1.2733 +
1.2734 + if( index != 0 ) {
1.2735 + if (scale == 0) {
1.2736 + __ daddu(AT, as_Register(base), as_Register(index));
1.2737 + } else {
1.2738 + __ dsll(AT, as_Register(index), scale);
1.2739 + __ daddu(AT, as_Register(base), AT);
1.2740 + }
1.2741 + if( Assembler::is_simm16(disp) ) {
1.2742 + __ lwu(as_Register(dst), AT, disp);
1.2743 + } else {
1.2744 + __ set64(T9, disp);
1.2745 + __ daddu(AT, AT, T9);
1.2746 + __ lwu(as_Register(dst), AT, 0);
1.2747 + }
1.2748 + } else {
1.2749 + if( Assembler::is_simm16(disp) ) {
1.2750 + __ lwu(as_Register(dst), as_Register(base), disp);
1.2751 + } else {
1.2752 + __ set64(T9, disp);
1.2753 + __ daddu(AT, as_Register(base), T9);
1.2754 + __ lwu(as_Register(dst), AT, 0);
1.2755 + }
1.2756 + }
1.2757 + %}
1.2758 +
1.2759 +
1.2760 + enc_class load_P_enc (mRegP dst, memory mem) %{
1.2761 + MacroAssembler _masm(&cbuf);
1.2762 + int dst = $dst$$reg;
1.2763 + int base = $mem$$base;
1.2764 + int index = $mem$$index;
1.2765 + int scale = $mem$$scale;
1.2766 + int disp = $mem$$disp;
1.2767 + relocInfo::relocType disp_reloc = $mem->disp_reloc();
1.2768 + assert(disp_reloc == relocInfo::none, "cannot have disp");
1.2769 +
1.2770 + if( index != 0 ) {
1.2771 + if ( UseLoongsonISA ) {
1.2772 + if ( Assembler::is_simm(disp, 8) ) {
1.2773 + if ( scale != 0 ) {
1.2774 + __ dsll(AT, as_Register(index), scale);
1.2775 + __ gsldx(as_Register(dst), as_Register(base), AT, disp);
1.2776 + } else {
1.2777 + __ gsldx(as_Register(dst), as_Register(base), as_Register(index), disp);
1.2778 + }
1.2779 + } else if ( Assembler::is_simm16(disp) ){
1.2780 + if ( scale != 0 ) {
1.2781 + __ dsll(AT, as_Register(index), scale);
1.2782 + __ daddu(AT, AT, as_Register(base));
1.2783 + } else {
1.2784 + __ daddu(AT, as_Register(index), as_Register(base));
1.2785 + }
1.2786 + __ ld(as_Register(dst), AT, disp);
1.2787 + } else {
1.2788 + if ( scale != 0 ) {
1.2789 + __ dsll(AT, as_Register(index), scale);
1.2790 + __ move(T9, disp);
1.2791 + __ daddu(AT, AT, T9);
1.2792 + } else {
1.2793 + __ move(T9, disp);
1.2794 + __ daddu(AT, as_Register(index), T9);
1.2795 + }
1.2796 + __ gsldx(as_Register(dst), as_Register(base), AT, 0);
1.2797 + }
1.2798 + } else { //not use loongson isa
1.2799 if (scale == 0) {
1.2800 - __ daddu(AT, as_Register(base), as_Register(index));
1.2801 - } else {
1.2802 - __ dsll(AT, as_Register(index), scale);
1.2803 - __ daddu(AT, as_Register(base), AT);
1.2804 - }
1.2805 - if( Assembler::is_simm16(disp) ) {
1.2806 - __ lwu(as_Register(dst), AT, disp);
1.2807 - } else {
1.2808 - __ set64(T9, disp);
1.2809 - __ daddu(AT, AT, T9);
1.2810 - __ lwu(as_Register(dst), AT, 0);
1.2811 - }
1.2812 - } else {
1.2813 - if( Assembler::is_simm16(disp) ) {
1.2814 - __ lwu(as_Register(dst), as_Register(base), disp);
1.2815 - } else {
1.2816 - __ set64(T9, disp);
1.2817 - __ daddu(AT, as_Register(base), T9);
1.2818 - __ lwu(as_Register(dst), AT, 0);
1.2819 - }
1.2820 - }
1.2821 -
1.2822 - %}
1.2823 -
1.2824 -
1.2825 - enc_class load_P_enc (mRegP dst, memory mem) %{
1.2826 - MacroAssembler _masm(&cbuf);
1.2827 - int dst = $dst$$reg;
1.2828 - int base = $mem$$base;
1.2829 - int index = $mem$$index;
1.2830 - int scale = $mem$$scale;
1.2831 - int disp = $mem$$disp;
1.2832 - relocInfo::relocType disp_reloc = $mem->disp_reloc();
1.2833 - assert(disp_reloc == relocInfo::none, "cannot have disp");
1.2834 -
1.2835 - if( index != 0 ) {
1.2836 - if ( UseLoongsonISA ) {
1.2837 - if ( Assembler::is_simm(disp, 8) ) {
1.2838 - if ( scale != 0 ) {
1.2839 - __ dsll(AT, as_Register(index), scale);
1.2840 - __ gsldx(as_Register(dst), as_Register(base), AT, disp);
1.2841 - } else {
1.2842 - __ gsldx(as_Register(dst), as_Register(base), as_Register(index), disp);
1.2843 - }
1.2844 - } else if ( Assembler::is_simm16(disp) ){
1.2845 - if ( scale != 0 ) {
1.2846 - __ dsll(AT, as_Register(index), scale);
1.2847 - __ daddu(AT, AT, as_Register(base));
1.2848 - } else {
1.2849 - __ daddu(AT, as_Register(index), as_Register(base));
1.2850 - }
1.2851 - __ ld(as_Register(dst), AT, disp);
1.2852 - } else {
1.2853 - if ( scale != 0 ) {
1.2854 - __ dsll(AT, as_Register(index), scale);
1.2855 - __ move(T9, disp);
1.2856 - __ daddu(AT, AT, T9);
1.2857 - } else {
1.2858 - __ move(T9, disp);
1.2859 - __ daddu(AT, as_Register(index), T9);
1.2860 - }
1.2861 - __ gsldx(as_Register(dst), as_Register(base), AT, 0);
1.2862 - }
1.2863 - } else { //not use loongson isa
1.2864 - if (scale == 0) {
1.2865 - __ daddu(AT, as_Register(base), as_Register(index));
1.2866 - } else {
1.2867 - __ dsll(AT, as_Register(index), scale);
1.2868 - __ daddu(AT, as_Register(base), AT);
1.2869 - }
1.2870 - if( Assembler::is_simm16(disp) ) {
1.2871 - __ ld(as_Register(dst), AT, disp);
1.2872 - } else {
1.2873 - __ set64(T9, disp);
1.2874 - __ daddu(AT, AT, T9);
1.2875 - __ ld(as_Register(dst), AT, 0);
1.2876 - }
1.2877 - }
1.2878 - } else {
1.2879 - if ( UseLoongsonISA ) {
1.2880 - if ( Assembler::is_simm16(disp) ){
1.2881 - __ ld(as_Register(dst), as_Register(base), disp);
1.2882 - } else {
1.2883 - __ set64(T9, disp);
1.2884 - __ gsldx(as_Register(dst), as_Register(base), T9, 0);
1.2885 - }
1.2886 - } else { //not use loongson isa
1.2887 - if( Assembler::is_simm16(disp) ) {
1.2888 - __ ld(as_Register(dst), as_Register(base), disp);
1.2889 - } else {
1.2890 - __ set64(T9, disp);
1.2891 - __ daddu(AT, as_Register(base), T9);
1.2892 - __ ld(as_Register(dst), AT, 0);
1.2893 - }
1.2894 - }
1.2895 - }
1.2896 -// if( disp_reloc != relocInfo::none) __ ld(as_Register(dst), as_Register(dst), 0);
1.2897 + __ daddu(AT, as_Register(base), as_Register(index));
1.2898 + } else {
1.2899 + __ dsll(AT, as_Register(index), scale);
1.2900 + __ daddu(AT, as_Register(base), AT);
1.2901 + }
1.2902 + if( Assembler::is_simm16(disp) ) {
1.2903 + __ ld(as_Register(dst), AT, disp);
1.2904 + } else {
1.2905 + __ set64(T9, disp);
1.2906 + __ daddu(AT, AT, T9);
1.2907 + __ ld(as_Register(dst), AT, 0);
1.2908 + }
1.2909 + }
1.2910 + } else {
1.2911 + if ( UseLoongsonISA ) {
1.2912 + if ( Assembler::is_simm16(disp) ){
1.2913 + __ ld(as_Register(dst), as_Register(base), disp);
1.2914 + } else {
1.2915 + __ set64(T9, disp);
1.2916 + __ gsldx(as_Register(dst), as_Register(base), T9, 0);
1.2917 + }
1.2918 + } else { //not use loongson isa
1.2919 + if( Assembler::is_simm16(disp) ) {
1.2920 + __ ld(as_Register(dst), as_Register(base), disp);
1.2921 + } else {
1.2922 + __ set64(T9, disp);
1.2923 + __ daddu(AT, as_Register(base), T9);
1.2924 + __ ld(as_Register(dst), AT, 0);
1.2925 + }
1.2926 + }
1.2927 + }
1.2928 %}
1.2929
1.2930 enc_class store_P_reg_enc (memory mem, mRegP src) %{
1.2931 - MacroAssembler _masm(&cbuf);
1.2932 - int src = $src$$reg;
1.2933 - int base = $mem$$base;
1.2934 - int index = $mem$$index;
1.2935 - int scale = $mem$$scale;
1.2936 - int disp = $mem$$disp;
1.2937 -
1.2938 - if( index != 0 ) {
1.2939 - if ( UseLoongsonISA ){
1.2940 - if ( Assembler::is_simm(disp, 8) ) {
1.2941 - if ( scale == 0 ) {
1.2942 - __ gssdx(as_Register(src), as_Register(base), as_Register(index), disp);
1.2943 - } else {
1.2944 - __ dsll(AT, as_Register(index), scale);
1.2945 - __ gssdx(as_Register(src), as_Register(base), AT, disp);
1.2946 - }
1.2947 - } else if ( Assembler::is_simm16(disp) ) {
1.2948 - if ( scale == 0 ) {
1.2949 - __ daddu(AT, as_Register(base), as_Register(index));
1.2950 - } else {
1.2951 - __ dsll(AT, as_Register(index), scale);
1.2952 - __ daddu(AT, as_Register(base), AT);
1.2953 - }
1.2954 - __ sd(as_Register(src), AT, disp);
1.2955 - } else {
1.2956 - if ( scale == 0 ) {
1.2957 - __ move(T9, disp);
1.2958 - __ daddu(AT, as_Register(index), T9);
1.2959 - } else {
1.2960 - __ dsll(AT, as_Register(index), scale);
1.2961 - __ move(T9, disp);
1.2962 - __ daddu(AT, AT, T9);
1.2963 - }
1.2964 - __ gssdx(as_Register(src), as_Register(base), AT, 0);
1.2965 - }
1.2966 - } else { //not use loongson isa
1.2967 - if (scale == 0) {
1.2968 - __ daddu(AT, as_Register(base), as_Register(index));
1.2969 - } else {
1.2970 - __ dsll(AT, as_Register(index), scale);
1.2971 - __ daddu(AT, as_Register(base), AT);
1.2972 - }
1.2973 - if( Assembler::is_simm16(disp) ) {
1.2974 - __ sd(as_Register(src), AT, disp);
1.2975 - } else {
1.2976 - __ move(T9, disp);
1.2977 - __ daddu(AT, AT, T9);
1.2978 - __ sd(as_Register(src), AT, 0);
1.2979 - }
1.2980 - }
1.2981 - } else {
1.2982 - if ( UseLoongsonISA ) {
1.2983 - if ( Assembler::is_simm16(disp) ) {
1.2984 - __ sd(as_Register(src), as_Register(base), disp);
1.2985 - } else {
1.2986 - __ move(T9, disp);
1.2987 - __ gssdx(as_Register(src), as_Register(base), T9, 0);
1.2988 - }
1.2989 - } else {
1.2990 - if( Assembler::is_simm16(disp) ) {
1.2991 - __ sd(as_Register(src), as_Register(base), disp);
1.2992 - } else {
1.2993 - __ move(T9, disp);
1.2994 - __ daddu(AT, as_Register(base), T9);
1.2995 - __ sd(as_Register(src), AT, 0);
1.2996 - }
1.2997 - }
1.2998 - }
1.2999 + MacroAssembler _masm(&cbuf);
1.3000 + int src = $src$$reg;
1.3001 + int base = $mem$$base;
1.3002 + int index = $mem$$index;
1.3003 + int scale = $mem$$scale;
1.3004 + int disp = $mem$$disp;
1.3005 +
1.3006 + if( index != 0 ) {
1.3007 + if ( UseLoongsonISA ){
1.3008 + if ( Assembler::is_simm(disp, 8) ) {
1.3009 + if ( scale == 0 ) {
1.3010 + __ gssdx(as_Register(src), as_Register(base), as_Register(index), disp);
1.3011 + } else {
1.3012 + __ dsll(AT, as_Register(index), scale);
1.3013 + __ gssdx(as_Register(src), as_Register(base), AT, disp);
1.3014 + }
1.3015 + } else if ( Assembler::is_simm16(disp) ) {
1.3016 + if ( scale == 0 ) {
1.3017 + __ daddu(AT, as_Register(base), as_Register(index));
1.3018 + } else {
1.3019 + __ dsll(AT, as_Register(index), scale);
1.3020 + __ daddu(AT, as_Register(base), AT);
1.3021 + }
1.3022 + __ sd(as_Register(src), AT, disp);
1.3023 + } else {
1.3024 + if ( scale == 0 ) {
1.3025 + __ move(T9, disp);
1.3026 + __ daddu(AT, as_Register(index), T9);
1.3027 + } else {
1.3028 + __ dsll(AT, as_Register(index), scale);
1.3029 + __ move(T9, disp);
1.3030 + __ daddu(AT, AT, T9);
1.3031 + }
1.3032 + __ gssdx(as_Register(src), as_Register(base), AT, 0);
1.3033 + }
1.3034 + } else { //not use loongson isa
1.3035 + if (scale == 0) {
1.3036 + __ daddu(AT, as_Register(base), as_Register(index));
1.3037 + } else {
1.3038 + __ dsll(AT, as_Register(index), scale);
1.3039 + __ daddu(AT, as_Register(base), AT);
1.3040 + }
1.3041 + if( Assembler::is_simm16(disp) ) {
1.3042 + __ sd(as_Register(src), AT, disp);
1.3043 + } else {
1.3044 + __ move(T9, disp);
1.3045 + __ daddu(AT, AT, T9);
1.3046 + __ sd(as_Register(src), AT, 0);
1.3047 + }
1.3048 + }
1.3049 + } else {
1.3050 + if ( UseLoongsonISA ) {
1.3051 + if ( Assembler::is_simm16(disp) ) {
1.3052 + __ sd(as_Register(src), as_Register(base), disp);
1.3053 + } else {
1.3054 + __ move(T9, disp);
1.3055 + __ gssdx(as_Register(src), as_Register(base), T9, 0);
1.3056 + }
1.3057 + } else {
1.3058 + if( Assembler::is_simm16(disp) ) {
1.3059 + __ sd(as_Register(src), as_Register(base), disp);
1.3060 + } else {
1.3061 + __ move(T9, disp);
1.3062 + __ daddu(AT, as_Register(base), T9);
1.3063 + __ sd(as_Register(src), AT, 0);
1.3064 + }
1.3065 + }
1.3066 + }
1.3067 %}
1.3068
1.3069 enc_class store_N_reg_enc (memory mem, mRegN src) %{
1.3070 - MacroAssembler _masm(&cbuf);
1.3071 - int src = $src$$reg;
1.3072 - int base = $mem$$base;
1.3073 - int index = $mem$$index;
1.3074 - int scale = $mem$$scale;
1.3075 - int disp = $mem$$disp;
1.3076 -
1.3077 - if( index != 0 ) {
1.3078 - if ( UseLoongsonISA ){
1.3079 - if ( Assembler::is_simm(disp, 8) ) {
1.3080 - if ( scale == 0 ) {
1.3081 - __ gsswx(as_Register(src), as_Register(base), as_Register(index), disp);
1.3082 - } else {
1.3083 - __ dsll(AT, as_Register(index), scale);
1.3084 - __ gsswx(as_Register(src), as_Register(base), AT, disp);
1.3085 - }
1.3086 - } else if ( Assembler::is_simm16(disp) ) {
1.3087 - if ( scale == 0 ) {
1.3088 - __ daddu(AT, as_Register(base), as_Register(index));
1.3089 - } else {
1.3090 - __ dsll(AT, as_Register(index), scale);
1.3091 - __ daddu(AT, as_Register(base), AT);
1.3092 - }
1.3093 - __ sw(as_Register(src), AT, disp);
1.3094 - } else {
1.3095 - if ( scale == 0 ) {
1.3096 - __ move(T9, disp);
1.3097 - __ daddu(AT, as_Register(index), T9);
1.3098 - } else {
1.3099 - __ dsll(AT, as_Register(index), scale);
1.3100 - __ move(T9, disp);
1.3101 - __ daddu(AT, AT, T9);
1.3102 - }
1.3103 - __ gsswx(as_Register(src), as_Register(base), AT, 0);
1.3104 - }
1.3105 - } else { //not use loongson isa
1.3106 - if (scale == 0) {
1.3107 - __ daddu(AT, as_Register(base), as_Register(index));
1.3108 - } else {
1.3109 - __ dsll(AT, as_Register(index), scale);
1.3110 - __ daddu(AT, as_Register(base), AT);
1.3111 - }
1.3112 - if( Assembler::is_simm16(disp) ) {
1.3113 - __ sw(as_Register(src), AT, disp);
1.3114 - } else {
1.3115 - __ move(T9, disp);
1.3116 - __ daddu(AT, AT, T9);
1.3117 - __ sw(as_Register(src), AT, 0);
1.3118 - }
1.3119 - }
1.3120 - } else {
1.3121 - if ( UseLoongsonISA ) {
1.3122 - if ( Assembler::is_simm16(disp) ) {
1.3123 - __ sw(as_Register(src), as_Register(base), disp);
1.3124 - } else {
1.3125 - __ move(T9, disp);
1.3126 - __ gsswx(as_Register(src), as_Register(base), T9, 0);
1.3127 - }
1.3128 - } else {
1.3129 - if( Assembler::is_simm16(disp) ) {
1.3130 - __ sw(as_Register(src), as_Register(base), disp);
1.3131 - } else {
1.3132 - __ move(T9, disp);
1.3133 - __ daddu(AT, as_Register(base), T9);
1.3134 - __ sw(as_Register(src), AT, 0);
1.3135 - }
1.3136 - }
1.3137 - }
1.3138 + MacroAssembler _masm(&cbuf);
1.3139 + int src = $src$$reg;
1.3140 + int base = $mem$$base;
1.3141 + int index = $mem$$index;
1.3142 + int scale = $mem$$scale;
1.3143 + int disp = $mem$$disp;
1.3144 +
1.3145 + if( index != 0 ) {
1.3146 + if ( UseLoongsonISA ){
1.3147 + if ( Assembler::is_simm(disp, 8) ) {
1.3148 + if ( scale == 0 ) {
1.3149 + __ gsswx(as_Register(src), as_Register(base), as_Register(index), disp);
1.3150 + } else {
1.3151 + __ dsll(AT, as_Register(index), scale);
1.3152 + __ gsswx(as_Register(src), as_Register(base), AT, disp);
1.3153 + }
1.3154 + } else if ( Assembler::is_simm16(disp) ) {
1.3155 + if ( scale == 0 ) {
1.3156 + __ daddu(AT, as_Register(base), as_Register(index));
1.3157 + } else {
1.3158 + __ dsll(AT, as_Register(index), scale);
1.3159 + __ daddu(AT, as_Register(base), AT);
1.3160 + }
1.3161 + __ sw(as_Register(src), AT, disp);
1.3162 + } else {
1.3163 + if ( scale == 0 ) {
1.3164 + __ move(T9, disp);
1.3165 + __ daddu(AT, as_Register(index), T9);
1.3166 + } else {
1.3167 + __ dsll(AT, as_Register(index), scale);
1.3168 + __ move(T9, disp);
1.3169 + __ daddu(AT, AT, T9);
1.3170 + }
1.3171 + __ gsswx(as_Register(src), as_Register(base), AT, 0);
1.3172 + }
1.3173 + } else { //not use loongson isa
1.3174 + if (scale == 0) {
1.3175 + __ daddu(AT, as_Register(base), as_Register(index));
1.3176 + } else {
1.3177 + __ dsll(AT, as_Register(index), scale);
1.3178 + __ daddu(AT, as_Register(base), AT);
1.3179 + }
1.3180 + if( Assembler::is_simm16(disp) ) {
1.3181 + __ sw(as_Register(src), AT, disp);
1.3182 + } else {
1.3183 + __ move(T9, disp);
1.3184 + __ daddu(AT, AT, T9);
1.3185 + __ sw(as_Register(src), AT, 0);
1.3186 + }
1.3187 + }
1.3188 + } else {
1.3189 + if ( UseLoongsonISA ) {
1.3190 + if ( Assembler::is_simm16(disp) ) {
1.3191 + __ sw(as_Register(src), as_Register(base), disp);
1.3192 + } else {
1.3193 + __ move(T9, disp);
1.3194 + __ gsswx(as_Register(src), as_Register(base), T9, 0);
1.3195 + }
1.3196 + } else {
1.3197 + if( Assembler::is_simm16(disp) ) {
1.3198 + __ sw(as_Register(src), as_Register(base), disp);
1.3199 + } else {
1.3200 + __ move(T9, disp);
1.3201 + __ daddu(AT, as_Register(base), T9);
1.3202 + __ sw(as_Register(src), AT, 0);
1.3203 + }
1.3204 + }
1.3205 + }
1.3206 %}
1.3207
1.3208 enc_class store_P_immP0_enc (memory mem) %{
1.3209 - MacroAssembler _masm(&cbuf);
1.3210 - int base = $mem$$base;
1.3211 - int index = $mem$$index;
1.3212 - int scale = $mem$$scale;
1.3213 - int disp = $mem$$disp;
1.3214 -
1.3215 - if( index != 0 ) {
1.3216 + MacroAssembler _masm(&cbuf);
1.3217 + int base = $mem$$base;
1.3218 + int index = $mem$$index;
1.3219 + int scale = $mem$$scale;
1.3220 + int disp = $mem$$disp;
1.3221 +
1.3222 + if( index != 0 ) {
1.3223 + if (scale == 0) {
1.3224 + if( Assembler::is_simm16(disp) ) {
1.3225 + if (UseLoongsonISA && Assembler::is_simm(disp, 8)) {
1.3226 + __ gssdx(R0, as_Register(base), as_Register(index), disp);
1.3227 + } else {
1.3228 + __ daddu(AT, as_Register(base), as_Register(index));
1.3229 + __ sd(R0, AT, disp);
1.3230 + }
1.3231 + } else {
1.3232 + __ daddu(AT, as_Register(base), as_Register(index));
1.3233 + __ move(T9, disp);
1.3234 + if(UseLoongsonISA) {
1.3235 + __ gssdx(R0, AT, T9, 0);
1.3236 + } else {
1.3237 + __ daddu(AT, AT, T9);
1.3238 + __ sd(R0, AT, 0);
1.3239 + }
1.3240 + }
1.3241 + } else {
1.3242 + __ dsll(AT, as_Register(index), scale);
1.3243 + if( Assembler::is_simm16(disp) ) {
1.3244 + if (UseLoongsonISA && Assembler::is_simm(disp, 8)) {
1.3245 + __ gssdx(R0, as_Register(base), AT, disp);
1.3246 + } else {
1.3247 + __ daddu(AT, as_Register(base), AT);
1.3248 + __ sd(R0, AT, disp);
1.3249 + }
1.3250 + } else {
1.3251 + __ daddu(AT, as_Register(base), AT);
1.3252 + __ move(T9, disp);
1.3253 + if (UseLoongsonISA) {
1.3254 + __ gssdx(R0, AT, T9, 0);
1.3255 + } else {
1.3256 + __ daddu(AT, AT, T9);
1.3257 + __ sd(R0, AT, 0);
1.3258 + }
1.3259 + }
1.3260 + }
1.3261 + } else {
1.3262 + if( Assembler::is_simm16(disp) ) {
1.3263 + __ sd(R0, as_Register(base), disp);
1.3264 + } else {
1.3265 + __ move(T9, disp);
1.3266 + if (UseLoongsonISA) {
1.3267 + __ gssdx(R0, as_Register(base), T9, 0);
1.3268 + } else {
1.3269 + __ daddu(AT, as_Register(base), T9);
1.3270 + __ sd(R0, AT, 0);
1.3271 + }
1.3272 + }
1.3273 + }
1.3274 + %}
1.3275 +
1.3276 + enc_class storeImmN0_enc(memory mem, ImmN0 src) %{
1.3277 + MacroAssembler _masm(&cbuf);
1.3278 + int base = $mem$$base;
1.3279 + int index = $mem$$index;
1.3280 + int scale = $mem$$scale;
1.3281 + int disp = $mem$$disp;
1.3282 +
1.3283 + if(index!=0){
1.3284 + if (scale == 0) {
1.3285 + __ daddu(AT, as_Register(base), as_Register(index));
1.3286 + } else {
1.3287 + __ dsll(AT, as_Register(index), scale);
1.3288 + __ daddu(AT, as_Register(base), AT);
1.3289 + }
1.3290 +
1.3291 + if( Assembler::is_simm16(disp) ) {
1.3292 + __ sw(R0, AT, disp);
1.3293 + } else {
1.3294 + __ move(T9, disp);
1.3295 + __ daddu(AT, AT, T9);
1.3296 + __ sw(R0, AT, 0);
1.3297 + }
1.3298 + } else {
1.3299 + if( Assembler::is_simm16(disp) ) {
1.3300 + __ sw(R0, as_Register(base), disp);
1.3301 + } else {
1.3302 + __ move(T9, disp);
1.3303 + __ daddu(AT, as_Register(base), T9);
1.3304 + __ sw(R0, AT, 0);
1.3305 + }
1.3306 + }
1.3307 + %}
1.3308 +
1.3309 + enc_class load_L_enc (mRegL dst, memory mem) %{
1.3310 + MacroAssembler _masm(&cbuf);
1.3311 + int base = $mem$$base;
1.3312 + int index = $mem$$index;
1.3313 + int scale = $mem$$scale;
1.3314 + int disp = $mem$$disp;
1.3315 + Register dst_reg = as_Register($dst$$reg);
1.3316 +
1.3317 + // For implicit null check
1.3318 + __ lb(AT, as_Register(base), 0);
1.3319 +
1.3320 + if( index != 0 ) {
1.3321 + if (scale == 0) {
1.3322 + __ daddu(AT, as_Register(base), as_Register(index));
1.3323 + } else {
1.3324 + __ dsll(AT, as_Register(index), scale);
1.3325 + __ daddu(AT, as_Register(base), AT);
1.3326 + }
1.3327 + if( Assembler::is_simm16(disp) ) {
1.3328 + __ ld(dst_reg, AT, disp);
1.3329 + } else {
1.3330 + __ move(T9, disp);
1.3331 + __ daddu(AT, AT, T9);
1.3332 + __ ld(dst_reg, AT, 0);
1.3333 + }
1.3334 + } else {
1.3335 + if( Assembler::is_simm16(disp) ) {
1.3336 + __ ld(dst_reg, as_Register(base), disp);
1.3337 + } else {
1.3338 + __ move(T9, disp);
1.3339 + __ daddu(AT, as_Register(base), T9);
1.3340 + __ ld(dst_reg, AT, 0);
1.3341 + }
1.3342 + }
1.3343 + %}
1.3344 +
1.3345 + enc_class store_L_reg_enc (memory mem, mRegL src) %{
1.3346 + MacroAssembler _masm(&cbuf);
1.3347 + int base = $mem$$base;
1.3348 + int index = $mem$$index;
1.3349 + int scale = $mem$$scale;
1.3350 + int disp = $mem$$disp;
1.3351 + Register src_reg = as_Register($src$$reg);
1.3352 +
1.3353 + if( index != 0 ) {
1.3354 + if (scale == 0) {
1.3355 + __ daddu(AT, as_Register(base), as_Register(index));
1.3356 + } else {
1.3357 + __ dsll(AT, as_Register(index), scale);
1.3358 + __ daddu(AT, as_Register(base), AT);
1.3359 + }
1.3360 + if( Assembler::is_simm16(disp) ) {
1.3361 + __ sd(src_reg, AT, disp);
1.3362 + } else {
1.3363 + __ move(T9, disp);
1.3364 + __ daddu(AT, AT, T9);
1.3365 + __ sd(src_reg, AT, 0);
1.3366 + }
1.3367 + } else {
1.3368 + if( Assembler::is_simm16(disp) ) {
1.3369 + __ sd(src_reg, as_Register(base), disp);
1.3370 + } else {
1.3371 + __ move(T9, disp);
1.3372 + __ daddu(AT, as_Register(base), T9);
1.3373 + __ sd(src_reg, AT, 0);
1.3374 + }
1.3375 + }
1.3376 + %}
1.3377 +
1.3378 + enc_class store_L_immL0_enc (memory mem, immL0 src) %{
1.3379 + MacroAssembler _masm(&cbuf);
1.3380 + int base = $mem$$base;
1.3381 + int index = $mem$$index;
1.3382 + int scale = $mem$$scale;
1.3383 + int disp = $mem$$disp;
1.3384 +
1.3385 + if( index != 0 ) {
1.3386 + // For implicit null check
1.3387 + __ lb(AT, as_Register(base), 0);
1.3388 +
1.3389 + if (scale == 0) {
1.3390 + __ daddu(AT, as_Register(base), as_Register(index));
1.3391 + } else {
1.3392 + __ dsll(AT, as_Register(index), scale);
1.3393 + __ daddu(AT, as_Register(base), AT);
1.3394 + }
1.3395 + if( Assembler::is_simm16(disp) ) {
1.3396 + __ sd(R0, AT, disp);
1.3397 + } else {
1.3398 + __ move(T9, disp);
1.3399 + __ addu(AT, AT, T9);
1.3400 + __ sd(R0, AT, 0);
1.3401 + }
1.3402 + } else {
1.3403 + if( Assembler::is_simm16(disp) ) {
1.3404 + __ sd(R0, as_Register(base), disp);
1.3405 + } else {
1.3406 + __ move(T9, disp);
1.3407 + __ addu(AT, as_Register(base), T9);
1.3408 + __ sd(R0, AT, 0);
1.3409 + }
1.3410 + }
1.3411 + %}
1.3412 +
1.3413 + enc_class store_L_immL_enc (memory mem, immL src) %{
1.3414 + MacroAssembler _masm(&cbuf);
1.3415 + int base = $mem$$base;
1.3416 + int index = $mem$$index;
1.3417 + int scale = $mem$$scale;
1.3418 + int disp = $mem$$disp;
1.3419 + long imm = $src$$constant;
1.3420 +
1.3421 + if( index != 0 ) {
1.3422 + if (scale == 0) {
1.3423 + __ daddu(AT, as_Register(base), as_Register(index));
1.3424 + } else {
1.3425 + __ dsll(AT, as_Register(index), scale);
1.3426 + __ daddu(AT, as_Register(base), AT);
1.3427 + }
1.3428 + if( Assembler::is_simm16(disp) ) {
1.3429 + __ set64(T9, imm);
1.3430 + __ sd(T9, AT, disp);
1.3431 + } else {
1.3432 + __ move(T9, disp);
1.3433 + __ addu(AT, AT, T9);
1.3434 + __ set64(T9, imm);
1.3435 + __ sd(T9, AT, 0);
1.3436 + }
1.3437 + } else {
1.3438 + if( Assembler::is_simm16(disp) ) {
1.3439 + __ move(AT, as_Register(base));
1.3440 + __ set64(T9, imm);
1.3441 + __ sd(T9, AT, disp);
1.3442 + } else {
1.3443 + __ move(T9, disp);
1.3444 + __ addu(AT, as_Register(base), T9);
1.3445 + __ set64(T9, imm);
1.3446 + __ sd(T9, AT, 0);
1.3447 + }
1.3448 + }
1.3449 + %}
1.3450 +
1.3451 + enc_class load_F_enc (regF dst, memory mem) %{
1.3452 + MacroAssembler _masm(&cbuf);
1.3453 + int base = $mem$$base;
1.3454 + int index = $mem$$index;
1.3455 + int scale = $mem$$scale;
1.3456 + int disp = $mem$$disp;
1.3457 + FloatRegister dst = $dst$$FloatRegister;
1.3458 +
1.3459 + if( index != 0 ) {
1.3460 + if( Assembler::is_simm16(disp) ) {
1.3461 + if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
1.3462 + if (scale == 0) {
1.3463 + __ gslwxc1(dst, as_Register(base), as_Register(index), disp);
1.3464 + } else {
1.3465 + __ dsll(AT, as_Register(index), scale);
1.3466 + __ gslwxc1(dst, as_Register(base), AT, disp);
1.3467 + }
1.3468 + } else {
1.3469 + if (scale == 0) {
1.3470 + __ daddu(AT, as_Register(base), as_Register(index));
1.3471 + } else {
1.3472 + __ dsll(AT, as_Register(index), scale);
1.3473 + __ daddu(AT, as_Register(base), AT);
1.3474 + }
1.3475 + __ lwc1(dst, AT, disp);
1.3476 + }
1.3477 + } else {
1.3478 if (scale == 0) {
1.3479 - if( Assembler::is_simm16(disp) ) {
1.3480 - if (UseLoongsonISA && Assembler::is_simm(disp, 8)) {
1.3481 - __ gssdx(R0, as_Register(base), as_Register(index), disp);
1.3482 - } else {
1.3483 - __ daddu(AT, as_Register(base), as_Register(index));
1.3484 - __ sd(R0, AT, disp);
1.3485 - }
1.3486 - } else {
1.3487 - __ daddu(AT, as_Register(base), as_Register(index));
1.3488 - __ move(T9, disp);
1.3489 - if(UseLoongsonISA) {
1.3490 - __ gssdx(R0, AT, T9, 0);
1.3491 - } else {
1.3492 - __ daddu(AT, AT, T9);
1.3493 - __ sd(R0, AT, 0);
1.3494 - }
1.3495 - }
1.3496 - } else {
1.3497 - __ dsll(AT, as_Register(index), scale);
1.3498 - if( Assembler::is_simm16(disp) ) {
1.3499 - if (UseLoongsonISA && Assembler::is_simm(disp, 8)) {
1.3500 - __ gssdx(R0, as_Register(base), AT, disp);
1.3501 - } else {
1.3502 - __ daddu(AT, as_Register(base), AT);
1.3503 - __ sd(R0, AT, disp);
1.3504 - }
1.3505 - } else {
1.3506 - __ daddu(AT, as_Register(base), AT);
1.3507 - __ move(T9, disp);
1.3508 - if (UseLoongsonISA) {
1.3509 - __ gssdx(R0, AT, T9, 0);
1.3510 - } else {
1.3511 - __ daddu(AT, AT, T9);
1.3512 - __ sd(R0, AT, 0);
1.3513 - }
1.3514 - }
1.3515 - }
1.3516 - } else {
1.3517 - if( Assembler::is_simm16(disp) ) {
1.3518 - __ sd(R0, as_Register(base), disp);
1.3519 - } else {
1.3520 - __ move(T9, disp);
1.3521 - if (UseLoongsonISA) {
1.3522 - __ gssdx(R0, as_Register(base), T9, 0);
1.3523 - } else {
1.3524 - __ daddu(AT, as_Register(base), T9);
1.3525 - __ sd(R0, AT, 0);
1.3526 - }
1.3527 - }
1.3528 - }
1.3529 - %}
1.3530 -
1.3531 - enc_class storeImmN0_enc(memory mem, ImmN0 src) %{
1.3532 - MacroAssembler _masm(&cbuf);
1.3533 - int base = $mem$$base;
1.3534 - int index = $mem$$index;
1.3535 - int scale = $mem$$scale;
1.3536 - int disp = $mem$$disp;
1.3537 -
1.3538 - if(index!=0){
1.3539 - if (scale == 0) {
1.3540 - __ daddu(AT, as_Register(base), as_Register(index));
1.3541 - } else {
1.3542 - __ dsll(AT, as_Register(index), scale);
1.3543 - __ daddu(AT, as_Register(base), AT);
1.3544 - }
1.3545 -
1.3546 - if( Assembler::is_simm16(disp) ) {
1.3547 - __ sw(R0, AT, disp);
1.3548 - } else {
1.3549 - __ move(T9, disp);
1.3550 - __ daddu(AT, AT, T9);
1.3551 - __ sw(R0, AT, 0);
1.3552 - }
1.3553 - }
1.3554 - else {
1.3555 - if( Assembler::is_simm16(disp) ) {
1.3556 - __ sw(R0, as_Register(base), disp);
1.3557 - } else {
1.3558 - __ move(T9, disp);
1.3559 - __ daddu(AT, as_Register(base), T9);
1.3560 - __ sw(R0, AT, 0);
1.3561 - }
1.3562 - }
1.3563 - %}
1.3564 -
1.3565 - enc_class load_L_enc (mRegL dst, memory mem) %{
1.3566 - MacroAssembler _masm(&cbuf);
1.3567 - int base = $mem$$base;
1.3568 - int index = $mem$$index;
1.3569 - int scale = $mem$$scale;
1.3570 - int disp = $mem$$disp;
1.3571 - Register dst_reg = as_Register($dst$$reg);
1.3572 -
1.3573 - // For implicit null check
1.3574 - __ lb(AT, as_Register(base), 0);
1.3575 -
1.3576 - if( index != 0 ) {
1.3577 + __ daddu(AT, as_Register(base), as_Register(index));
1.3578 + } else {
1.3579 + __ dsll(AT, as_Register(index), scale);
1.3580 + __ daddu(AT, as_Register(base), AT);
1.3581 + }
1.3582 + __ move(T9, disp);
1.3583 + if( UseLoongsonISA ) {
1.3584 + __ gslwxc1(dst, AT, T9, 0);
1.3585 + } else {
1.3586 + __ daddu(AT, AT, T9);
1.3587 + __ lwc1(dst, AT, 0);
1.3588 + }
1.3589 + }
1.3590 + } else {
1.3591 + if( Assembler::is_simm16(disp) ) {
1.3592 + __ lwc1(dst, as_Register(base), disp);
1.3593 + } else {
1.3594 + __ move(T9, disp);
1.3595 + if( UseLoongsonISA ) {
1.3596 + __ gslwxc1(dst, as_Register(base), T9, 0);
1.3597 + } else {
1.3598 + __ daddu(AT, as_Register(base), T9);
1.3599 + __ lwc1(dst, AT, 0);
1.3600 + }
1.3601 + }
1.3602 + }
1.3603 + %}
1.3604 +
1.3605 + enc_class store_F_reg_enc (memory mem, regF src) %{
1.3606 + MacroAssembler _masm(&cbuf);
1.3607 + int base = $mem$$base;
1.3608 + int index = $mem$$index;
1.3609 + int scale = $mem$$scale;
1.3610 + int disp = $mem$$disp;
1.3611 + FloatRegister src = $src$$FloatRegister;
1.3612 +
1.3613 + if( index != 0 ) {
1.3614 + if( Assembler::is_simm16(disp) ) {
1.3615 + if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
1.3616 + if (scale == 0) {
1.3617 + __ gsswxc1(src, as_Register(base), as_Register(index), disp);
1.3618 + } else {
1.3619 + __ dsll(AT, as_Register(index), scale);
1.3620 + __ gsswxc1(src, as_Register(base), AT, disp);
1.3621 + }
1.3622 + } else {
1.3623 + if (scale == 0) {
1.3624 + __ daddu(AT, as_Register(base), as_Register(index));
1.3625 + } else {
1.3626 + __ dsll(AT, as_Register(index), scale);
1.3627 + __ daddu(AT, as_Register(base), AT);
1.3628 + }
1.3629 + __ swc1(src, AT, disp);
1.3630 + }
1.3631 + } else {
1.3632 if (scale == 0) {
1.3633 - __ daddu(AT, as_Register(base), as_Register(index));
1.3634 - } else {
1.3635 - __ dsll(AT, as_Register(index), scale);
1.3636 - __ daddu(AT, as_Register(base), AT);
1.3637 - }
1.3638 - if( Assembler::is_simm16(disp) ) {
1.3639 - __ ld(dst_reg, AT, disp);
1.3640 - } else {
1.3641 - __ move(T9, disp);
1.3642 - __ daddu(AT, AT, T9);
1.3643 - __ ld(dst_reg, AT, 0);
1.3644 - }
1.3645 - } else {
1.3646 - if( Assembler::is_simm16(disp) ) {
1.3647 - __ ld(dst_reg, as_Register(base), disp);
1.3648 - } else {
1.3649 - __ move(T9, disp);
1.3650 - __ daddu(AT, as_Register(base), T9);
1.3651 - __ ld(dst_reg, AT, 0);
1.3652 - }
1.3653 - }
1.3654 - %}
1.3655 -
1.3656 - enc_class store_L_reg_enc (memory mem, mRegL src) %{
1.3657 - MacroAssembler _masm(&cbuf);
1.3658 - int base = $mem$$base;
1.3659 - int index = $mem$$index;
1.3660 - int scale = $mem$$scale;
1.3661 - int disp = $mem$$disp;
1.3662 - Register src_reg = as_Register($src$$reg);
1.3663 -
1.3664 - if( index != 0 ) {
1.3665 + __ daddu(AT, as_Register(base), as_Register(index));
1.3666 + } else {
1.3667 + __ dsll(AT, as_Register(index), scale);
1.3668 + __ daddu(AT, as_Register(base), AT);
1.3669 + }
1.3670 + __ move(T9, disp);
1.3671 + if( UseLoongsonISA ) {
1.3672 + __ gsswxc1(src, AT, T9, 0);
1.3673 + } else {
1.3674 + __ daddu(AT, AT, T9);
1.3675 + __ swc1(src, AT, 0);
1.3676 + }
1.3677 + }
1.3678 + } else {
1.3679 + if( Assembler::is_simm16(disp) ) {
1.3680 + __ swc1(src, as_Register(base), disp);
1.3681 + } else {
1.3682 + __ move(T9, disp);
1.3683 + if( UseLoongsonISA ) {
1.3684 + __ gsswxc1(src, as_Register(base), T9, 0);
1.3685 + } else {
1.3686 + __ daddu(AT, as_Register(base), T9);
1.3687 + __ swc1(src, AT, 0);
1.3688 + }
1.3689 + }
1.3690 + }
1.3691 + %}
1.3692 +
1.3693 + enc_class load_D_enc (regD dst, memory mem) %{
1.3694 + MacroAssembler _masm(&cbuf);
1.3695 + int base = $mem$$base;
1.3696 + int index = $mem$$index;
1.3697 + int scale = $mem$$scale;
1.3698 + int disp = $mem$$disp;
1.3699 + FloatRegister dst_reg = as_FloatRegister($dst$$reg);
1.3700 +
1.3701 + if( index != 0 ) {
1.3702 + if( Assembler::is_simm16(disp) ) {
1.3703 + if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
1.3704 + if (scale == 0) {
1.3705 + __ gsldxc1(dst_reg, as_Register(base), as_Register(index), disp);
1.3706 + } else {
1.3707 + __ dsll(AT, as_Register(index), scale);
1.3708 + __ gsldxc1(dst_reg, as_Register(base), AT, disp);
1.3709 + }
1.3710 + } else {
1.3711 + if (scale == 0) {
1.3712 + __ daddu(AT, as_Register(base), as_Register(index));
1.3713 + } else {
1.3714 + __ dsll(AT, as_Register(index), scale);
1.3715 + __ daddu(AT, as_Register(base), AT);
1.3716 + }
1.3717 + __ ldc1(dst_reg, AT, disp);
1.3718 + }
1.3719 + } else {
1.3720 if (scale == 0) {
1.3721 - __ daddu(AT, as_Register(base), as_Register(index));
1.3722 - } else {
1.3723 - __ dsll(AT, as_Register(index), scale);
1.3724 - __ daddu(AT, as_Register(base), AT);
1.3725 - }
1.3726 - if( Assembler::is_simm16(disp) ) {
1.3727 - __ sd(src_reg, AT, disp);
1.3728 - } else {
1.3729 - __ move(T9, disp);
1.3730 - __ daddu(AT, AT, T9);
1.3731 - __ sd(src_reg, AT, 0);
1.3732 - }
1.3733 - } else {
1.3734 - if( Assembler::is_simm16(disp) ) {
1.3735 - __ sd(src_reg, as_Register(base), disp);
1.3736 - } else {
1.3737 - __ move(T9, disp);
1.3738 - __ daddu(AT, as_Register(base), T9);
1.3739 - __ sd(src_reg, AT, 0);
1.3740 - }
1.3741 - }
1.3742 - %}
1.3743 -
1.3744 - enc_class store_L_immL0_enc (memory mem, immL0 src) %{
1.3745 - MacroAssembler _masm(&cbuf);
1.3746 - int base = $mem$$base;
1.3747 - int index = $mem$$index;
1.3748 - int scale = $mem$$scale;
1.3749 - int disp = $mem$$disp;
1.3750 -
1.3751 - if( index != 0 ) {
1.3752 - // For implicit null check
1.3753 - __ lb(AT, as_Register(base), 0);
1.3754 -
1.3755 + __ daddu(AT, as_Register(base), as_Register(index));
1.3756 + } else {
1.3757 + __ dsll(AT, as_Register(index), scale);
1.3758 + __ daddu(AT, as_Register(base), AT);
1.3759 + }
1.3760 + __ move(T9, disp);
1.3761 + if( UseLoongsonISA ) {
1.3762 + __ gsldxc1(dst_reg, AT, T9, 0);
1.3763 + } else {
1.3764 + __ addu(AT, AT, T9);
1.3765 + __ ldc1(dst_reg, AT, 0);
1.3766 + }
1.3767 + }
1.3768 + } else {
1.3769 + if( Assembler::is_simm16(disp) ) {
1.3770 + __ ldc1(dst_reg, as_Register(base), disp);
1.3771 + } else {
1.3772 + __ move(T9, disp);
1.3773 + if( UseLoongsonISA ) {
1.3774 + __ gsldxc1(dst_reg, as_Register(base), T9, 0);
1.3775 + } else {
1.3776 + __ addu(AT, as_Register(base), T9);
1.3777 + __ ldc1(dst_reg, AT, 0);
1.3778 + }
1.3779 + }
1.3780 + }
1.3781 + %}
1.3782 +
1.3783 + enc_class store_D_reg_enc (memory mem, regD src) %{
1.3784 + MacroAssembler _masm(&cbuf);
1.3785 + int base = $mem$$base;
1.3786 + int index = $mem$$index;
1.3787 + int scale = $mem$$scale;
1.3788 + int disp = $mem$$disp;
1.3789 + FloatRegister src_reg = as_FloatRegister($src$$reg);
1.3790 +
1.3791 + if( index != 0 ) {
1.3792 + if( Assembler::is_simm16(disp) ) {
1.3793 + if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
1.3794 + if (scale == 0) {
1.3795 + __ gssdxc1(src_reg, as_Register(base), as_Register(index), disp);
1.3796 + } else {
1.3797 + __ dsll(AT, as_Register(index), scale);
1.3798 + __ gssdxc1(src_reg, as_Register(base), AT, disp);
1.3799 + }
1.3800 + } else {
1.3801 + if (scale == 0) {
1.3802 + __ daddu(AT, as_Register(base), as_Register(index));
1.3803 + } else {
1.3804 + __ dsll(AT, as_Register(index), scale);
1.3805 + __ daddu(AT, as_Register(base), AT);
1.3806 + }
1.3807 + __ sdc1(src_reg, AT, disp);
1.3808 + }
1.3809 + } else {
1.3810 if (scale == 0) {
1.3811 - __ daddu(AT, as_Register(base), as_Register(index));
1.3812 - } else {
1.3813 - __ dsll(AT, as_Register(index), scale);
1.3814 - __ daddu(AT, as_Register(base), AT);
1.3815 - }
1.3816 - if( Assembler::is_simm16(disp) ) {
1.3817 - __ sd(R0, AT, disp);
1.3818 - } else {
1.3819 - __ move(T9, disp);
1.3820 - __ addu(AT, AT, T9);
1.3821 - __ sd(R0, AT, 0);
1.3822 - }
1.3823 - } else {
1.3824 - if( Assembler::is_simm16(disp) ) {
1.3825 - __ sd(R0, as_Register(base), disp);
1.3826 - } else {
1.3827 - __ move(T9, disp);
1.3828 - __ addu(AT, as_Register(base), T9);
1.3829 - __ sd(R0, AT, 0);
1.3830 - }
1.3831 - }
1.3832 - %}
1.3833 -
1.3834 - enc_class store_L_immL_enc (memory mem, immL src) %{
1.3835 - MacroAssembler _masm(&cbuf);
1.3836 - int base = $mem$$base;
1.3837 - int index = $mem$$index;
1.3838 - int scale = $mem$$scale;
1.3839 - int disp = $mem$$disp;
1.3840 - long imm = $src$$constant;
1.3841 -
1.3842 - if( index != 0 ) {
1.3843 - if (scale == 0) {
1.3844 - __ daddu(AT, as_Register(base), as_Register(index));
1.3845 - } else {
1.3846 - __ dsll(AT, as_Register(index), scale);
1.3847 - __ daddu(AT, as_Register(base), AT);
1.3848 - }
1.3849 - if( Assembler::is_simm16(disp) ) {
1.3850 - __ set64(T9, imm);
1.3851 - __ sd(T9, AT, disp);
1.3852 - } else {
1.3853 - __ move(T9, disp);
1.3854 - __ addu(AT, AT, T9);
1.3855 - __ set64(T9, imm);
1.3856 - __ sd(T9, AT, 0);
1.3857 - }
1.3858 - } else {
1.3859 - if( Assembler::is_simm16(disp) ) {
1.3860 - __ move(AT, as_Register(base));
1.3861 - __ set64(T9, imm);
1.3862 - __ sd(T9, AT, disp);
1.3863 - } else {
1.3864 - __ move(T9, disp);
1.3865 - __ addu(AT, as_Register(base), T9);
1.3866 - __ set64(T9, imm);
1.3867 - __ sd(T9, AT, 0);
1.3868 - }
1.3869 - }
1.3870 - %}
1.3871 -
1.3872 - enc_class load_F_enc (regF dst, memory mem) %{
1.3873 - MacroAssembler _masm(&cbuf);
1.3874 - int base = $mem$$base;
1.3875 - int index = $mem$$index;
1.3876 - int scale = $mem$$scale;
1.3877 - int disp = $mem$$disp;
1.3878 - FloatRegister dst = $dst$$FloatRegister;
1.3879 -
1.3880 - if( index != 0 ) {
1.3881 - if( Assembler::is_simm16(disp) ) {
1.3882 - if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
1.3883 - if (scale == 0) {
1.3884 - __ gslwxc1(dst, as_Register(base), as_Register(index), disp);
1.3885 - } else {
1.3886 - __ dsll(AT, as_Register(index), scale);
1.3887 - __ gslwxc1(dst, as_Register(base), AT, disp);
1.3888 - }
1.3889 - } else {
1.3890 - if (scale == 0) {
1.3891 - __ daddu(AT, as_Register(base), as_Register(index));
1.3892 - } else {
1.3893 - __ dsll(AT, as_Register(index), scale);
1.3894 - __ daddu(AT, as_Register(base), AT);
1.3895 - }
1.3896 - __ lwc1(dst, AT, disp);
1.3897 - }
1.3898 - } else {
1.3899 - if (scale == 0) {
1.3900 - __ daddu(AT, as_Register(base), as_Register(index));
1.3901 - } else {
1.3902 - __ dsll(AT, as_Register(index), scale);
1.3903 - __ daddu(AT, as_Register(base), AT);
1.3904 - }
1.3905 - __ move(T9, disp);
1.3906 - if( UseLoongsonISA ) {
1.3907 - __ gslwxc1(dst, AT, T9, 0);
1.3908 - } else {
1.3909 - __ daddu(AT, AT, T9);
1.3910 - __ lwc1(dst, AT, 0);
1.3911 - }
1.3912 - }
1.3913 - } else {
1.3914 - if( Assembler::is_simm16(disp) ) {
1.3915 - __ lwc1(dst, as_Register(base), disp);
1.3916 - } else {
1.3917 - __ move(T9, disp);
1.3918 - if( UseLoongsonISA ) {
1.3919 - __ gslwxc1(dst, as_Register(base), T9, 0);
1.3920 - } else {
1.3921 - __ daddu(AT, as_Register(base), T9);
1.3922 - __ lwc1(dst, AT, 0);
1.3923 - }
1.3924 - }
1.3925 - }
1.3926 - %}
1.3927 -
1.3928 - enc_class store_F_reg_enc (memory mem, regF src) %{
1.3929 - MacroAssembler _masm(&cbuf);
1.3930 - int base = $mem$$base;
1.3931 - int index = $mem$$index;
1.3932 - int scale = $mem$$scale;
1.3933 - int disp = $mem$$disp;
1.3934 - FloatRegister src = $src$$FloatRegister;
1.3935 -
1.3936 - if( index != 0 ) {
1.3937 - if( Assembler::is_simm16(disp) ) {
1.3938 - if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
1.3939 - if (scale == 0) {
1.3940 - __ gsswxc1(src, as_Register(base), as_Register(index), disp);
1.3941 - } else {
1.3942 - __ dsll(AT, as_Register(index), scale);
1.3943 - __ gsswxc1(src, as_Register(base), AT, disp);
1.3944 - }
1.3945 - } else {
1.3946 - if (scale == 0) {
1.3947 - __ daddu(AT, as_Register(base), as_Register(index));
1.3948 - } else {
1.3949 - __ dsll(AT, as_Register(index), scale);
1.3950 - __ daddu(AT, as_Register(base), AT);
1.3951 - }
1.3952 - __ swc1(src, AT, disp);
1.3953 - }
1.3954 - } else {
1.3955 - if (scale == 0) {
1.3956 - __ daddu(AT, as_Register(base), as_Register(index));
1.3957 - } else {
1.3958 - __ dsll(AT, as_Register(index), scale);
1.3959 - __ daddu(AT, as_Register(base), AT);
1.3960 - }
1.3961 - __ move(T9, disp);
1.3962 - if( UseLoongsonISA ) {
1.3963 - __ gsswxc1(src, AT, T9, 0);
1.3964 - } else {
1.3965 - __ daddu(AT, AT, T9);
1.3966 - __ swc1(src, AT, 0);
1.3967 - }
1.3968 - }
1.3969 - } else {
1.3970 - if( Assembler::is_simm16(disp) ) {
1.3971 - __ swc1(src, as_Register(base), disp);
1.3972 - } else {
1.3973 - __ move(T9, disp);
1.3974 - if( UseLoongsonISA ) {
1.3975 - __ gsswxc1(src, as_Register(base), T9, 0);
1.3976 - } else {
1.3977 - __ daddu(AT, as_Register(base), T9);
1.3978 - __ swc1(src, AT, 0);
1.3979 - }
1.3980 - }
1.3981 - }
1.3982 - %}
1.3983 -
1.3984 - enc_class load_D_enc (regD dst, memory mem) %{
1.3985 - MacroAssembler _masm(&cbuf);
1.3986 - int base = $mem$$base;
1.3987 - int index = $mem$$index;
1.3988 - int scale = $mem$$scale;
1.3989 - int disp = $mem$$disp;
1.3990 - FloatRegister dst_reg = as_FloatRegister($dst$$reg);
1.3991 -
1.3992 - if( index != 0 ) {
1.3993 - if( Assembler::is_simm16(disp) ) {
1.3994 - if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
1.3995 - if (scale == 0) {
1.3996 - __ gsldxc1(dst_reg, as_Register(base), as_Register(index), disp);
1.3997 - } else {
1.3998 - __ dsll(AT, as_Register(index), scale);
1.3999 - __ gsldxc1(dst_reg, as_Register(base), AT, disp);
1.4000 - }
1.4001 - } else {
1.4002 - if (scale == 0) {
1.4003 - __ daddu(AT, as_Register(base), as_Register(index));
1.4004 - } else {
1.4005 - __ dsll(AT, as_Register(index), scale);
1.4006 - __ daddu(AT, as_Register(base), AT);
1.4007 - }
1.4008 - __ ldc1(dst_reg, AT, disp);
1.4009 - }
1.4010 - } else {
1.4011 - if (scale == 0) {
1.4012 - __ daddu(AT, as_Register(base), as_Register(index));
1.4013 - } else {
1.4014 - __ dsll(AT, as_Register(index), scale);
1.4015 - __ daddu(AT, as_Register(base), AT);
1.4016 - }
1.4017 - __ move(T9, disp);
1.4018 - if( UseLoongsonISA ) {
1.4019 - __ gsldxc1(dst_reg, AT, T9, 0);
1.4020 - } else {
1.4021 - __ addu(AT, AT, T9);
1.4022 - __ ldc1(dst_reg, AT, 0);
1.4023 - }
1.4024 - }
1.4025 - } else {
1.4026 - if( Assembler::is_simm16(disp) ) {
1.4027 - __ ldc1(dst_reg, as_Register(base), disp);
1.4028 - } else {
1.4029 - __ move(T9, disp);
1.4030 - if( UseLoongsonISA ) {
1.4031 - __ gsldxc1(dst_reg, as_Register(base), T9, 0);
1.4032 - } else {
1.4033 - __ addu(AT, as_Register(base), T9);
1.4034 - __ ldc1(dst_reg, AT, 0);
1.4035 - }
1.4036 - }
1.4037 - }
1.4038 - %}
1.4039 -
1.4040 - enc_class store_D_reg_enc (memory mem, regD src) %{
1.4041 - MacroAssembler _masm(&cbuf);
1.4042 - int base = $mem$$base;
1.4043 - int index = $mem$$index;
1.4044 - int scale = $mem$$scale;
1.4045 - int disp = $mem$$disp;
1.4046 - FloatRegister src_reg = as_FloatRegister($src$$reg);
1.4047 -
1.4048 - if( index != 0 ) {
1.4049 - if( Assembler::is_simm16(disp) ) {
1.4050 - if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
1.4051 - if (scale == 0) {
1.4052 - __ gssdxc1(src_reg, as_Register(base), as_Register(index), disp);
1.4053 - } else {
1.4054 - __ dsll(AT, as_Register(index), scale);
1.4055 - __ gssdxc1(src_reg, as_Register(base), AT, disp);
1.4056 - }
1.4057 - } else {
1.4058 - if (scale == 0) {
1.4059 - __ daddu(AT, as_Register(base), as_Register(index));
1.4060 - } else {
1.4061 - __ dsll(AT, as_Register(index), scale);
1.4062 - __ daddu(AT, as_Register(base), AT);
1.4063 - }
1.4064 - __ sdc1(src_reg, AT, disp);
1.4065 - }
1.4066 - } else {
1.4067 - if (scale == 0) {
1.4068 - __ daddu(AT, as_Register(base), as_Register(index));
1.4069 - } else {
1.4070 - __ dsll(AT, as_Register(index), scale);
1.4071 - __ daddu(AT, as_Register(base), AT);
1.4072 - }
1.4073 - __ move(T9, disp);
1.4074 - if( UseLoongsonISA ) {
1.4075 - __ gssdxc1(src_reg, AT, T9, 0);
1.4076 - } else {
1.4077 - __ addu(AT, AT, T9);
1.4078 - __ sdc1(src_reg, AT, 0);
1.4079 - }
1.4080 - }
1.4081 - } else {
1.4082 - if( Assembler::is_simm16(disp) ) {
1.4083 - __ sdc1(src_reg, as_Register(base), disp);
1.4084 - } else {
1.4085 - __ move(T9, disp);
1.4086 - if( UseLoongsonISA ) {
1.4087 - __ gssdxc1(src_reg, as_Register(base), T9, 0);
1.4088 - } else {
1.4089 - __ addu(AT, as_Register(base), T9);
1.4090 - __ sdc1(src_reg, AT, 0);
1.4091 - }
1.4092 - }
1.4093 - }
1.4094 + __ daddu(AT, as_Register(base), as_Register(index));
1.4095 + } else {
1.4096 + __ dsll(AT, as_Register(index), scale);
1.4097 + __ daddu(AT, as_Register(base), AT);
1.4098 + }
1.4099 + __ move(T9, disp);
1.4100 + if( UseLoongsonISA ) {
1.4101 + __ gssdxc1(src_reg, AT, T9, 0);
1.4102 + } else {
1.4103 + __ addu(AT, AT, T9);
1.4104 + __ sdc1(src_reg, AT, 0);
1.4105 + }
1.4106 + }
1.4107 + } else {
1.4108 + if( Assembler::is_simm16(disp) ) {
1.4109 + __ sdc1(src_reg, as_Register(base), disp);
1.4110 + } else {
1.4111 + __ move(T9, disp);
1.4112 + if( UseLoongsonISA ) {
1.4113 + __ gssdxc1(src_reg, as_Register(base), T9, 0);
1.4114 + } else {
1.4115 + __ addu(AT, as_Register(base), T9);
1.4116 + __ sdc1(src_reg, AT, 0);
1.4117 + }
1.4118 + }
1.4119 + }
1.4120 %}
1.4121
1.4122 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
1.4123 - MacroAssembler _masm(&cbuf);
1.4124 + MacroAssembler _masm(&cbuf);
1.4125 // This is the instruction starting address for relocation info.
1.4126 __ block_comment("Java_To_Runtime");
1.4127 cbuf.set_insts_mark();
1.4128 __ relocate(relocInfo::runtime_call_type);
1.4129
1.4130 __ patchable_call((address)$meth$$method);
1.4131 - %}
1.4132 + %}
1.4133
1.4134 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
1.4135 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1.4136 @@ -3338,13 +3316,13 @@
1.4137 %}
1.4138
1.4139
1.4140 -/*
1.4141 - * [Ref: LIR_Assembler::ic_call() ]
1.4142 - */
1.4143 -enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
1.4144 + /*
1.4145 + * [Ref: LIR_Assembler::ic_call() ]
1.4146 + */
1.4147 + enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
1.4148 MacroAssembler _masm(&cbuf);
1.4149 - __ block_comment("Java_Dynamic_Call");
1.4150 - __ ic_call((address)$meth$$method);
1.4151 + __ block_comment("Java_Dynamic_Call");
1.4152 + __ ic_call((address)$meth$$method);
1.4153 %}
1.4154
1.4155
1.4156 @@ -3354,7 +3332,7 @@
1.4157
1.4158 MacroAssembler _masm(&cbuf);
1.4159
1.4160 - __ addu(flags, R0, R0);
1.4161 + __ addu(flags, R0, R0);
1.4162 __ beq(AT, R0, L);
1.4163 __ delayed()->nop();
1.4164 __ move(flags, 0xFFFFFFFF);
1.4165 @@ -3374,12 +3352,12 @@
1.4166 * 47c partialSubtypeCheck result=S1, sub=S1, super=S3, length=S0
1.4167 * 4bc mov S2, NULL #@loadConP
1.4168 * 4c0 beq S1, S2, B21 #@branchConP P=0.999999 C=-1.000000
1.4169 - */
1.4170 + */
1.4171 MacroAssembler _masm(&cbuf);
1.4172 Label done;
1.4173 __ check_klass_subtype_slow_path(sub, super, length, tmp,
1.4174 - NULL, &miss,
1.4175 - /*set_cond_codes:*/ true);
1.4176 + NULL, &miss,
1.4177 + /*set_cond_codes:*/ true);
1.4178 /* 2013/7/22 Jin: Refer to X86_64's RDI */
1.4179 __ move(result, 0);
1.4180 __ b(done);
1.4181 @@ -3400,10 +3378,10 @@
1.4182 // | (to get allocators register number
1.4183 // G Owned by | | v add SharedInfo::stack0)
1.4184 // r CALLER | |
1.4185 -// o | +--------+ pad to even-align allocators stack-slot
1.4186 +// o | +--------+ pad to even-align allocators stack-slot
1.4187 // w V | pad0 | numbers; owned by CALLER
1.4188 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
1.4189 -// h ^ | in | 5
1.4190 +// h ^ | in | 5
1.4191 // | | args | 4 Holes in incoming args owned by SELF
1.4192 // | | old | | 3
1.4193 // | | SP-+--------+----> Matcher::_old_SP, even aligned
1.4194 @@ -3412,30 +3390,30 @@
1.4195 // Self | pad2 | 2 pad to align old SP
1.4196 // | +--------+ 1
1.4197 // | | locks | 0
1.4198 -// | +--------+----> SharedInfo::stack0, even aligned
1.4199 +// | +--------+----> SharedInfo::stack0, even aligned
1.4200 // | | pad1 | 11 pad to align new SP
1.4201 // | +--------+
1.4202 // | | | 10
1.4203 // | | spills | 9 spills
1.4204 // V | | 8 (pad0 slot for callee)
1.4205 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
1.4206 -// ^ | out | 7
1.4207 +// ^ | out | 7
1.4208 // | | args | 6 Holes in outgoing args owned by CALLEE
1.4209 -// Owned by new | |
1.4210 -// Callee SP-+--------+----> Matcher::_new_SP, even aligned
1.4211 -// | |
1.4212 +// Owned by new | |
1.4213 +// Callee SP-+--------+----> Matcher::_new_SP, even aligned
1.4214 +// | |
1.4215 //
1.4216 -// Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
1.4217 +// Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
1.4218 // known from SELF's arguments and the Java calling convention.
1.4219 // Region 6-7 is determined per call site.
1.4220 -// Note 2: If the calling convention leaves holes in the incoming argument
1.4221 +// Note 2: If the calling convention leaves holes in the incoming argument
1.4222 // area, those holes are owned by SELF. Holes in the outgoing area
1.4223 // are owned by the CALLEE. Holes should not be nessecary in the
1.4224 // incoming area, as the Java calling convention is completely under
1.4225 // the control of the AD file. Doubles can be sorted and packed to
1.4226 // avoid holes. Holes in the outgoing arguments may be nessecary for
1.4227 // varargs C calling conventions.
1.4228 -// Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
1.4229 +// Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
1.4230 // even aligned with pad0 as needed.
1.4231 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
1.4232 // region 6-11 is even aligned; it may be padded out more so that
1.4233 @@ -3449,23 +3427,19 @@
1.4234
1.4235 stack_direction(TOWARDS_LOW);
1.4236
1.4237 - // These two registers define part of the calling convention
1.4238 + // These two registers define part of the calling convention
1.4239 // between compiled code and the interpreter.
1.4240 - // SEE StartI2CNode::calling_convention & StartC2INode::calling_convention & StartOSRNode::calling_convention
1.4241 - // for more information. by yjl 3/16/2006
1.4242 + // SEE StartI2CNode::calling_convention & StartC2INode::calling_convention & StartOSRNode::calling_convention
1.4243 + // for more information. by yjl 3/16/2006
1.4244
1.4245 inline_cache_reg(T1); // Inline Cache Register
1.4246 interpreter_method_oop_reg(S3); // Method Oop Register when calling interpreter
1.4247 - /*
1.4248 - inline_cache_reg(T1); // Inline Cache Register or methodOop for I2C
1.4249 - interpreter_arg_ptr_reg(A0); // Argument pointer for I2C adapters
1.4250 -*/
1.4251
1.4252 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
1.4253 - cisc_spilling_operand_name(indOffset32);
1.4254 + cisc_spilling_operand_name(indOffset32);
1.4255
1.4256 // Number of stack slots consumed by locking an object
1.4257 - // generate Compile::sync_stack_slots
1.4258 + // generate Compile::sync_stack_slots
1.4259 #ifdef _LP64
1.4260 sync_stack_slots(2);
1.4261 #else
1.4262 @@ -3474,20 +3448,20 @@
1.4263
1.4264 frame_pointer(SP);
1.4265
1.4266 - // Interpreter stores its frame pointer in a register which is
1.4267 + // Interpreter stores its frame pointer in a register which is
1.4268 // stored to the stack by I2CAdaptors.
1.4269 // I2CAdaptors convert from interpreted java to compiled java.
1.4270
1.4271 interpreter_frame_pointer(FP);
1.4272
1.4273 - // generate Matcher::stack_alignment
1.4274 - stack_alignment(StackAlignmentInBytes); //wordSize = sizeof(char*);
1.4275 -
1.4276 - // Number of stack slots between incoming argument block and the start of
1.4277 + // generate Matcher::stack_alignment
1.4278 + stack_alignment(StackAlignmentInBytes); //wordSize = sizeof(char*);
1.4279 +
1.4280 + // Number of stack slots between incoming argument block and the start of
1.4281 // a new frame. The PROLOG must add this many slots to the stack. The
1.4282 // EPILOG must remove this many slots. Intel needs one slot for
1.4283 // return address.
1.4284 - // generate Matcher::in_preserve_stack_slots
1.4285 + // generate Matcher::in_preserve_stack_slots
1.4286 //in_preserve_stack_slots(VerifyStackAtCalls + 2); //Now VerifyStackAtCalls is defined as false ! Leave one stack slot for ra and fp
1.4287 in_preserve_stack_slots(4); //Now VerifyStackAtCalls is defined as false ! Leave two stack slots for ra and fp
1.4288
1.4289 @@ -3510,11 +3484,11 @@
1.4290 // offsets are based on outgoing arguments, i.e. a CALLER setting up
1.4291 // arguments for a CALLEE. Incoming stack arguments are
1.4292 // automatically biased by the preserve_stack_slots field above.
1.4293 -
1.4294 -
1.4295 - // will generated to Matcher::calling_convention(OptoRegPair *sig, uint length, bool is_outgoing)
1.4296 - // StartNode::calling_convention call this. by yjl 3/16/2006
1.4297 - calling_convention %{
1.4298 +
1.4299 +
1.4300 + // will generated to Matcher::calling_convention(OptoRegPair *sig, uint length, bool is_outgoing)
1.4301 + // StartNode::calling_convention call this. by yjl 3/16/2006
1.4302 + calling_convention %{
1.4303 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
1.4304 %}
1.4305
1.4306 @@ -3529,15 +3503,15 @@
1.4307 // automatically biased by the preserve_stack_slots field above.
1.4308
1.4309
1.4310 - // SEE CallRuntimeNode::calling_convention for more information. by yjl 3/16/2006
1.4311 - c_calling_convention %{
1.4312 + // SEE CallRuntimeNode::calling_convention for more information. by yjl 3/16/2006
1.4313 + c_calling_convention %{
1.4314 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
1.4315 %}
1.4316
1.4317
1.4318 // Location of C & interpreter return values
1.4319 - // register(s) contain(s) return value for Op_StartI2C and Op_StartOSR.
1.4320 - // SEE Matcher::match. by yjl 3/16/2006
1.4321 + // register(s) contain(s) return value for Op_StartI2C and Op_StartOSR.
1.4322 + // SEE Matcher::match. by yjl 3/16/2006
1.4323 c_return_value %{
1.4324 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
1.4325 /* -- , -- , Op_RegN, Op_RegI, Op_RegP, Op_RegF, Op_RegD, Op_RegL */
1.4326 @@ -3547,8 +3521,8 @@
1.4327 %}
1.4328
1.4329 // Location of return values
1.4330 - // register(s) contain(s) return value for Op_StartC2I and Op_Start.
1.4331 - // SEE Matcher::match. by yjl 3/16/2006
1.4332 + // register(s) contain(s) return value for Op_StartC2I and Op_Start.
1.4333 + // SEE Matcher::match. by yjl 3/16/2006
1.4334
1.4335 return_value %{
1.4336 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
1.4337 @@ -3906,7 +3880,7 @@
1.4338 interface(CONST_INTER);
1.4339 %}
1.4340
1.4341 -// Pointer for polling page
1.4342 +// Pointer for polling page
1.4343 operand immP_poll() %{
1.4344 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
1.4345 match(ConP);
1.4346 @@ -4139,7 +4113,7 @@
1.4347 interface(CONST_INTER);
1.4348 %}
1.4349
1.4350 -//double-precision floating-point zero
1.4351 +//double-precision floating-point zero
1.4352 operand immD0() %{
1.4353 predicate(jlong_cast(n->getd()) == 0);
1.4354 match(ConD);
1.4355 @@ -4172,10 +4146,10 @@
1.4356 constraint(ALLOC_IN_RC(no_Ax_int_reg));
1.4357 match(RegI);
1.4358 match(mRegI);
1.4359 -
1.4360 +
1.4361 format %{ %}
1.4362 interface(REG_INTER);
1.4363 -%}
1.4364 +%}
1.4365
1.4366 operand mS0RegI() %{
1.4367 constraint(ALLOC_IN_RC(s0_reg));
1.4368 @@ -4622,19 +4596,19 @@
1.4369 operand mRegP() %{
1.4370 constraint(ALLOC_IN_RC(p_reg));
1.4371 match(RegP);
1.4372 -
1.4373 +
1.4374 format %{ %}
1.4375 interface(REG_INTER);
1.4376 -%}
1.4377 +%}
1.4378
1.4379 operand no_T8_mRegP() %{
1.4380 constraint(ALLOC_IN_RC(no_T8_p_reg));
1.4381 match(RegP);
1.4382 match(mRegP);
1.4383 -
1.4384 +
1.4385 format %{ %}
1.4386 interface(REG_INTER);
1.4387 -%}
1.4388 +%}
1.4389
1.4390 operand s0_RegP()
1.4391 %{
1.4392 @@ -5142,7 +5116,7 @@
1.4393 format %{ "[$reg] @ indirect" %}
1.4394 interface(MEMORY_INTER) %{
1.4395 base($reg);
1.4396 - index(0x0); /* NO_INDEX */
1.4397 + index(0x0); /* NO_INDEX */
1.4398 scale(0x0);
1.4399 disp(0x0);
1.4400 %}
1.4401 @@ -5181,7 +5155,7 @@
1.4402 %}
1.4403
1.4404
1.4405 -// [base + index + offset]
1.4406 +// [base + index + offset]
1.4407 operand baseIndexOffset8(mRegP base, mRegL index, immL8 off)
1.4408 %{
1.4409 constraint(ALLOC_IN_RC(p_reg));
1.4410 @@ -5197,7 +5171,7 @@
1.4411 %}
1.4412 %}
1.4413
1.4414 -// [base + index + offset]
1.4415 +// [base + index + offset]
1.4416 operand baseIndexOffset8_convI2L(mRegP base, mRegI index, immL8 off)
1.4417 %{
1.4418 constraint(ALLOC_IN_RC(p_reg));
1.4419 @@ -5244,7 +5218,7 @@
1.4420 %}
1.4421 %}
1.4422
1.4423 -// [base + index<<scale + offset]
1.4424 +// [base + index<<scale + offset]
1.4425 operand basePosIndexScaleOffset8(mRegP base, mRegI index, immL8 off, immI_0_31 scale)
1.4426 %{
1.4427 constraint(ALLOC_IN_RC(p_reg));
1.4428 @@ -5306,13 +5280,13 @@
1.4429 format %{ "[$reg + $off (32-bit)] @ indOffset32" %}
1.4430 interface(MEMORY_INTER) %{
1.4431 base($reg);
1.4432 - index(0x0); /* NO_INDEX */
1.4433 + index(0x0); /* NO_INDEX */
1.4434 scale(0x0);
1.4435 disp($off);
1.4436 %}
1.4437 %}
1.4438
1.4439 -// Indirect Memory Plus Index Register
1.4440 +// Indirect Memory Plus Index Register
1.4441 operand indIndex(mRegP addr, mRegL index) %{
1.4442 constraint(ALLOC_IN_RC(p_reg));
1.4443 match(AddP addr index);
1.4444 @@ -5623,329 +5597,329 @@
1.4445 disp($reg); // Stack Offset
1.4446 %}
1.4447 %}
1.4448 -
1.4449 +
1.4450
1.4451 //------------------------OPERAND CLASSES--------------------------------------
1.4452 //opclass memory( direct, indirect, indOffset16, indOffset32, indOffset32X, indIndexOffset );
1.4453 -opclass memory( indirect, indirectNarrow, indOffset8, indOffset32, indIndex, indIndexScale, load_long_indirect, load_long_indOffset32, baseIndexOffset8, baseIndexOffset8_convI2L, indIndexScaleOffset8, indIndexScaleOffset8_convI2L, basePosIndexScaleOffset8, indIndexScaleOffsetNarrow, indPosIndexI2LScaleOffset8Narrow, indOffset8Narrow, indIndexOffset8Narrow);
1.4454 +opclass memory( indirect, indirectNarrow, indOffset8, indOffset32, indIndex, indIndexScale, load_long_indirect, load_long_indOffset32, baseIndexOffset8, baseIndexOffset8_convI2L, indIndexScaleOffset8, indIndexScaleOffset8_convI2L, basePosIndexScaleOffset8, indIndexScaleOffsetNarrow, indPosIndexI2LScaleOffset8Narrow, indOffset8Narrow, indIndexOffset8Narrow);
1.4455
1.4456
1.4457 //----------PIPELINE-----------------------------------------------------------
1.4458 // Rules which define the behavior of the target architectures pipeline.
1.4459 -
1.4460 +
1.4461 pipeline %{
1.4462
1.4463 -//----------ATTRIBUTES---------------------------------------------------------
1.4464 -attributes %{
1.4465 - fixed_size_instructions; // Fixed size instructions
1.4466 - branch_has_delay_slot; // branch have delay slot in gs2
1.4467 - max_instructions_per_bundle = 1; // 1 instruction per bundle
1.4468 - max_bundles_per_cycle = 4; // Up to 4 bundles per cycle
1.4469 - bundle_unit_size=4;
1.4470 - instruction_unit_size = 4; // An instruction is 4 bytes long
1.4471 - instruction_fetch_unit_size = 16; // The processor fetches one line
1.4472 - instruction_fetch_units = 1; // of 16 bytes
1.4473 -
1.4474 - // List of nop instructions
1.4475 - nops( MachNop );
1.4476 - %}
1.4477 -
1.4478 - //----------RESOURCES----------------------------------------------------------
1.4479 - // Resources are the functional units available to the machine
1.4480 -
1.4481 - resources(D1, D2, D3, D4, DECODE = D1 | D2 | D3| D4, ALU1, ALU2, ALU = ALU1 | ALU2, FPU1, FPU2, FPU = FPU1 | FPU2, MEM, BR);
1.4482 -
1.4483 - //----------PIPELINE DESCRIPTION-----------------------------------------------
1.4484 - // Pipeline Description specifies the stages in the machine's pipeline
1.4485 -
1.4486 - // IF: fetch
1.4487 - // ID: decode
1.4488 - // RD: read
1.4489 - // CA: caculate
1.4490 - // WB: write back
1.4491 - // CM: commit
1.4492 -
1.4493 - pipe_desc(IF, ID, RD, CA, WB, CM);
1.4494 -
1.4495 -
1.4496 - //----------PIPELINE CLASSES---------------------------------------------------
1.4497 - // Pipeline Classes describe the stages in which input and output are
1.4498 - // referenced by the hardware pipeline.
1.4499 -
1.4500 - //No.1 Integer ALU reg-reg operation : dst <-- reg1 op reg2
1.4501 - pipe_class ialu_regI_regI(mRegI dst, mRegI src1, mRegI src2) %{
1.4502 - single_instruction;
1.4503 - src1 : RD(read);
1.4504 - src2 : RD(read);
1.4505 - dst : WB(write)+1;
1.4506 - DECODE : ID;
1.4507 - ALU : CA;
1.4508 - %}
1.4509 -
1.4510 - //No.19 Integer mult operation : dst <-- reg1 mult reg2
1.4511 - pipe_class ialu_mult(mRegI dst, mRegI src1, mRegI src2) %{
1.4512 - src1 : RD(read);
1.4513 - src2 : RD(read);
1.4514 - dst : WB(write)+5;
1.4515 - DECODE : ID;
1.4516 - ALU2 : CA;
1.4517 - %}
1.4518 -
1.4519 - pipe_class mulL_reg_reg(mRegL dst, mRegL src1, mRegL src2) %{
1.4520 - src1 : RD(read);
1.4521 - src2 : RD(read);
1.4522 - dst : WB(write)+10;
1.4523 - DECODE : ID;
1.4524 - ALU2 : CA;
1.4525 - %}
1.4526 -
1.4527 - //No.19 Integer div operation : dst <-- reg1 div reg2
1.4528 - pipe_class ialu_div(mRegI dst, mRegI src1, mRegI src2) %{
1.4529 - src1 : RD(read);
1.4530 - src2 : RD(read);
1.4531 - dst : WB(write)+10;
1.4532 - DECODE : ID;
1.4533 - ALU2 : CA;
1.4534 - %}
1.4535 -
1.4536 - //No.19 Integer mod operation : dst <-- reg1 mod reg2
1.4537 - pipe_class ialu_mod(mRegI dst, mRegI src1, mRegI src2) %{
1.4538 - instruction_count(2);
1.4539 - src1 : RD(read);
1.4540 - src2 : RD(read);
1.4541 - dst : WB(write)+10;
1.4542 - DECODE : ID;
1.4543 - ALU2 : CA;
1.4544 - %}
1.4545 -
1.4546 - //No.15 Long ALU reg-reg operation : dst <-- reg1 op reg2
1.4547 - pipe_class ialu_regL_regL(mRegL dst, mRegL src1, mRegL src2) %{
1.4548 - instruction_count(2);
1.4549 - src1 : RD(read);
1.4550 - src2 : RD(read);
1.4551 - dst : WB(write);
1.4552 - DECODE : ID;
1.4553 - ALU : CA;
1.4554 - %}
1.4555 -
1.4556 - //No.18 Long ALU reg-imm16 operation : dst <-- reg1 op imm16
1.4557 - pipe_class ialu_regL_imm16(mRegL dst, mRegL src) %{
1.4558 - instruction_count(2);
1.4559 - src : RD(read);
1.4560 - dst : WB(write);
1.4561 - DECODE : ID;
1.4562 - ALU : CA;
1.4563 - %}
1.4564 -
1.4565 - //no.16 load Long from memory :
1.4566 - pipe_class ialu_loadL(mRegL dst, memory mem) %{
1.4567 - instruction_count(2);
1.4568 - mem : RD(read);
1.4569 - dst : WB(write)+5;
1.4570 - DECODE : ID;
1.4571 - MEM : RD;
1.4572 - %}
1.4573 -
1.4574 - //No.17 Store Long to Memory :
1.4575 - pipe_class ialu_storeL(mRegL src, memory mem) %{
1.4576 - instruction_count(2);
1.4577 - mem : RD(read);
1.4578 - src : RD(read);
1.4579 - DECODE : ID;
1.4580 - MEM : RD;
1.4581 - %}
1.4582 -
1.4583 - //No.2 Integer ALU reg-imm16 operation : dst <-- reg1 op imm16
1.4584 - pipe_class ialu_regI_imm16(mRegI dst, mRegI src) %{
1.4585 - single_instruction;
1.4586 - src : RD(read);
1.4587 - dst : WB(write);
1.4588 - DECODE : ID;
1.4589 - ALU : CA;
1.4590 - %}
1.4591 -
1.4592 - //No.3 Integer move operation : dst <-- reg
1.4593 - pipe_class ialu_regI_mov(mRegI dst, mRegI src) %{
1.4594 - src : RD(read);
1.4595 - dst : WB(write);
1.4596 - DECODE : ID;
1.4597 - ALU : CA;
1.4598 - %}
1.4599 -
1.4600 - //No.4 No instructions : do nothing
1.4601 - pipe_class empty( ) %{
1.4602 - instruction_count(0);
1.4603 - %}
1.4604 -
1.4605 - //No.5 UnConditional branch :
1.4606 - pipe_class pipe_jump( label labl ) %{
1.4607 - multiple_bundles;
1.4608 - DECODE : ID;
1.4609 - BR : RD;
1.4610 - %}
1.4611 -
1.4612 - //No.6 ALU Conditional branch :
1.4613 - pipe_class pipe_alu_branch(mRegI src1, mRegI src2, label labl ) %{
1.4614 - multiple_bundles;
1.4615 - src1 : RD(read);
1.4616 - src2 : RD(read);
1.4617 - DECODE : ID;
1.4618 - BR : RD;
1.4619 - %}
1.4620 -
1.4621 - //no.7 load integer from memory :
1.4622 - pipe_class ialu_loadI(mRegI dst, memory mem) %{
1.4623 - mem : RD(read);
1.4624 - dst : WB(write)+3;
1.4625 - DECODE : ID;
1.4626 - MEM : RD;
1.4627 - %}
1.4628 -
1.4629 - //No.8 Store Integer to Memory :
1.4630 - pipe_class ialu_storeI(mRegI src, memory mem) %{
1.4631 - mem : RD(read);
1.4632 - src : RD(read);
1.4633 - DECODE : ID;
1.4634 - MEM : RD;
1.4635 - %}
1.4636 -
1.4637 -
1.4638 - //No.10 Floating FPU reg-reg operation : dst <-- reg1 op reg2
1.4639 - pipe_class fpu_regF_regF(regF dst, regF src1, regF src2) %{
1.4640 - src1 : RD(read);
1.4641 - src2 : RD(read);
1.4642 - dst : WB(write);
1.4643 - DECODE : ID;
1.4644 - FPU : CA;
1.4645 - %}
1.4646 -
1.4647 - //No.22 Floating div operation : dst <-- reg1 div reg2
1.4648 - pipe_class fpu_div(regF dst, regF src1, regF src2) %{
1.4649 - src1 : RD(read);
1.4650 - src2 : RD(read);
1.4651 - dst : WB(write);
1.4652 - DECODE : ID;
1.4653 - FPU2 : CA;
1.4654 - %}
1.4655 -
1.4656 - pipe_class fcvt_I2D(regD dst, mRegI src) %{
1.4657 - src : RD(read);
1.4658 - dst : WB(write);
1.4659 - DECODE : ID;
1.4660 - FPU1 : CA;
1.4661 - %}
1.4662 -
1.4663 - pipe_class fcvt_D2I(mRegI dst, regD src) %{
1.4664 - src : RD(read);
1.4665 - dst : WB(write);
1.4666 - DECODE : ID;
1.4667 - FPU1 : CA;
1.4668 - %}
1.4669 -
1.4670 - pipe_class pipe_mfc1(mRegI dst, regD src) %{
1.4671 - src : RD(read);
1.4672 - dst : WB(write);
1.4673 - DECODE : ID;
1.4674 - MEM : RD;
1.4675 - %}
1.4676 -
1.4677 - pipe_class pipe_mtc1(regD dst, mRegI src) %{
1.4678 - src : RD(read);
1.4679 - dst : WB(write);
1.4680 - DECODE : ID;
1.4681 - MEM : RD(5);
1.4682 - %}
1.4683 -
1.4684 - //No.23 Floating sqrt operation : dst <-- reg1 sqrt reg2
1.4685 - pipe_class fpu_sqrt(regF dst, regF src1, regF src2) %{
1.4686 - multiple_bundles;
1.4687 - src1 : RD(read);
1.4688 - src2 : RD(read);
1.4689 - dst : WB(write);
1.4690 - DECODE : ID;
1.4691 - FPU2 : CA;
1.4692 - %}
1.4693 -
1.4694 - //No.11 Load Floating from Memory :
1.4695 - pipe_class fpu_loadF(regF dst, memory mem) %{
1.4696 - instruction_count(1);
1.4697 - mem : RD(read);
1.4698 - dst : WB(write)+3;
1.4699 - DECODE : ID;
1.4700 - MEM : RD;
1.4701 - %}
1.4702 -
1.4703 - //No.12 Store Floating to Memory :
1.4704 - pipe_class fpu_storeF(regF src, memory mem) %{
1.4705 - instruction_count(1);
1.4706 - mem : RD(read);
1.4707 - src : RD(read);
1.4708 - DECODE : ID;
1.4709 - MEM : RD;
1.4710 - %}
1.4711 -
1.4712 - //No.13 FPU Conditional branch :
1.4713 - pipe_class pipe_fpu_branch(regF src1, regF src2, label labl ) %{
1.4714 - multiple_bundles;
1.4715 - src1 : RD(read);
1.4716 - src2 : RD(read);
1.4717 - DECODE : ID;
1.4718 - BR : RD;
1.4719 - %}
1.4720 -
1.4721 -//No.14 Floating FPU reg operation : dst <-- op reg
1.4722 - pipe_class fpu1_regF(regF dst, regF src) %{
1.4723 - src : RD(read);
1.4724 - dst : WB(write);
1.4725 - DECODE : ID;
1.4726 - FPU : CA;
1.4727 - %}
1.4728 -
1.4729 - pipe_class long_memory_op() %{
1.4730 - instruction_count(10); multiple_bundles; force_serialization;
1.4731 - fixed_latency(30);
1.4732 - %}
1.4733 -
1.4734 - pipe_class simple_call() %{
1.4735 - instruction_count(10); multiple_bundles; force_serialization;
1.4736 - fixed_latency(200);
1.4737 - BR : RD;
1.4738 - %}
1.4739 -
1.4740 - pipe_class call() %{
1.4741 - instruction_count(10); multiple_bundles; force_serialization;
1.4742 - fixed_latency(200);
1.4743 - %}
1.4744 -
1.4745 - //FIXME:
1.4746 - //No.9 Piple slow : for multi-instructions
1.4747 - pipe_class pipe_slow( ) %{
1.4748 - instruction_count(20);
1.4749 - force_serialization;
1.4750 - multiple_bundles;
1.4751 - fixed_latency(50);
1.4752 - %}
1.4753 + //----------ATTRIBUTES---------------------------------------------------------
1.4754 + attributes %{
1.4755 + fixed_size_instructions; // Fixed size instructions
1.4756 + branch_has_delay_slot; // branch have delay slot in gs2
1.4757 + max_instructions_per_bundle = 1; // 1 instruction per bundle
1.4758 + max_bundles_per_cycle = 4; // Up to 4 bundles per cycle
1.4759 + bundle_unit_size=4;
1.4760 + instruction_unit_size = 4; // An instruction is 4 bytes long
1.4761 + instruction_fetch_unit_size = 16; // The processor fetches one line
1.4762 + instruction_fetch_units = 1; // of 16 bytes
1.4763 +
1.4764 + // List of nop instructions
1.4765 + nops( MachNop );
1.4766 + %}
1.4767 +
1.4768 + //----------RESOURCES----------------------------------------------------------
1.4769 + // Resources are the functional units available to the machine
1.4770 +
1.4771 + resources(D1, D2, D3, D4, DECODE = D1 | D2 | D3| D4, ALU1, ALU2, ALU = ALU1 | ALU2, FPU1, FPU2, FPU = FPU1 | FPU2, MEM, BR);
1.4772 +
1.4773 + //----------PIPELINE DESCRIPTION-----------------------------------------------
1.4774 + // Pipeline Description specifies the stages in the machine's pipeline
1.4775 +
1.4776 + // IF: fetch
1.4777 + // ID: decode
1.4778 + // RD: read
1.4779 + // CA: caculate
1.4780 + // WB: write back
1.4781 + // CM: commit
1.4782 +
1.4783 + pipe_desc(IF, ID, RD, CA, WB, CM);
1.4784 +
1.4785 +
1.4786 + //----------PIPELINE CLASSES---------------------------------------------------
1.4787 + // Pipeline Classes describe the stages in which input and output are
1.4788 + // referenced by the hardware pipeline.
1.4789 +
1.4790 + //No.1 Integer ALU reg-reg operation : dst <-- reg1 op reg2
1.4791 + pipe_class ialu_regI_regI(mRegI dst, mRegI src1, mRegI src2) %{
1.4792 + single_instruction;
1.4793 + src1 : RD(read);
1.4794 + src2 : RD(read);
1.4795 + dst : WB(write)+1;
1.4796 + DECODE : ID;
1.4797 + ALU : CA;
1.4798 + %}
1.4799 +
1.4800 + //No.19 Integer mult operation : dst <-- reg1 mult reg2
1.4801 + pipe_class ialu_mult(mRegI dst, mRegI src1, mRegI src2) %{
1.4802 + src1 : RD(read);
1.4803 + src2 : RD(read);
1.4804 + dst : WB(write)+5;
1.4805 + DECODE : ID;
1.4806 + ALU2 : CA;
1.4807 + %}
1.4808 +
1.4809 + pipe_class mulL_reg_reg(mRegL dst, mRegL src1, mRegL src2) %{
1.4810 + src1 : RD(read);
1.4811 + src2 : RD(read);
1.4812 + dst : WB(write)+10;
1.4813 + DECODE : ID;
1.4814 + ALU2 : CA;
1.4815 + %}
1.4816 +
1.4817 + //No.19 Integer div operation : dst <-- reg1 div reg2
1.4818 + pipe_class ialu_div(mRegI dst, mRegI src1, mRegI src2) %{
1.4819 + src1 : RD(read);
1.4820 + src2 : RD(read);
1.4821 + dst : WB(write)+10;
1.4822 + DECODE : ID;
1.4823 + ALU2 : CA;
1.4824 + %}
1.4825 +
1.4826 + //No.19 Integer mod operation : dst <-- reg1 mod reg2
1.4827 + pipe_class ialu_mod(mRegI dst, mRegI src1, mRegI src2) %{
1.4828 + instruction_count(2);
1.4829 + src1 : RD(read);
1.4830 + src2 : RD(read);
1.4831 + dst : WB(write)+10;
1.4832 + DECODE : ID;
1.4833 + ALU2 : CA;
1.4834 + %}
1.4835 +
1.4836 + //No.15 Long ALU reg-reg operation : dst <-- reg1 op reg2
1.4837 + pipe_class ialu_regL_regL(mRegL dst, mRegL src1, mRegL src2) %{
1.4838 + instruction_count(2);
1.4839 + src1 : RD(read);
1.4840 + src2 : RD(read);
1.4841 + dst : WB(write);
1.4842 + DECODE : ID;
1.4843 + ALU : CA;
1.4844 + %}
1.4845 +
1.4846 + //No.18 Long ALU reg-imm16 operation : dst <-- reg1 op imm16
1.4847 + pipe_class ialu_regL_imm16(mRegL dst, mRegL src) %{
1.4848 + instruction_count(2);
1.4849 + src : RD(read);
1.4850 + dst : WB(write);
1.4851 + DECODE : ID;
1.4852 + ALU : CA;
1.4853 + %}
1.4854 +
1.4855 + //no.16 load Long from memory :
1.4856 + pipe_class ialu_loadL(mRegL dst, memory mem) %{
1.4857 + instruction_count(2);
1.4858 + mem : RD(read);
1.4859 + dst : WB(write)+5;
1.4860 + DECODE : ID;
1.4861 + MEM : RD;
1.4862 + %}
1.4863 +
1.4864 + //No.17 Store Long to Memory :
1.4865 + pipe_class ialu_storeL(mRegL src, memory mem) %{
1.4866 + instruction_count(2);
1.4867 + mem : RD(read);
1.4868 + src : RD(read);
1.4869 + DECODE : ID;
1.4870 + MEM : RD;
1.4871 + %}
1.4872 +
1.4873 + //No.2 Integer ALU reg-imm16 operation : dst <-- reg1 op imm16
1.4874 + pipe_class ialu_regI_imm16(mRegI dst, mRegI src) %{
1.4875 + single_instruction;
1.4876 + src : RD(read);
1.4877 + dst : WB(write);
1.4878 + DECODE : ID;
1.4879 + ALU : CA;
1.4880 + %}
1.4881 +
1.4882 + //No.3 Integer move operation : dst <-- reg
1.4883 + pipe_class ialu_regI_mov(mRegI dst, mRegI src) %{
1.4884 + src : RD(read);
1.4885 + dst : WB(write);
1.4886 + DECODE : ID;
1.4887 + ALU : CA;
1.4888 + %}
1.4889 +
1.4890 + //No.4 No instructions : do nothing
1.4891 + pipe_class empty( ) %{
1.4892 + instruction_count(0);
1.4893 + %}
1.4894 +
1.4895 + //No.5 UnConditional branch :
1.4896 + pipe_class pipe_jump( label labl ) %{
1.4897 + multiple_bundles;
1.4898 + DECODE : ID;
1.4899 + BR : RD;
1.4900 + %}
1.4901 +
1.4902 + //No.6 ALU Conditional branch :
1.4903 + pipe_class pipe_alu_branch(mRegI src1, mRegI src2, label labl ) %{
1.4904 + multiple_bundles;
1.4905 + src1 : RD(read);
1.4906 + src2 : RD(read);
1.4907 + DECODE : ID;
1.4908 + BR : RD;
1.4909 + %}
1.4910 +
1.4911 + //no.7 load integer from memory :
1.4912 + pipe_class ialu_loadI(mRegI dst, memory mem) %{
1.4913 + mem : RD(read);
1.4914 + dst : WB(write)+3;
1.4915 + DECODE : ID;
1.4916 + MEM : RD;
1.4917 + %}
1.4918 +
1.4919 + //No.8 Store Integer to Memory :
1.4920 + pipe_class ialu_storeI(mRegI src, memory mem) %{
1.4921 + mem : RD(read);
1.4922 + src : RD(read);
1.4923 + DECODE : ID;
1.4924 + MEM : RD;
1.4925 + %}
1.4926 +
1.4927 +
1.4928 + //No.10 Floating FPU reg-reg operation : dst <-- reg1 op reg2
1.4929 + pipe_class fpu_regF_regF(regF dst, regF src1, regF src2) %{
1.4930 + src1 : RD(read);
1.4931 + src2 : RD(read);
1.4932 + dst : WB(write);
1.4933 + DECODE : ID;
1.4934 + FPU : CA;
1.4935 + %}
1.4936 +
1.4937 + //No.22 Floating div operation : dst <-- reg1 div reg2
1.4938 + pipe_class fpu_div(regF dst, regF src1, regF src2) %{
1.4939 + src1 : RD(read);
1.4940 + src2 : RD(read);
1.4941 + dst : WB(write);
1.4942 + DECODE : ID;
1.4943 + FPU2 : CA;
1.4944 + %}
1.4945 +
1.4946 + pipe_class fcvt_I2D(regD dst, mRegI src) %{
1.4947 + src : RD(read);
1.4948 + dst : WB(write);
1.4949 + DECODE : ID;
1.4950 + FPU1 : CA;
1.4951 + %}
1.4952 +
1.4953 + pipe_class fcvt_D2I(mRegI dst, regD src) %{
1.4954 + src : RD(read);
1.4955 + dst : WB(write);
1.4956 + DECODE : ID;
1.4957 + FPU1 : CA;
1.4958 + %}
1.4959 +
1.4960 + pipe_class pipe_mfc1(mRegI dst, regD src) %{
1.4961 + src : RD(read);
1.4962 + dst : WB(write);
1.4963 + DECODE : ID;
1.4964 + MEM : RD;
1.4965 + %}
1.4966 +
1.4967 + pipe_class pipe_mtc1(regD dst, mRegI src) %{
1.4968 + src : RD(read);
1.4969 + dst : WB(write);
1.4970 + DECODE : ID;
1.4971 + MEM : RD(5);
1.4972 + %}
1.4973 +
1.4974 + //No.23 Floating sqrt operation : dst <-- reg1 sqrt reg2
1.4975 + pipe_class fpu_sqrt(regF dst, regF src1, regF src2) %{
1.4976 + multiple_bundles;
1.4977 + src1 : RD(read);
1.4978 + src2 : RD(read);
1.4979 + dst : WB(write);
1.4980 + DECODE : ID;
1.4981 + FPU2 : CA;
1.4982 + %}
1.4983 +
1.4984 + //No.11 Load Floating from Memory :
1.4985 + pipe_class fpu_loadF(regF dst, memory mem) %{
1.4986 + instruction_count(1);
1.4987 + mem : RD(read);
1.4988 + dst : WB(write)+3;
1.4989 + DECODE : ID;
1.4990 + MEM : RD;
1.4991 + %}
1.4992 +
1.4993 + //No.12 Store Floating to Memory :
1.4994 + pipe_class fpu_storeF(regF src, memory mem) %{
1.4995 + instruction_count(1);
1.4996 + mem : RD(read);
1.4997 + src : RD(read);
1.4998 + DECODE : ID;
1.4999 + MEM : RD;
1.5000 + %}
1.5001 +
1.5002 + //No.13 FPU Conditional branch :
1.5003 + pipe_class pipe_fpu_branch(regF src1, regF src2, label labl ) %{
1.5004 + multiple_bundles;
1.5005 + src1 : RD(read);
1.5006 + src2 : RD(read);
1.5007 + DECODE : ID;
1.5008 + BR : RD;
1.5009 + %}
1.5010 +
1.5011 +//No.14 Floating FPU reg operation : dst <-- op reg
1.5012 + pipe_class fpu1_regF(regF dst, regF src) %{
1.5013 + src : RD(read);
1.5014 + dst : WB(write);
1.5015 + DECODE : ID;
1.5016 + FPU : CA;
1.5017 + %}
1.5018 +
1.5019 + pipe_class long_memory_op() %{
1.5020 + instruction_count(10); multiple_bundles; force_serialization;
1.5021 + fixed_latency(30);
1.5022 + %}
1.5023 +
1.5024 + pipe_class simple_call() %{
1.5025 + instruction_count(10); multiple_bundles; force_serialization;
1.5026 + fixed_latency(200);
1.5027 + BR : RD;
1.5028 + %}
1.5029 +
1.5030 + pipe_class call() %{
1.5031 + instruction_count(10); multiple_bundles; force_serialization;
1.5032 + fixed_latency(200);
1.5033 + %}
1.5034 +
1.5035 + //FIXME:
1.5036 + //No.9 Piple slow : for multi-instructions
1.5037 + pipe_class pipe_slow( ) %{
1.5038 + instruction_count(20);
1.5039 + force_serialization;
1.5040 + multiple_bundles;
1.5041 + fixed_latency(50);
1.5042 + %}
1.5043
1.5044 %}
1.5045
1.5046
1.5047
1.5048 //----------INSTRUCTIONS-------------------------------------------------------
1.5049 -//
1.5050 -// match -- States which machine-independent subtree may be replaced
1.5051 +//
1.5052 +// match -- States which machine-independent subtree may be replaced
1.5053 // by this instruction.
1.5054 // ins_cost -- The estimated cost of this instruction is used by instruction
1.5055 -// selection to identify a minimum cost tree of machine
1.5056 -// instructions that matches a tree of machine-independent
1.5057 +// selection to identify a minimum cost tree of machine
1.5058 +// instructions that matches a tree of machine-independent
1.5059 // instructions.
1.5060 // format -- A string providing the disassembly for this instruction.
1.5061 -// The value of an instruction's operand may be inserted
1.5062 +// The value of an instruction's operand may be inserted
1.5063 // by referring to it with a '$' prefix.
1.5064 -// opcode -- Three instruction opcodes may be provided. These are referred
1.5065 +// opcode -- Three instruction opcodes may be provided. These are referred
1.5066 // to within an encode class as $primary, $secondary, and $tertiary
1.5067 -// respectively. The primary opcode is commonly used to
1.5068 -// indicate the type of machine instruction, while secondary
1.5069 -// and tertiary are often used for prefix options or addressing
1.5070 +// respectively. The primary opcode is commonly used to
1.5071 +// indicate the type of machine instruction, while secondary
1.5072 +// and tertiary are often used for prefix options or addressing
1.5073 // modes.
1.5074 // ins_encode -- A list of encode classes with parameters. The encode class
1.5075 // name must have been defined in an 'enc_class' specification
1.5076 @@ -5957,7 +5931,7 @@
1.5077 match(Set dst (LoadI mem));
1.5078
1.5079 ins_cost(125);
1.5080 - format %{ "lw $dst, $mem #@loadI" %}
1.5081 + format %{ "lw $dst, $mem #@loadI" %}
1.5082 ins_encode (load_I_enc(dst, mem));
1.5083 ins_pipe( ialu_loadI );
1.5084 %}
1.5085 @@ -5966,7 +5940,7 @@
1.5086 match(Set dst (ConvI2L (LoadI mem)));
1.5087
1.5088 ins_cost(125);
1.5089 - format %{ "lw $dst, $mem #@loadI_convI2L" %}
1.5090 + format %{ "lw $dst, $mem #@loadI_convI2L" %}
1.5091 ins_encode (load_I_enc(dst, mem));
1.5092 ins_pipe( ialu_loadI );
1.5093 %}
1.5094 @@ -6246,7 +6220,7 @@
1.5095
1.5096 ins_cost(125); // XXX
1.5097 format %{ "sw $mem, $src\t# compressed ptr @ storeN" %}
1.5098 - ins_encode(store_N_reg_enc(mem, src));
1.5099 + ins_encode(store_N_reg_enc(mem, src));
1.5100 ins_pipe( ialu_storeI );
1.5101 %}
1.5102
1.5103 @@ -6257,7 +6231,7 @@
1.5104
1.5105 ins_cost(125); // XXX
1.5106 format %{ "sw $mem, $src\t# @ storeP2N" %}
1.5107 - ins_encode(store_N_reg_enc(mem, src));
1.5108 + ins_encode(store_N_reg_enc(mem, src));
1.5109 ins_pipe( ialu_storeI );
1.5110 %}
1.5111
1.5112 @@ -6428,17 +6402,17 @@
1.5113 long* value = (long*)$src$$constant;
1.5114
1.5115 if($src->constant_reloc() == relocInfo::metadata_type){
1.5116 - int klass_index = __ oop_recorder()->find_index((Klass*)value);
1.5117 - RelocationHolder rspec = metadata_Relocation::spec(klass_index);
1.5118 -
1.5119 - __ relocate(rspec);
1.5120 - __ patchable_set48(dst, (long)value);
1.5121 + int klass_index = __ oop_recorder()->find_index((Klass*)value);
1.5122 + RelocationHolder rspec = metadata_Relocation::spec(klass_index);
1.5123 +
1.5124 + __ relocate(rspec);
1.5125 + __ patchable_set48(dst, (long)value);
1.5126 }else if($src->constant_reloc() == relocInfo::oop_type){
1.5127 - int oop_index = __ oop_recorder()->find_index((jobject)value);
1.5128 - RelocationHolder rspec = oop_Relocation::spec(oop_index);
1.5129 -
1.5130 - __ relocate(rspec);
1.5131 - __ patchable_set48(dst, (long)value);
1.5132 + int oop_index = __ oop_recorder()->find_index((jobject)value);
1.5133 + RelocationHolder rspec = oop_Relocation::spec(oop_index);
1.5134 +
1.5135 + __ relocate(rspec);
1.5136 + __ patchable_set48(dst, (long)value);
1.5137 } else if ($src->constant_reloc() == relocInfo::none) {
1.5138 __ set64(dst, (long)value);
1.5139 }
1.5140 @@ -6507,7 +6481,7 @@
1.5141
1.5142 instruct loadConP0(mRegP dst, immP0 src)
1.5143 %{
1.5144 - match(Set dst src);
1.5145 + match(Set dst src);
1.5146
1.5147 ins_cost(50);
1.5148 format %{ "mov $dst, R0\t# ptr" %}
1.5149 @@ -6641,7 +6615,7 @@
1.5150 0x2d3bf354: lw s2, 0xffffcc80(at)
1.5151
1.5152 0x2d3bf358: lw s0, 0x0(sp)
1.5153 - 0x2d3bf35c: sw s0, 0x118(s2) // last_sp -> threa
1.5154 + 0x2d3bf35c: sw s0, 0x118(s2) // last_sp -> threa
1.5155 0x2d3bf360: sw s2, 0xc(sp)
1.5156
1.5157 ; OptoRuntime::rethrow_C(oopDesc* exception, JavaThread* thread, address ret_pc)
1.5158 @@ -6654,12 +6628,12 @@
1.5159 0x2d3bf378: jalr t9
1.5160 0x2d3bf37c: nop
1.5161
1.5162 - 0x2d3bf380: addu s3, v0, zero ; S3: SharedRuntime::raw_exception_handler_for_return_address()
1.5163 + 0x2d3bf380: addu s3, v0, zero ; S3: SharedRuntime::raw_exception_handler_for_return_address()
1.5164
1.5165 0x2d3bf384: lw s0, 0xc(sp)
1.5166 0x2d3bf388: sw zero, 0x118(s0)
1.5167 0x2d3bf38c: sw zero, 0x11c(s0)
1.5168 - 0x2d3bf390: lw s1, 0x144(s0) ; ex_oop: S1
1.5169 + 0x2d3bf390: lw s1, 0x144(s0) ; ex_oop: S1
1.5170 0x2d3bf394: addu s2, s0, zero
1.5171 0x2d3bf398: sw zero, 0x144(s2)
1.5172 0x2d3bf39c: lw s0, 0x4(s2)
1.5173 @@ -6679,7 +6653,7 @@
1.5174 0x2d3bf3cc: jr s3
1.5175 0x2d3bf3d0: nop
1.5176 ; Exception:
1.5177 - 0x2d3bf3d4: lui s1, 0x2cc8 ; generate_forward_exception()
1.5178 + 0x2d3bf3d4: lui s1, 0x2cc8 ; generate_forward_exception()
1.5179 0x2d3bf3d8: addiu s1, s1, 0x40
1.5180 0x2d3bf3dc: addiu s2, zero, 0x0
1.5181 0x2d3bf3e0: addiu sp, sp, 0x10
1.5182 @@ -6688,8 +6662,8 @@
1.5183 0x2d3bf3ec: lw fp, 0xfffffff8(sp)
1.5184 0x2d3bf3f0: lui at, 0x2b48
1.5185 0x2d3bf3f4: lw at, 0x100(at)
1.5186 -; TailCalljmpInd
1.5187 - __ push(RA); ; to be used in generate_forward_exception()
1.5188 +; TailCalljmpInd
1.5189 + __ push(RA); ; to be used in generate_forward_exception()
1.5190 0x2d3bf3f8: addu t7, s2, zero
1.5191 0x2d3bf3fc: jr s1
1.5192 0x2d3bf400: nop
1.5193 @@ -6728,23 +6702,22 @@
1.5194 Label &L = *($labl$$label);
1.5195 int flag = $cmp$$cmpcode;
1.5196
1.5197 - switch(flag)
1.5198 - {
1.5199 + switch(flag) {
1.5200 case 0x01: //equal
1.5201 - if (&L)
1.5202 - __ beq(op1, op2, L);
1.5203 - else
1.5204 - __ beq(op1, op2, (int)0);
1.5205 + if (&L)
1.5206 + __ beq(op1, op2, L);
1.5207 + else
1.5208 + __ beq(op1, op2, (int)0);
1.5209 break;
1.5210 case 0x02: //not_equal
1.5211 - if (&L)
1.5212 - __ bne(op1, op2, L);
1.5213 - else
1.5214 - __ bne(op1, op2, (int)0);
1.5215 + if (&L)
1.5216 + __ bne(op1, op2, L);
1.5217 + else
1.5218 + __ bne(op1, op2, (int)0);
1.5219 break;
1.5220 default:
1.5221 - Unimplemented();
1.5222 - }
1.5223 + Unimplemented();
1.5224 + }
1.5225 __ nop();
1.5226 %}
1.5227
1.5228 @@ -6769,20 +6742,20 @@
1.5229 switch(flag)
1.5230 {
1.5231 case 0x01: //equal
1.5232 - if (&L)
1.5233 - __ beq(op1, op2, L);
1.5234 - else
1.5235 - __ beq(op1, op2, (int)0);
1.5236 + if (&L)
1.5237 + __ beq(op1, op2, L);
1.5238 + else
1.5239 + __ beq(op1, op2, (int)0);
1.5240 break;
1.5241 case 0x02: //not_equal
1.5242 - if (&L)
1.5243 - __ bne(op1, op2, L);
1.5244 - else
1.5245 - __ bne(op1, op2, (int)0);
1.5246 + if (&L)
1.5247 + __ bne(op1, op2, L);
1.5248 + else
1.5249 + __ bne(op1, op2, (int)0);
1.5250 break;
1.5251 default:
1.5252 - Unimplemented();
1.5253 - }
1.5254 + Unimplemented();
1.5255 + }
1.5256 __ nop();
1.5257 %}
1.5258
1.5259 @@ -6805,51 +6778,50 @@
1.5260 Label &L = *($labl$$label);
1.5261 int flag = $cmp$$cmpcode;
1.5262
1.5263 - switch(flag)
1.5264 - {
1.5265 + switch(flag) {
1.5266 case 0x01: //equal
1.5267 - if (&L)
1.5268 - __ beq(op1, op2, L);
1.5269 - else
1.5270 - __ beq(op1, op2, (int)0);
1.5271 + if (&L)
1.5272 + __ beq(op1, op2, L);
1.5273 + else
1.5274 + __ beq(op1, op2, (int)0);
1.5275 break;
1.5276 case 0x02: //not_equal
1.5277 - if (&L)
1.5278 - __ bne(op1, op2, L);
1.5279 - else
1.5280 - __ bne(op1, op2, (int)0);
1.5281 + if (&L)
1.5282 + __ bne(op1, op2, L);
1.5283 + else
1.5284 + __ bne(op1, op2, (int)0);
1.5285 break;
1.5286 case 0x03: //above
1.5287 __ sltu(AT, op2, op1);
1.5288 if(&L)
1.5289 - __ bne(R0, AT, L);
1.5290 + __ bne(R0, AT, L);
1.5291 else
1.5292 __ bne(R0, AT, (int)0);
1.5293 break;
1.5294 case 0x04: //above_equal
1.5295 __ sltu(AT, op1, op2);
1.5296 if(&L)
1.5297 - __ beq(AT, R0, L);
1.5298 - else
1.5299 - __ beq(AT, R0, (int)0);
1.5300 + __ beq(AT, R0, L);
1.5301 + else
1.5302 + __ beq(AT, R0, (int)0);
1.5303 break;
1.5304 case 0x05: //below
1.5305 __ sltu(AT, op1, op2);
1.5306 if(&L)
1.5307 - __ bne(R0, AT, L);
1.5308 - else
1.5309 - __ bne(R0, AT, (int)0);
1.5310 + __ bne(R0, AT, L);
1.5311 + else
1.5312 + __ bne(R0, AT, (int)0);
1.5313 break;
1.5314 case 0x06: //below_equal
1.5315 __ sltu(AT, op2, op1);
1.5316 if(&L)
1.5317 - __ beq(AT, R0, L);
1.5318 - else
1.5319 - __ beq(AT, R0, (int)0);
1.5320 + __ beq(AT, R0, L);
1.5321 + else
1.5322 + __ beq(AT, R0, (int)0);
1.5323 break;
1.5324 default:
1.5325 Unimplemented();
1.5326 - }
1.5327 + }
1.5328 __ nop();
1.5329 %}
1.5330
1.5331 @@ -6870,23 +6842,22 @@
1.5332 Label &L = *($labl$$label);
1.5333 int flag = $cmp$$cmpcode;
1.5334
1.5335 - switch(flag)
1.5336 - {
1.5337 - case 0x01: //equal
1.5338 - if (&L)
1.5339 - __ beq(op1, op2, L);
1.5340 - else
1.5341 - __ beq(op1, op2, (int)0);
1.5342 - break;
1.5343 - case 0x02: //not_equal
1.5344 - if (&L)
1.5345 - __ bne(op1, op2, L);
1.5346 - else
1.5347 - __ bne(op1, op2, (int)0);
1.5348 - break;
1.5349 - default:
1.5350 + switch(flag) {
1.5351 + case 0x01: //equal
1.5352 + if (&L)
1.5353 + __ beq(op1, op2, L);
1.5354 + else
1.5355 + __ beq(op1, op2, (int)0);
1.5356 + break;
1.5357 + case 0x02: //not_equal
1.5358 + if (&L)
1.5359 + __ bne(op1, op2, L);
1.5360 + else
1.5361 + __ bne(op1, op2, (int)0);
1.5362 + break;
1.5363 + default:
1.5364 Unimplemented();
1.5365 - }
1.5366 + }
1.5367 __ nop();
1.5368 %}
1.5369 //TODO: pipe_branchP or create pipe_branchN LEE
1.5370 @@ -6907,51 +6878,50 @@
1.5371 Label &L = *($labl$$label);
1.5372 int flag = $cmp$$cmpcode;
1.5373
1.5374 - switch(flag)
1.5375 - {
1.5376 - case 0x01: //equal
1.5377 - if (&L)
1.5378 - __ beq(op1_reg, op2_reg, L);
1.5379 - else
1.5380 - __ beq(op1_reg, op2_reg, (int)0);
1.5381 - break;
1.5382 - case 0x02: //not_equal
1.5383 - if (&L)
1.5384 - __ bne(op1_reg, op2_reg, L);
1.5385 - else
1.5386 - __ bne(op1_reg, op2_reg, (int)0);
1.5387 - break;
1.5388 - case 0x03: //above
1.5389 - __ sltu(AT, op2_reg, op1_reg);
1.5390 - if(&L)
1.5391 - __ bne(R0, AT, L);
1.5392 - else
1.5393 - __ bne(R0, AT, (int)0);
1.5394 - break;
1.5395 - case 0x04: //above_equal
1.5396 - __ sltu(AT, op1_reg, op2_reg);
1.5397 - if(&L)
1.5398 - __ beq(AT, R0, L);
1.5399 - else
1.5400 - __ beq(AT, R0, (int)0);
1.5401 - break;
1.5402 - case 0x05: //below
1.5403 - __ sltu(AT, op1_reg, op2_reg);
1.5404 - if(&L)
1.5405 - __ bne(R0, AT, L);
1.5406 - else
1.5407 - __ bne(R0, AT, (int)0);
1.5408 - break;
1.5409 - case 0x06: //below_equal
1.5410 - __ sltu(AT, op2_reg, op1_reg);
1.5411 - if(&L)
1.5412 - __ beq(AT, R0, L);
1.5413 - else
1.5414 - __ beq(AT, R0, (int)0);
1.5415 - break;
1.5416 - default:
1.5417 - Unimplemented();
1.5418 - }
1.5419 + switch(flag) {
1.5420 + case 0x01: //equal
1.5421 + if (&L)
1.5422 + __ beq(op1_reg, op2_reg, L);
1.5423 + else
1.5424 + __ beq(op1_reg, op2_reg, (int)0);
1.5425 + break;
1.5426 + case 0x02: //not_equal
1.5427 + if (&L)
1.5428 + __ bne(op1_reg, op2_reg, L);
1.5429 + else
1.5430 + __ bne(op1_reg, op2_reg, (int)0);
1.5431 + break;
1.5432 + case 0x03: //above
1.5433 + __ sltu(AT, op2_reg, op1_reg);
1.5434 + if(&L)
1.5435 + __ bne(R0, AT, L);
1.5436 + else
1.5437 + __ bne(R0, AT, (int)0);
1.5438 + break;
1.5439 + case 0x04: //above_equal
1.5440 + __ sltu(AT, op1_reg, op2_reg);
1.5441 + if(&L)
1.5442 + __ beq(AT, R0, L);
1.5443 + else
1.5444 + __ beq(AT, R0, (int)0);
1.5445 + break;
1.5446 + case 0x05: //below
1.5447 + __ sltu(AT, op1_reg, op2_reg);
1.5448 + if(&L)
1.5449 + __ bne(R0, AT, L);
1.5450 + else
1.5451 + __ bne(R0, AT, (int)0);
1.5452 + break;
1.5453 + case 0x06: //below_equal
1.5454 + __ sltu(AT, op2_reg, op1_reg);
1.5455 + if(&L)
1.5456 + __ beq(AT, R0, L);
1.5457 + else
1.5458 + __ beq(AT, R0, (int)0);
1.5459 + break;
1.5460 + default:
1.5461 + Unimplemented();
1.5462 + }
1.5463 __ nop();
1.5464 %}
1.5465 ins_pc_relative(1);
1.5466 @@ -6969,51 +6939,50 @@
1.5467 Label &L = *($labl$$label);
1.5468 int flag = $cmp$$cmpcode;
1.5469
1.5470 - switch(flag)
1.5471 - {
1.5472 + switch(flag) {
1.5473 case 0x01: //equal
1.5474 - if (&L)
1.5475 - __ beq(op1, op2, L);
1.5476 - else
1.5477 - __ beq(op1, op2, (int)0);
1.5478 + if (&L)
1.5479 + __ beq(op1, op2, L);
1.5480 + else
1.5481 + __ beq(op1, op2, (int)0);
1.5482 break;
1.5483 case 0x02: //not_equal
1.5484 - if (&L)
1.5485 - __ bne(op1, op2, L);
1.5486 - else
1.5487 - __ bne(op1, op2, (int)0);
1.5488 + if (&L)
1.5489 + __ bne(op1, op2, L);
1.5490 + else
1.5491 + __ bne(op1, op2, (int)0);
1.5492 break;
1.5493 case 0x03: //above
1.5494 __ sltu(AT, op2, op1);
1.5495 if(&L)
1.5496 - __ bne(AT, R0, L);
1.5497 + __ bne(AT, R0, L);
1.5498 else
1.5499 __ bne(AT, R0, (int)0);
1.5500 break;
1.5501 case 0x04: //above_equal
1.5502 __ sltu(AT, op1, op2);
1.5503 if(&L)
1.5504 - __ beq(AT, R0, L);
1.5505 + __ beq(AT, R0, L);
1.5506 else
1.5507 __ beq(AT, R0, (int)0);
1.5508 break;
1.5509 case 0x05: //below
1.5510 __ sltu(AT, op1, op2);
1.5511 if(&L)
1.5512 - __ bne(AT, R0, L);
1.5513 - else
1.5514 - __ bne(AT, R0, (int)0);
1.5515 + __ bne(AT, R0, L);
1.5516 + else
1.5517 + __ bne(AT, R0, (int)0);
1.5518 break;
1.5519 case 0x06: //below_equal
1.5520 __ sltu(AT, op2, op1);
1.5521 if(&L)
1.5522 - __ beq(AT, R0, L);
1.5523 - else
1.5524 - __ beq(AT, R0, (int)0);
1.5525 + __ beq(AT, R0, L);
1.5526 + else
1.5527 + __ beq(AT, R0, (int)0);
1.5528 break;
1.5529 default:
1.5530 - Unimplemented();
1.5531 - }
1.5532 + Unimplemented();
1.5533 + }
1.5534 __ nop();
1.5535 %}
1.5536
1.5537 @@ -7034,51 +7003,50 @@
1.5538 int flag = $cmp$$cmpcode;
1.5539
1.5540 __ move(AT, val);
1.5541 - switch(flag)
1.5542 - {
1.5543 + switch(flag) {
1.5544 case 0x01: //equal
1.5545 - if (&L)
1.5546 - __ beq(op1, AT, L);
1.5547 - else
1.5548 - __ beq(op1, AT, (int)0);
1.5549 + if (&L)
1.5550 + __ beq(op1, AT, L);
1.5551 + else
1.5552 + __ beq(op1, AT, (int)0);
1.5553 break;
1.5554 case 0x02: //not_equal
1.5555 - if (&L)
1.5556 - __ bne(op1, AT, L);
1.5557 - else
1.5558 - __ bne(op1, AT, (int)0);
1.5559 + if (&L)
1.5560 + __ bne(op1, AT, L);
1.5561 + else
1.5562 + __ bne(op1, AT, (int)0);
1.5563 break;
1.5564 case 0x03: //above
1.5565 __ sltu(AT, AT, op1);
1.5566 if(&L)
1.5567 - __ bne(R0, AT, L);
1.5568 + __ bne(R0, AT, L);
1.5569 else
1.5570 __ bne(R0, AT, (int)0);
1.5571 break;
1.5572 case 0x04: //above_equal
1.5573 __ sltu(AT, op1, AT);
1.5574 if(&L)
1.5575 - __ beq(AT, R0, L);
1.5576 + __ beq(AT, R0, L);
1.5577 else
1.5578 __ beq(AT, R0, (int)0);
1.5579 break;
1.5580 case 0x05: //below
1.5581 __ sltu(AT, op1, AT);
1.5582 if(&L)
1.5583 - __ bne(R0, AT, L);
1.5584 - else
1.5585 - __ bne(R0, AT, (int)0);
1.5586 + __ bne(R0, AT, L);
1.5587 + else
1.5588 + __ bne(R0, AT, (int)0);
1.5589 break;
1.5590 case 0x06: //below_equal
1.5591 __ sltu(AT, AT, op1);
1.5592 if(&L)
1.5593 - __ beq(AT, R0, L);
1.5594 - else
1.5595 - __ beq(AT, R0, (int)0);
1.5596 + __ beq(AT, R0, L);
1.5597 + else
1.5598 + __ beq(AT, R0, (int)0);
1.5599 break;
1.5600 default:
1.5601 - Unimplemented();
1.5602 - }
1.5603 + Unimplemented();
1.5604 + }
1.5605 __ nop();
1.5606 %}
1.5607
1.5608 @@ -7097,51 +7065,50 @@
1.5609 Label &L = *($labl$$label);
1.5610 int flag = $cmp$$cmpcode;
1.5611
1.5612 - switch(flag)
1.5613 - {
1.5614 + switch(flag) {
1.5615 case 0x01: //equal
1.5616 - if (&L)
1.5617 - __ beq(op1, op2, L);
1.5618 - else
1.5619 - __ beq(op1, op2, (int)0);
1.5620 + if (&L)
1.5621 + __ beq(op1, op2, L);
1.5622 + else
1.5623 + __ beq(op1, op2, (int)0);
1.5624 break;
1.5625 case 0x02: //not_equal
1.5626 - if (&L)
1.5627 - __ bne(op1, op2, L);
1.5628 - else
1.5629 - __ bne(op1, op2, (int)0);
1.5630 + if (&L)
1.5631 + __ bne(op1, op2, L);
1.5632 + else
1.5633 + __ bne(op1, op2, (int)0);
1.5634 break;
1.5635 case 0x03: //above
1.5636 __ slt(AT, op2, op1);
1.5637 if(&L)
1.5638 - __ bne(R0, AT, L);
1.5639 + __ bne(R0, AT, L);
1.5640 else
1.5641 __ bne(R0, AT, (int)0);
1.5642 break;
1.5643 case 0x04: //above_equal
1.5644 __ slt(AT, op1, op2);
1.5645 if(&L)
1.5646 - __ beq(AT, R0, L);
1.5647 + __ beq(AT, R0, L);
1.5648 else
1.5649 __ beq(AT, R0, (int)0);
1.5650 break;
1.5651 case 0x05: //below
1.5652 __ slt(AT, op1, op2);
1.5653 if(&L)
1.5654 - __ bne(R0, AT, L);
1.5655 - else
1.5656 - __ bne(R0, AT, (int)0);
1.5657 + __ bne(R0, AT, L);
1.5658 + else
1.5659 + __ bne(R0, AT, (int)0);
1.5660 break;
1.5661 case 0x06: //below_equal
1.5662 __ slt(AT, op2, op1);
1.5663 if(&L)
1.5664 - __ beq(AT, R0, L);
1.5665 - else
1.5666 - __ beq(AT, R0, (int)0);
1.5667 + __ beq(AT, R0, L);
1.5668 + else
1.5669 + __ beq(AT, R0, (int)0);
1.5670 break;
1.5671 default:
1.5672 - Unimplemented();
1.5673 - }
1.5674 + Unimplemented();
1.5675 + }
1.5676 __ nop();
1.5677 %}
1.5678
1.5679 @@ -7157,24 +7124,21 @@
1.5680
1.5681 ins_encode %{
1.5682 Register op1 = $src1$$Register;
1.5683 -// int val = $src2$$constant;
1.5684 Label &L = *($labl$$label);
1.5685 int flag = $cmp$$cmpcode;
1.5686
1.5687 - //__ move(AT, val);
1.5688 - switch(flag)
1.5689 - {
1.5690 + switch(flag) {
1.5691 case 0x01: //equal
1.5692 - if (&L)
1.5693 - __ beq(op1, R0, L);
1.5694 - else
1.5695 - __ beq(op1, R0, (int)0);
1.5696 + if (&L)
1.5697 + __ beq(op1, R0, L);
1.5698 + else
1.5699 + __ beq(op1, R0, (int)0);
1.5700 break;
1.5701 case 0x02: //not_equal
1.5702 - if (&L)
1.5703 - __ bne(op1, R0, L);
1.5704 - else
1.5705 - __ bne(op1, R0, (int)0);
1.5706 + if (&L)
1.5707 + __ bne(op1, R0, L);
1.5708 + else
1.5709 + __ bne(op1, R0, (int)0);
1.5710 break;
1.5711 case 0x03: //greater
1.5712 if(&L)
1.5713 @@ -7201,8 +7165,8 @@
1.5714 __ blez(op1, (int)0);
1.5715 break;
1.5716 default:
1.5717 - Unimplemented();
1.5718 - }
1.5719 + Unimplemented();
1.5720 + }
1.5721 __ nop();
1.5722 %}
1.5723
1.5724 @@ -7224,51 +7188,50 @@
1.5725 int flag = $cmp$$cmpcode;
1.5726
1.5727 __ move(AT, val);
1.5728 - switch(flag)
1.5729 - {
1.5730 + switch(flag) {
1.5731 case 0x01: //equal
1.5732 - if (&L)
1.5733 - __ beq(op1, AT, L);
1.5734 - else
1.5735 - __ beq(op1, AT, (int)0);
1.5736 + if (&L)
1.5737 + __ beq(op1, AT, L);
1.5738 + else
1.5739 + __ beq(op1, AT, (int)0);
1.5740 break;
1.5741 case 0x02: //not_equal
1.5742 - if (&L)
1.5743 - __ bne(op1, AT, L);
1.5744 - else
1.5745 - __ bne(op1, AT, (int)0);
1.5746 + if (&L)
1.5747 + __ bne(op1, AT, L);
1.5748 + else
1.5749 + __ bne(op1, AT, (int)0);
1.5750 break;
1.5751 case 0x03: //greater
1.5752 __ slt(AT, AT, op1);
1.5753 if(&L)
1.5754 - __ bne(R0, AT, L);
1.5755 + __ bne(R0, AT, L);
1.5756 else
1.5757 __ bne(R0, AT, (int)0);
1.5758 break;
1.5759 case 0x04: //greater_equal
1.5760 __ slt(AT, op1, AT);
1.5761 if(&L)
1.5762 - __ beq(AT, R0, L);
1.5763 + __ beq(AT, R0, L);
1.5764 else
1.5765 __ beq(AT, R0, (int)0);
1.5766 break;
1.5767 case 0x05: //less
1.5768 __ slt(AT, op1, AT);
1.5769 if(&L)
1.5770 - __ bne(R0, AT, L);
1.5771 - else
1.5772 - __ bne(R0, AT, (int)0);
1.5773 + __ bne(R0, AT, L);
1.5774 + else
1.5775 + __ bne(R0, AT, (int)0);
1.5776 break;
1.5777 case 0x06: //less_equal
1.5778 __ slt(AT, AT, op1);
1.5779 if(&L)
1.5780 - __ beq(AT, R0, L);
1.5781 - else
1.5782 - __ beq(AT, R0, (int)0);
1.5783 + __ beq(AT, R0, L);
1.5784 + else
1.5785 + __ beq(AT, R0, (int)0);
1.5786 break;
1.5787 default:
1.5788 Unimplemented();
1.5789 - }
1.5790 + }
1.5791 __ nop();
1.5792 %}
1.5793
1.5794 @@ -7286,46 +7249,45 @@
1.5795 Label &L = *($labl$$label);
1.5796 int flag = $cmp$$cmpcode;
1.5797
1.5798 - switch(flag)
1.5799 - {
1.5800 + switch(flag) {
1.5801 case 0x01: //equal
1.5802 - if (&L)
1.5803 - __ beq(op1, R0, L);
1.5804 - else
1.5805 - __ beq(op1, R0, (int)0);
1.5806 + if (&L)
1.5807 + __ beq(op1, R0, L);
1.5808 + else
1.5809 + __ beq(op1, R0, (int)0);
1.5810 break;
1.5811 case 0x02: //not_equal
1.5812 - if (&L)
1.5813 - __ bne(op1, R0, L);
1.5814 - else
1.5815 - __ bne(op1, R0, (int)0);
1.5816 + if (&L)
1.5817 + __ bne(op1, R0, L);
1.5818 + else
1.5819 + __ bne(op1, R0, (int)0);
1.5820 break;
1.5821 case 0x03: //above
1.5822 if(&L)
1.5823 - __ bne(R0, op1, L);
1.5824 - else
1.5825 - __ bne(R0, op1, (int)0);
1.5826 + __ bne(R0, op1, L);
1.5827 + else
1.5828 + __ bne(R0, op1, (int)0);
1.5829 break;
1.5830 case 0x04: //above_equal
1.5831 if(&L)
1.5832 - __ beq(R0, R0, L);
1.5833 - else
1.5834 - __ beq(R0, R0, (int)0);
1.5835 + __ beq(R0, R0, L);
1.5836 + else
1.5837 + __ beq(R0, R0, (int)0);
1.5838 break;
1.5839 case 0x05: //below
1.5840 return;
1.5841 break;
1.5842 case 0x06: //below_equal
1.5843 if(&L)
1.5844 - __ beq(op1, R0, L);
1.5845 - else
1.5846 - __ beq(op1, R0, (int)0);
1.5847 - break;
1.5848 + __ beq(op1, R0, L);
1.5849 + else
1.5850 + __ beq(op1, R0, (int)0);
1.5851 + break;
1.5852 default:
1.5853 - Unimplemented();
1.5854 - }
1.5855 + Unimplemented();
1.5856 + }
1.5857 __ nop();
1.5858 - %}
1.5859 + %}
1.5860
1.5861 ins_pc_relative(1);
1.5862 ins_pipe( pipe_alu_branch );
1.5863 @@ -7344,55 +7306,54 @@
1.5864 Label &L = *($labl$$label);
1.5865 int flag = $cmp$$cmpcode;
1.5866
1.5867 - switch(flag)
1.5868 - {
1.5869 + switch(flag) {
1.5870 case 0x01: //equal
1.5871 __ move(AT, val);
1.5872 - if (&L)
1.5873 - __ beq(op1, AT, L);
1.5874 - else
1.5875 - __ beq(op1, AT, (int)0);
1.5876 + if (&L)
1.5877 + __ beq(op1, AT, L);
1.5878 + else
1.5879 + __ beq(op1, AT, (int)0);
1.5880 break;
1.5881 case 0x02: //not_equal
1.5882 __ move(AT, val);
1.5883 - if (&L)
1.5884 - __ bne(op1, AT, L);
1.5885 - else
1.5886 - __ bne(op1, AT, (int)0);
1.5887 + if (&L)
1.5888 + __ bne(op1, AT, L);
1.5889 + else
1.5890 + __ bne(op1, AT, (int)0);
1.5891 break;
1.5892 case 0x03: //above
1.5893 __ move(AT, val);
1.5894 __ sltu(AT, AT, op1);
1.5895 if(&L)
1.5896 - __ bne(R0, AT, L);
1.5897 - else
1.5898 - __ bne(R0, AT, (int)0);
1.5899 + __ bne(R0, AT, L);
1.5900 + else
1.5901 + __ bne(R0, AT, (int)0);
1.5902 break;
1.5903 case 0x04: //above_equal
1.5904 __ sltiu(AT, op1, val);
1.5905 if(&L)
1.5906 - __ beq(AT, R0, L);
1.5907 - else
1.5908 - __ beq(AT, R0, (int)0);
1.5909 + __ beq(AT, R0, L);
1.5910 + else
1.5911 + __ beq(AT, R0, (int)0);
1.5912 break;
1.5913 case 0x05: //below
1.5914 __ sltiu(AT, op1, val);
1.5915 if(&L)
1.5916 - __ bne(R0, AT, L);
1.5917 - else
1.5918 - __ bne(R0, AT, (int)0);
1.5919 + __ bne(R0, AT, L);
1.5920 + else
1.5921 + __ bne(R0, AT, (int)0);
1.5922 break;
1.5923 case 0x06: //below_equal
1.5924 __ move(AT, val);
1.5925 __ sltu(AT, AT, op1);
1.5926 if(&L)
1.5927 - __ beq(AT, R0, L);
1.5928 - else
1.5929 - __ beq(AT, R0, (int)0);
1.5930 - break;
1.5931 + __ beq(AT, R0, L);
1.5932 + else
1.5933 + __ beq(AT, R0, (int)0);
1.5934 + break;
1.5935 default:
1.5936 - Unimplemented();
1.5937 - }
1.5938 + Unimplemented();
1.5939 + }
1.5940 __ nop();
1.5941 %}
1.5942
1.5943 @@ -7414,39 +7375,38 @@
1.5944 Label &target = *($labl$$label);
1.5945 int flag = $cmp$$cmpcode;
1.5946
1.5947 - switch(flag)
1.5948 - {
1.5949 + switch(flag) {
1.5950 case 0x01: //equal
1.5951 - if (&target)
1.5952 - __ beq(opr1_reg, opr2_reg, target);
1.5953 - else
1.5954 - __ beq(opr1_reg, opr2_reg, (int)0);
1.5955 + if (&target)
1.5956 + __ beq(opr1_reg, opr2_reg, target);
1.5957 + else
1.5958 + __ beq(opr1_reg, opr2_reg, (int)0);
1.5959 __ delayed()->nop();
1.5960 break;
1.5961
1.5962 case 0x02: //not_equal
1.5963 if(&target)
1.5964 - __ bne(opr1_reg, opr2_reg, target);
1.5965 - else
1.5966 - __ bne(opr1_reg, opr2_reg, (int)0);
1.5967 + __ bne(opr1_reg, opr2_reg, target);
1.5968 + else
1.5969 + __ bne(opr1_reg, opr2_reg, (int)0);
1.5970 __ delayed()->nop();
1.5971 break;
1.5972
1.5973 case 0x03: //greater
1.5974 __ slt(AT, opr2_reg, opr1_reg);
1.5975 if(&target)
1.5976 - __ bne(AT, R0, target);
1.5977 - else
1.5978 - __ bne(AT, R0, (int)0);
1.5979 + __ bne(AT, R0, target);
1.5980 + else
1.5981 + __ bne(AT, R0, (int)0);
1.5982 __ delayed()->nop();
1.5983 break;
1.5984
1.5985 case 0x04: //greater_equal
1.5986 __ slt(AT, opr1_reg, opr2_reg);
1.5987 if(&target)
1.5988 - __ beq(AT, R0, target);
1.5989 - else
1.5990 - __ beq(AT, R0, (int)0);
1.5991 + __ beq(AT, R0, target);
1.5992 + else
1.5993 + __ beq(AT, R0, (int)0);
1.5994 __ delayed()->nop();
1.5995
1.5996 break;
1.5997 @@ -7454,27 +7414,27 @@
1.5998 case 0x05: //less
1.5999 __ slt(AT, opr1_reg, opr2_reg);
1.6000 if(&target)
1.6001 - __ bne(AT, R0, target);
1.6002 - else
1.6003 - __ bne(AT, R0, (int)0);
1.6004 + __ bne(AT, R0, target);
1.6005 + else
1.6006 + __ bne(AT, R0, (int)0);
1.6007 __ delayed()->nop();
1.6008
1.6009 break;
1.6010
1.6011 case 0x06: //less_equal
1.6012 - __ slt(AT, opr2_reg, opr1_reg);
1.6013 -
1.6014 - if(&target)
1.6015 + __ slt(AT, opr2_reg, opr1_reg);
1.6016 +
1.6017 + if(&target)
1.6018 __ beq(AT, R0, target);
1.6019 - else
1.6020 + else
1.6021 __ beq(AT, R0, (int)0);
1.6022 - __ delayed()->nop();
1.6023 -
1.6024 - break;
1.6025 + __ delayed()->nop();
1.6026 +
1.6027 + break;
1.6028
1.6029 default:
1.6030 - Unimplemented();
1.6031 - }
1.6032 + Unimplemented();
1.6033 + }
1.6034 %}
1.6035
1.6036
1.6037 @@ -7494,10 +7454,9 @@
1.6038 Label &target = *($labl$$label);
1.6039 int flag = $cmp$$cmpcode;
1.6040
1.6041 - switch(flag)
1.6042 - {
1.6043 + switch(flag) {
1.6044 case 0x01: //equal
1.6045 - if (&target)
1.6046 + if (&target)
1.6047 __ beq(opr1_reg, R0, target);
1.6048 else
1.6049 __ beq(opr1_reg, R0, int(0));
1.6050 @@ -7533,7 +7492,7 @@
1.6051 break;
1.6052
1.6053 case 0x06: //less_equal
1.6054 - if (&target)
1.6055 + if (&target)
1.6056 __ blez(opr1_reg, target);
1.6057 else
1.6058 __ blez(opr1_reg, int(0));
1.6059 @@ -7541,8 +7500,8 @@
1.6060
1.6061 default:
1.6062 Unimplemented();
1.6063 - }
1.6064 - __ delayed()->nop();
1.6065 + }
1.6066 + __ delayed()->nop();
1.6067 %}
1.6068
1.6069
1.6070 @@ -7565,57 +7524,56 @@
1.6071
1.6072 __ set64(opr2_reg, $src2$$constant);
1.6073
1.6074 - switch(flag)
1.6075 - {
1.6076 + switch(flag) {
1.6077 case 0x01: //equal
1.6078 - if (&target)
1.6079 - __ beq(opr1_reg, opr2_reg, target);
1.6080 - else
1.6081 - __ beq(opr1_reg, opr2_reg, (int)0);
1.6082 + if (&target)
1.6083 + __ beq(opr1_reg, opr2_reg, target);
1.6084 + else
1.6085 + __ beq(opr1_reg, opr2_reg, (int)0);
1.6086 break;
1.6087
1.6088 case 0x02: //not_equal
1.6089 if(&target)
1.6090 - __ bne(opr1_reg, opr2_reg, target);
1.6091 - else
1.6092 - __ bne(opr1_reg, opr2_reg, (int)0);
1.6093 + __ bne(opr1_reg, opr2_reg, target);
1.6094 + else
1.6095 + __ bne(opr1_reg, opr2_reg, (int)0);
1.6096 break;
1.6097
1.6098 case 0x03: //greater
1.6099 __ slt(AT, opr2_reg, opr1_reg);
1.6100 if(&target)
1.6101 - __ bne(AT, R0, target);
1.6102 - else
1.6103 - __ bne(AT, R0, (int)0);
1.6104 + __ bne(AT, R0, target);
1.6105 + else
1.6106 + __ bne(AT, R0, (int)0);
1.6107 break;
1.6108
1.6109 case 0x04: //greater_equal
1.6110 __ slt(AT, opr1_reg, opr2_reg);
1.6111 if(&target)
1.6112 - __ beq(AT, R0, target);
1.6113 - else
1.6114 - __ beq(AT, R0, (int)0);
1.6115 + __ beq(AT, R0, target);
1.6116 + else
1.6117 + __ beq(AT, R0, (int)0);
1.6118 break;
1.6119
1.6120 case 0x05: //less
1.6121 __ slt(AT, opr1_reg, opr2_reg);
1.6122 if(&target)
1.6123 - __ bne(AT, R0, target);
1.6124 - else
1.6125 - __ bne(AT, R0, (int)0);
1.6126 + __ bne(AT, R0, target);
1.6127 + else
1.6128 + __ bne(AT, R0, (int)0);
1.6129 break;
1.6130
1.6131 case 0x06: //less_equal
1.6132 - __ slt(AT, opr2_reg, opr1_reg);
1.6133 - if(&target)
1.6134 + __ slt(AT, opr2_reg, opr1_reg);
1.6135 + if(&target)
1.6136 __ beq(AT, R0, target);
1.6137 - else
1.6138 + else
1.6139 __ beq(AT, R0, (int)0);
1.6140 - break;
1.6141 + break;
1.6142
1.6143 default:
1.6144 - Unimplemented();
1.6145 - }
1.6146 + Unimplemented();
1.6147 + }
1.6148 __ nop();
1.6149 %}
1.6150
1.6151 @@ -7637,53 +7595,52 @@
1.6152 Label &L = *($labl$$label);
1.6153 int flag = $cmp$$cmpcode;
1.6154
1.6155 - switch(flag)
1.6156 - {
1.6157 + switch(flag) {
1.6158 case 0x01: //equal
1.6159 __ c_eq_s(reg_op1, reg_op2);
1.6160 - if (&L)
1.6161 - __ bc1t(L);
1.6162 - else
1.6163 - __ bc1t((int)0);
1.6164 + if (&L)
1.6165 + __ bc1t(L);
1.6166 + else
1.6167 + __ bc1t((int)0);
1.6168 break;
1.6169 case 0x02: //not_equal
1.6170 __ c_eq_s(reg_op1, reg_op2);
1.6171 - if (&L)
1.6172 - __ bc1f(L);
1.6173 - else
1.6174 - __ bc1f((int)0);
1.6175 + if (&L)
1.6176 + __ bc1f(L);
1.6177 + else
1.6178 + __ bc1f((int)0);
1.6179 break;
1.6180 case 0x03: //greater
1.6181 __ c_ule_s(reg_op1, reg_op2);
1.6182 if(&L)
1.6183 - __ bc1f(L);
1.6184 - else
1.6185 - __ bc1f((int)0);
1.6186 + __ bc1f(L);
1.6187 + else
1.6188 + __ bc1f((int)0);
1.6189 break;
1.6190 case 0x04: //greater_equal
1.6191 __ c_ult_s(reg_op1, reg_op2);
1.6192 if(&L)
1.6193 - __ bc1f(L);
1.6194 - else
1.6195 - __ bc1f((int)0);
1.6196 + __ bc1f(L);
1.6197 + else
1.6198 + __ bc1f((int)0);
1.6199 break;
1.6200 case 0x05: //less
1.6201 __ c_ult_s(reg_op1, reg_op2);
1.6202 if(&L)
1.6203 - __ bc1t(L);
1.6204 - else
1.6205 - __ bc1t((int)0);
1.6206 + __ bc1t(L);
1.6207 + else
1.6208 + __ bc1t((int)0);
1.6209 break;
1.6210 case 0x06: //less_equal
1.6211 __ c_ule_s(reg_op1, reg_op2);
1.6212 if(&L)
1.6213 - __ bc1t(L);
1.6214 - else
1.6215 - __ bc1t((int)0);
1.6216 - break;
1.6217 + __ bc1t(L);
1.6218 + else
1.6219 + __ bc1t((int)0);
1.6220 + break;
1.6221 default:
1.6222 - Unimplemented();
1.6223 - }
1.6224 + Unimplemented();
1.6225 + }
1.6226 __ nop();
1.6227 %}
1.6228
1.6229 @@ -7702,54 +7659,53 @@
1.6230 Label &L = *($labl$$label);
1.6231 int flag = $cmp$$cmpcode;
1.6232
1.6233 - switch(flag)
1.6234 - {
1.6235 + switch(flag) {
1.6236 case 0x01: //equal
1.6237 __ c_eq_d(reg_op1, reg_op2);
1.6238 - if (&L)
1.6239 - __ bc1t(L);
1.6240 - else
1.6241 - __ bc1t((int)0);
1.6242 + if (&L)
1.6243 + __ bc1t(L);
1.6244 + else
1.6245 + __ bc1t((int)0);
1.6246 break;
1.6247 case 0x02: //not_equal
1.6248 -//2016/4/19 aoqi: c_ueq_d cannot distinguish NaN from equal. Double.isNaN(Double) is implemented by 'f != f', so the use of c_ueq_d causes bugs.
1.6249 + //2016/4/19 aoqi: c_ueq_d cannot distinguish NaN from equal. Double.isNaN(Double) is implemented by 'f != f', so the use of c_ueq_d causes bugs.
1.6250 __ c_eq_d(reg_op1, reg_op2);
1.6251 - if (&L)
1.6252 - __ bc1f(L);
1.6253 - else
1.6254 - __ bc1f((int)0);
1.6255 + if (&L)
1.6256 + __ bc1f(L);
1.6257 + else
1.6258 + __ bc1f((int)0);
1.6259 break;
1.6260 case 0x03: //greater
1.6261 __ c_ule_d(reg_op1, reg_op2);
1.6262 if(&L)
1.6263 - __ bc1f(L);
1.6264 - else
1.6265 - __ bc1f((int)0);
1.6266 + __ bc1f(L);
1.6267 + else
1.6268 + __ bc1f((int)0);
1.6269 break;
1.6270 case 0x04: //greater_equal
1.6271 __ c_ult_d(reg_op1, reg_op2);
1.6272 if(&L)
1.6273 - __ bc1f(L);
1.6274 - else
1.6275 - __ bc1f((int)0);
1.6276 + __ bc1f(L);
1.6277 + else
1.6278 + __ bc1f((int)0);
1.6279 break;
1.6280 case 0x05: //less
1.6281 __ c_ult_d(reg_op1, reg_op2);
1.6282 if(&L)
1.6283 - __ bc1t(L);
1.6284 - else
1.6285 - __ bc1t((int)0);
1.6286 + __ bc1t(L);
1.6287 + else
1.6288 + __ bc1t((int)0);
1.6289 break;
1.6290 case 0x06: //less_equal
1.6291 __ c_ule_d(reg_op1, reg_op2);
1.6292 if(&L)
1.6293 - __ bc1t(L);
1.6294 - else
1.6295 - __ bc1t((int)0);
1.6296 - break;
1.6297 + __ bc1t(L);
1.6298 + else
1.6299 + __ bc1t((int)0);
1.6300 + break;
1.6301 default:
1.6302 - Unimplemented();
1.6303 - }
1.6304 + Unimplemented();
1.6305 + }
1.6306 __ nop();
1.6307 %}
1.6308
1.6309 @@ -7791,7 +7747,7 @@
1.6310
1.6311 format %{ "MEMBAR @ load_fence" %}
1.6312 ins_encode %{
1.6313 - __ sync();
1.6314 + __ sync();
1.6315 %}
1.6316 ins_pipe(pipe_slow);
1.6317 %}
1.6318 @@ -7828,7 +7784,7 @@
1.6319 format %{ "MEMBAR @ store_fence" %}
1.6320
1.6321 ins_encode %{
1.6322 - __ sync();
1.6323 + __ sync();
1.6324 %}
1.6325
1.6326 ins_pipe(pipe_slow);
1.6327 @@ -7869,7 +7825,7 @@
1.6328 ins_encode( );
1.6329 ins_pipe(empty);
1.6330 %}
1.6331 -
1.6332 +
1.6333 instruct membar_storestore() %{
1.6334 match(MemBarStoreStore);
1.6335
1.6336 @@ -7888,8 +7844,8 @@
1.6337 Register src = $src$$Register;
1.6338 Register dst = $dst$$Register;
1.6339
1.6340 - if(src != dst)
1.6341 - __ move(dst, src);
1.6342 + if(src != dst)
1.6343 + __ move(dst, src);
1.6344 %}
1.6345 ins_cost(10);
1.6346 ins_pipe( ialu_regI_mov );
1.6347 @@ -7903,8 +7859,8 @@
1.6348 Register src = $src$$Register;
1.6349 Register dst = $dst$$Register;
1.6350
1.6351 - if(src != dst)
1.6352 - __ move(dst, src);
1.6353 + if(src != dst)
1.6354 + __ move(dst, src);
1.6355 %}
1.6356 ins_pipe( ialu_regI_mov );
1.6357 %}
1.6358 @@ -7982,8 +7938,7 @@
1.6359 Register src = $src$$Register;
1.6360 int flag = $cop$$cmpcode;
1.6361
1.6362 - switch(flag)
1.6363 - {
1.6364 + switch(flag) {
1.6365 case 0x01: //equal
1.6366 __ subu32(AT, op1, op2);
1.6367 __ movz(dst, src, AT);
1.6368 @@ -8015,8 +7970,8 @@
1.6369 break;
1.6370
1.6371 default:
1.6372 - Unimplemented();
1.6373 - }
1.6374 + Unimplemented();
1.6375 + }
1.6376 %}
1.6377
1.6378 ins_pipe( pipe_slow );
1.6379 @@ -8036,8 +7991,7 @@
1.6380 Register src = $src$$Register;
1.6381 int flag = $cop$$cmpcode;
1.6382
1.6383 - switch(flag)
1.6384 - {
1.6385 + switch(flag) {
1.6386 case 0x01: //equal
1.6387 __ subu(AT, op1, op2);
1.6388 __ movz(dst, src, AT);
1.6389 @@ -8069,8 +8023,8 @@
1.6390 break;
1.6391
1.6392 default:
1.6393 - Unimplemented();
1.6394 - }
1.6395 + Unimplemented();
1.6396 + }
1.6397 %}
1.6398
1.6399 ins_pipe( pipe_slow );
1.6400 @@ -8090,8 +8044,7 @@
1.6401 Register src = $src$$Register;
1.6402 int flag = $cop$$cmpcode;
1.6403
1.6404 - switch(flag)
1.6405 - {
1.6406 + switch(flag) {
1.6407 case 0x01: //equal
1.6408 __ subu32(AT, op1, op2);
1.6409 __ movz(dst, src, AT);
1.6410 @@ -8124,7 +8077,7 @@
1.6411
1.6412 default:
1.6413 Unimplemented();
1.6414 - }
1.6415 + }
1.6416 %}
1.6417
1.6418 ins_pipe( pipe_slow );
1.6419 @@ -8144,8 +8097,7 @@
1.6420 Register src = $src$$Register;
1.6421 int flag = $cop$$cmpcode;
1.6422
1.6423 - switch(flag)
1.6424 - {
1.6425 + switch(flag) {
1.6426 case 0x01: //equal
1.6427 __ subu32(AT, op1, op2);
1.6428 __ movz(dst, src, AT);
1.6429 @@ -8178,7 +8130,7 @@
1.6430
1.6431 default:
1.6432 Unimplemented();
1.6433 - }
1.6434 + }
1.6435 %}
1.6436
1.6437 ins_pipe( pipe_slow );
1.6438 @@ -8199,8 +8151,7 @@
1.6439 Register src = $src$$Register;
1.6440 int flag = $cop$$cmpcode;
1.6441
1.6442 - switch(flag)
1.6443 - {
1.6444 + switch(flag) {
1.6445 case 0x01: //equal
1.6446 __ c_eq_s(reg_op1, reg_op2);
1.6447 __ movt(dst, src);
1.6448 @@ -8224,10 +8175,10 @@
1.6449 case 0x06: //less_equal
1.6450 __ c_ule_s(reg_op1, reg_op2);
1.6451 __ movt(dst, src);
1.6452 - break;
1.6453 + break;
1.6454 default:
1.6455 - Unimplemented();
1.6456 - }
1.6457 + Unimplemented();
1.6458 + }
1.6459 %}
1.6460 ins_pipe( pipe_slow );
1.6461 %}
1.6462 @@ -8246,8 +8197,7 @@
1.6463 Register src = $src$$Register;
1.6464 int flag = $cop$$cmpcode;
1.6465
1.6466 - switch(flag)
1.6467 - {
1.6468 + switch(flag) {
1.6469 case 0x01: //equal
1.6470 __ subu32(AT, op1, op2);
1.6471 __ movz(dst, src, AT);
1.6472 @@ -8279,8 +8229,8 @@
1.6473 break;
1.6474
1.6475 default:
1.6476 - Unimplemented();
1.6477 - }
1.6478 + Unimplemented();
1.6479 + }
1.6480 %}
1.6481
1.6482 ins_pipe( pipe_slow );
1.6483 @@ -8300,8 +8250,7 @@
1.6484 Register src = $src$$Register;
1.6485 int flag = $cop$$cmpcode;
1.6486
1.6487 - switch(flag)
1.6488 - {
1.6489 + switch(flag) {
1.6490 case 0x01: //equal
1.6491 __ subu(AT, op1, op2);
1.6492 __ movz(dst, src, AT);
1.6493 @@ -8330,11 +8279,11 @@
1.6494 case 0x06: //below_equal
1.6495 __ sltu(AT, op2, op1);
1.6496 __ movz(dst, src, AT);
1.6497 - break;
1.6498 + break;
1.6499
1.6500 default:
1.6501 - Unimplemented();
1.6502 - }
1.6503 + Unimplemented();
1.6504 + }
1.6505 %}
1.6506
1.6507 ins_pipe( pipe_slow );
1.6508 @@ -8355,8 +8304,7 @@
1.6509
1.6510 int flag = $cop$$cmpcode;
1.6511
1.6512 - switch(flag)
1.6513 - {
1.6514 + switch(flag) {
1.6515 case 0x01: //equal
1.6516 __ c_eq_d(reg_op1, reg_op2);
1.6517 __ movt(dst, src);
1.6518 @@ -8382,8 +8330,8 @@
1.6519 __ movt(dst, src);
1.6520 break;
1.6521 default:
1.6522 - Unimplemented();
1.6523 - }
1.6524 + Unimplemented();
1.6525 + }
1.6526 %}
1.6527
1.6528 ins_pipe( pipe_slow );
1.6529 @@ -8404,8 +8352,7 @@
1.6530 Register src = $src$$Register;
1.6531 int flag = $cop$$cmpcode;
1.6532
1.6533 - switch(flag)
1.6534 - {
1.6535 + switch(flag) {
1.6536 case 0x01: //equal
1.6537 __ subu32(AT, op1, op2);
1.6538 __ movz(dst, src, AT);
1.6539 @@ -8434,11 +8381,11 @@
1.6540 case 0x06: //below_equal
1.6541 __ sltu(AT, op2, op1);
1.6542 __ movz(dst, src, AT);
1.6543 - break;
1.6544 + break;
1.6545
1.6546 default:
1.6547 - Unimplemented();
1.6548 - }
1.6549 + Unimplemented();
1.6550 + }
1.6551 %}
1.6552
1.6553 ins_pipe( pipe_slow );
1.6554 @@ -8459,8 +8406,7 @@
1.6555 Register src = $src$$Register;
1.6556 int flag = $cop$$cmpcode;
1.6557
1.6558 - switch(flag)
1.6559 - {
1.6560 + switch(flag) {
1.6561 case 0x01: //equal
1.6562 __ subu(AT, op1, op2);
1.6563 __ movz(dst, src, AT);
1.6564 @@ -8489,11 +8435,11 @@
1.6565 case 0x06: //below_equal
1.6566 __ sltu(AT, op2, op1);
1.6567 __ movz(dst, src, AT);
1.6568 - break;
1.6569 + break;
1.6570
1.6571 default:
1.6572 - Unimplemented();
1.6573 - }
1.6574 + Unimplemented();
1.6575 + }
1.6576 %}
1.6577
1.6578 ins_pipe( pipe_slow );
1.6579 @@ -8513,8 +8459,7 @@
1.6580 Register src = $src$$Register;
1.6581 int flag = $cop$$cmpcode;
1.6582
1.6583 - switch(flag)
1.6584 - {
1.6585 + switch(flag) {
1.6586 case 0x01: //equal
1.6587 __ subu(AT, opr1, opr2);
1.6588 __ movz(dst, src, AT);
1.6589 @@ -8526,7 +8471,7 @@
1.6590 break;
1.6591
1.6592 case 0x03: //greater
1.6593 - __ slt(AT, opr2, opr1);
1.6594 + __ slt(AT, opr2, opr1);
1.6595 __ movn(dst, src, AT);
1.6596 break;
1.6597
1.6598 @@ -8546,8 +8491,8 @@
1.6599 break;
1.6600
1.6601 default:
1.6602 - Unimplemented();
1.6603 - }
1.6604 + Unimplemented();
1.6605 + }
1.6606 %}
1.6607
1.6608 ins_pipe( pipe_slow );
1.6609 @@ -8567,8 +8512,7 @@
1.6610 Register src = $src$$Register;
1.6611 int flag = $cop$$cmpcode;
1.6612
1.6613 - switch(flag)
1.6614 - {
1.6615 + switch(flag) {
1.6616 case 0x01: //equal
1.6617 __ subu(AT, opr1, opr2);
1.6618 __ movz(dst, src, AT);
1.6619 @@ -8600,8 +8544,8 @@
1.6620 break;
1.6621
1.6622 default:
1.6623 - Unimplemented();
1.6624 - }
1.6625 + Unimplemented();
1.6626 + }
1.6627 %}
1.6628
1.6629 ins_pipe( pipe_slow );
1.6630 @@ -8622,8 +8566,7 @@
1.6631
1.6632 int flag = $cop$$cmpcode;
1.6633
1.6634 - switch(flag)
1.6635 - {
1.6636 + switch(flag) {
1.6637 case 0x01: //equal
1.6638 __ c_eq_d(reg_op1, reg_op2);
1.6639 __ movt(dst, src);
1.6640 @@ -8650,8 +8593,8 @@
1.6641 __ movt(dst, src);
1.6642 break;
1.6643 default:
1.6644 - Unimplemented();
1.6645 - }
1.6646 + Unimplemented();
1.6647 + }
1.6648 %}
1.6649
1.6650 ins_pipe( pipe_slow );
1.6651 @@ -8672,8 +8615,7 @@
1.6652 Register src = $src$$Register;
1.6653 int flag = $cop$$cmpcode;
1.6654
1.6655 - switch(flag)
1.6656 - {
1.6657 + switch(flag) {
1.6658 case 0x01: //equal
1.6659 __ subu(AT, op1, op2);
1.6660 __ movz(dst, src, AT);
1.6661 @@ -8705,8 +8647,8 @@
1.6662 break;
1.6663
1.6664 default:
1.6665 - Unimplemented();
1.6666 - }
1.6667 + Unimplemented();
1.6668 + }
1.6669 %}
1.6670
1.6671 ins_pipe( pipe_slow );
1.6672 @@ -8726,8 +8668,7 @@
1.6673 Register src = $src$$Register;
1.6674 int flag = $cop$$cmpcode;
1.6675
1.6676 - switch(flag)
1.6677 - {
1.6678 + switch(flag) {
1.6679 case 0x01: //equal
1.6680 __ subu32(AT, op1, op2);
1.6681 __ movz(dst, src, AT);
1.6682 @@ -8756,11 +8697,11 @@
1.6683 case 0x06: //below_equal
1.6684 __ slt(AT, op2, op1);
1.6685 __ movz(dst, src, AT);
1.6686 - break;
1.6687 + break;
1.6688
1.6689 default:
1.6690 - Unimplemented();
1.6691 - }
1.6692 + Unimplemented();
1.6693 + }
1.6694 %}
1.6695
1.6696 ins_pipe( pipe_slow );
1.6697 @@ -8780,8 +8721,7 @@
1.6698 Register src = $src$$Register;
1.6699 int flag = $cop$$cmpcode;
1.6700
1.6701 - switch(flag)
1.6702 - {
1.6703 + switch(flag) {
1.6704 case 0x01: //equal
1.6705 __ subu(AT, opr1, opr2);
1.6706 __ movz(dst, src, AT);
1.6707 @@ -8793,7 +8733,7 @@
1.6708 break;
1.6709
1.6710 case 0x03: //greater
1.6711 - __ slt(AT, opr2, opr1);
1.6712 + __ slt(AT, opr2, opr1);
1.6713 __ movn(dst, src, AT);
1.6714 break;
1.6715
1.6716 @@ -8813,8 +8753,8 @@
1.6717 break;
1.6718
1.6719 default:
1.6720 - Unimplemented();
1.6721 - }
1.6722 + Unimplemented();
1.6723 + }
1.6724 %}
1.6725
1.6726 ins_pipe( pipe_slow );
1.6727 @@ -8834,8 +8774,7 @@
1.6728 Register src = $src$$Register;
1.6729 int flag = $cop$$cmpcode;
1.6730
1.6731 - switch(flag)
1.6732 - {
1.6733 + switch(flag) {
1.6734 case 0x01: //equal
1.6735 __ subu32(AT, op1, op2);
1.6736 __ movz(dst, src, AT);
1.6737 @@ -8867,8 +8806,8 @@
1.6738 break;
1.6739
1.6740 default:
1.6741 - Unimplemented();
1.6742 - }
1.6743 + Unimplemented();
1.6744 + }
1.6745 %}
1.6746
1.6747 ins_pipe( pipe_slow );
1.6748 @@ -8888,8 +8827,7 @@
1.6749 Register src = $src$$Register;
1.6750 int flag = $cop$$cmpcode;
1.6751
1.6752 - switch(flag)
1.6753 - {
1.6754 + switch(flag) {
1.6755 case 0x01: //equal
1.6756 __ subu32(AT, op1, op2);
1.6757 __ movz(dst, src, AT);
1.6758 @@ -8921,8 +8859,8 @@
1.6759 break;
1.6760
1.6761 default:
1.6762 - Unimplemented();
1.6763 - }
1.6764 + Unimplemented();
1.6765 + }
1.6766 %}
1.6767
1.6768 ins_pipe( pipe_slow );
1.6769 @@ -8943,8 +8881,7 @@
1.6770 Register src = $src$$Register;
1.6771 int flag = $cop$$cmpcode;
1.6772
1.6773 - switch(flag)
1.6774 - {
1.6775 + switch(flag) {
1.6776 case 0x01: //equal
1.6777 __ c_eq_s(reg_op1, reg_op2);
1.6778 __ movt(dst, src);
1.6779 @@ -8970,8 +8907,8 @@
1.6780 __ movt(dst, src);
1.6781 break;
1.6782 default:
1.6783 - Unimplemented();
1.6784 - }
1.6785 + Unimplemented();
1.6786 + }
1.6787 %}
1.6788 ins_pipe( pipe_slow );
1.6789 %}
1.6790 @@ -9024,8 +8961,8 @@
1.6791 break;
1.6792
1.6793 default:
1.6794 - Unimplemented();
1.6795 - }
1.6796 + Unimplemented();
1.6797 + }
1.6798 %}
1.6799
1.6800 ins_pipe( pipe_slow );
1.6801 @@ -9045,8 +8982,7 @@
1.6802 Register src = as_Register($src$$reg);
1.6803 int flag = $cop$$cmpcode;
1.6804
1.6805 - switch(flag)
1.6806 - {
1.6807 + switch(flag) {
1.6808 case 0x01: //equal
1.6809 __ subu(AT, opr1, opr2);
1.6810 __ movz(dst, src, AT);
1.6811 @@ -9078,8 +9014,8 @@
1.6812 break;
1.6813
1.6814 default:
1.6815 - Unimplemented();
1.6816 - }
1.6817 + Unimplemented();
1.6818 + }
1.6819 %}
1.6820
1.6821 ins_pipe( pipe_slow );
1.6822 @@ -9099,8 +9035,7 @@
1.6823 Register src = $src$$Register;
1.6824 int flag = $cop$$cmpcode;
1.6825
1.6826 - switch(flag)
1.6827 - {
1.6828 + switch(flag) {
1.6829 case 0x01: //equal
1.6830 __ subu32(AT, op1, op2);
1.6831 __ movz(dst, src, AT);
1.6832 @@ -9132,8 +9067,8 @@
1.6833 break;
1.6834
1.6835 default:
1.6836 - Unimplemented();
1.6837 - }
1.6838 + Unimplemented();
1.6839 + }
1.6840 %}
1.6841
1.6842 ins_pipe( pipe_slow );
1.6843 @@ -9155,8 +9090,7 @@
1.6844
1.6845 int flag = $cop$$cmpcode;
1.6846
1.6847 - switch(flag)
1.6848 - {
1.6849 + switch(flag) {
1.6850 case 0x01: //equal
1.6851 __ c_eq_d(reg_op1, reg_op2);
1.6852 __ movt(dst, src);
1.6853 @@ -9182,8 +9116,8 @@
1.6854 __ movt(dst, src);
1.6855 break;
1.6856 default:
1.6857 - Unimplemented();
1.6858 - }
1.6859 + Unimplemented();
1.6860 + }
1.6861 %}
1.6862
1.6863 ins_pipe( pipe_slow );
1.6864 @@ -9204,8 +9138,7 @@
1.6865
1.6866 int flag = $cop$$cmpcode;
1.6867
1.6868 - switch(flag)
1.6869 - {
1.6870 + switch(flag) {
1.6871 case 0x01: //equal
1.6872 __ c_eq_d(reg_op1, reg_op2);
1.6873 __ movt_d(dst, src);
1.6874 @@ -9231,7 +9164,7 @@
1.6875 __ movt_d(dst, src);
1.6876 break;
1.6877 default:
1.6878 - Unimplemented();
1.6879 + Unimplemented();
1.6880 }
1.6881 %}
1.6882
1.6883 @@ -9252,53 +9185,52 @@
1.6884 FloatRegister dst = as_FloatRegister($dst$$reg);
1.6885 FloatRegister src = as_FloatRegister($src$$reg);
1.6886 int flag = $cop$$cmpcode;
1.6887 - Label L;
1.6888 -
1.6889 - switch(flag)
1.6890 - {
1.6891 + Label L;
1.6892 +
1.6893 + switch(flag) {
1.6894 case 0x01: //equal
1.6895 - __ bne(op1, op2, L);
1.6896 + __ bne(op1, op2, L);
1.6897 __ nop();
1.6898 __ mov_s(dst, src);
1.6899 __ bind(L);
1.6900 break;
1.6901 case 0x02: //not_equal
1.6902 - __ beq(op1, op2, L);
1.6903 + __ beq(op1, op2, L);
1.6904 __ nop();
1.6905 __ mov_s(dst, src);
1.6906 __ bind(L);
1.6907 break;
1.6908 case 0x03: //great
1.6909 __ slt(AT, op2, op1);
1.6910 - __ beq(AT, R0, L);
1.6911 + __ beq(AT, R0, L);
1.6912 __ nop();
1.6913 __ mov_s(dst, src);
1.6914 __ bind(L);
1.6915 break;
1.6916 case 0x04: //great_equal
1.6917 __ slt(AT, op1, op2);
1.6918 - __ bne(AT, R0, L);
1.6919 + __ bne(AT, R0, L);
1.6920 __ nop();
1.6921 __ mov_s(dst, src);
1.6922 __ bind(L);
1.6923 break;
1.6924 case 0x05: //less
1.6925 __ slt(AT, op1, op2);
1.6926 - __ beq(AT, R0, L);
1.6927 + __ beq(AT, R0, L);
1.6928 __ nop();
1.6929 __ mov_s(dst, src);
1.6930 __ bind(L);
1.6931 break;
1.6932 case 0x06: //less_equal
1.6933 __ slt(AT, op2, op1);
1.6934 - __ bne(AT, R0, L);
1.6935 + __ bne(AT, R0, L);
1.6936 __ nop();
1.6937 __ mov_s(dst, src);
1.6938 __ bind(L);
1.6939 break;
1.6940 default:
1.6941 - Unimplemented();
1.6942 - }
1.6943 + Unimplemented();
1.6944 + }
1.6945 %}
1.6946
1.6947 ins_pipe( pipe_slow );
1.6948 @@ -9318,53 +9250,52 @@
1.6949 FloatRegister dst = as_FloatRegister($dst$$reg);
1.6950 FloatRegister src = as_FloatRegister($src$$reg);
1.6951 int flag = $cop$$cmpcode;
1.6952 - Label L;
1.6953 -
1.6954 - switch(flag)
1.6955 - {
1.6956 + Label L;
1.6957 +
1.6958 + switch(flag) {
1.6959 case 0x01: //equal
1.6960 - __ bne(op1, op2, L);
1.6961 + __ bne(op1, op2, L);
1.6962 __ nop();
1.6963 __ mov_d(dst, src);
1.6964 __ bind(L);
1.6965 break;
1.6966 case 0x02: //not_equal
1.6967 - __ beq(op1, op2, L);
1.6968 + __ beq(op1, op2, L);
1.6969 __ nop();
1.6970 __ mov_d(dst, src);
1.6971 __ bind(L);
1.6972 break;
1.6973 case 0x03: //great
1.6974 __ slt(AT, op2, op1);
1.6975 - __ beq(AT, R0, L);
1.6976 + __ beq(AT, R0, L);
1.6977 __ nop();
1.6978 __ mov_d(dst, src);
1.6979 __ bind(L);
1.6980 break;
1.6981 case 0x04: //great_equal
1.6982 __ slt(AT, op1, op2);
1.6983 - __ bne(AT, R0, L);
1.6984 + __ bne(AT, R0, L);
1.6985 __ nop();
1.6986 __ mov_d(dst, src);
1.6987 __ bind(L);
1.6988 break;
1.6989 case 0x05: //less
1.6990 __ slt(AT, op1, op2);
1.6991 - __ beq(AT, R0, L);
1.6992 + __ beq(AT, R0, L);
1.6993 __ nop();
1.6994 __ mov_d(dst, src);
1.6995 __ bind(L);
1.6996 break;
1.6997 case 0x06: //less_equal
1.6998 __ slt(AT, op2, op1);
1.6999 - __ bne(AT, R0, L);
1.7000 + __ bne(AT, R0, L);
1.7001 __ nop();
1.7002 __ mov_d(dst, src);
1.7003 __ bind(L);
1.7004 - break;
1.7005 + break;
1.7006 default:
1.7007 - Unimplemented();
1.7008 - }
1.7009 + Unimplemented();
1.7010 + }
1.7011 %}
1.7012
1.7013 ins_pipe( pipe_slow );
1.7014 @@ -9384,53 +9315,52 @@
1.7015 FloatRegister dst = as_FloatRegister($dst$$reg);
1.7016 FloatRegister src = as_FloatRegister($src$$reg);
1.7017 int flag = $cop$$cmpcode;
1.7018 - Label L;
1.7019 -
1.7020 - switch(flag)
1.7021 - {
1.7022 + Label L;
1.7023 +
1.7024 + switch(flag) {
1.7025 case 0x01: //equal
1.7026 - __ bne(op1, op2, L);
1.7027 + __ bne(op1, op2, L);
1.7028 __ nop();
1.7029 __ mov_d(dst, src);
1.7030 __ bind(L);
1.7031 break;
1.7032 case 0x02: //not_equal
1.7033 - __ beq(op1, op2, L);
1.7034 + __ beq(op1, op2, L);
1.7035 __ nop();
1.7036 __ mov_d(dst, src);
1.7037 __ bind(L);
1.7038 break;
1.7039 case 0x03: //great
1.7040 __ slt(AT, op2, op1);
1.7041 - __ beq(AT, R0, L);
1.7042 + __ beq(AT, R0, L);
1.7043 __ nop();
1.7044 __ mov_d(dst, src);
1.7045 __ bind(L);
1.7046 break;
1.7047 case 0x04: //great_equal
1.7048 __ slt(AT, op1, op2);
1.7049 - __ bne(AT, R0, L);
1.7050 + __ bne(AT, R0, L);
1.7051 __ nop();
1.7052 __ mov_d(dst, src);
1.7053 __ bind(L);
1.7054 break;
1.7055 case 0x05: //less
1.7056 __ slt(AT, op1, op2);
1.7057 - __ beq(AT, R0, L);
1.7058 + __ beq(AT, R0, L);
1.7059 __ nop();
1.7060 __ mov_d(dst, src);
1.7061 __ bind(L);
1.7062 break;
1.7063 case 0x06: //less_equal
1.7064 __ slt(AT, op2, op1);
1.7065 - __ bne(AT, R0, L);
1.7066 + __ bne(AT, R0, L);
1.7067 __ nop();
1.7068 __ mov_d(dst, src);
1.7069 __ bind(L);
1.7070 - break;
1.7071 + break;
1.7072 default:
1.7073 - Unimplemented();
1.7074 - }
1.7075 + Unimplemented();
1.7076 + }
1.7077 %}
1.7078
1.7079 ins_pipe( pipe_slow );
1.7080 @@ -9452,8 +9382,7 @@
1.7081 Register src = $src$$Register;
1.7082 int flag = $cop$$cmpcode;
1.7083
1.7084 - switch(flag)
1.7085 - {
1.7086 + switch(flag) {
1.7087 case 0x01: //equal
1.7088 __ c_eq_s(reg_op1, reg_op2);
1.7089 __ movt(dst, src);
1.7090 @@ -9477,10 +9406,10 @@
1.7091 case 0x06: //less_equal
1.7092 __ c_ule_s(reg_op1, reg_op2);
1.7093 __ movt(dst, src);
1.7094 - break;
1.7095 + break;
1.7096 default:
1.7097 - Unimplemented();
1.7098 - }
1.7099 + Unimplemented();
1.7100 + }
1.7101 %}
1.7102 ins_pipe( pipe_slow );
1.7103 %}
1.7104 @@ -9500,8 +9429,7 @@
1.7105 FloatRegister src = $src$$FloatRegister;
1.7106 int flag = $cop$$cmpcode;
1.7107
1.7108 - switch(flag)
1.7109 - {
1.7110 + switch(flag) {
1.7111 case 0x01: //equal
1.7112 __ c_eq_s(reg_op1, reg_op2);
1.7113 __ movt_s(dst, src);
1.7114 @@ -9527,7 +9455,7 @@
1.7115 __ movt_s(dst, src);
1.7116 break;
1.7117 default:
1.7118 - Unimplemented();
1.7119 + Unimplemented();
1.7120 }
1.7121 %}
1.7122 ins_pipe( pipe_slow );
1.7123 @@ -9559,9 +9487,9 @@
1.7124 %}
1.7125
1.7126 //
1.7127 -// less_rsult = -1
1.7128 +// less_rsult = -1
1.7129 // greater_result = 1
1.7130 -// equal_result = 0
1.7131 +// equal_result = 0
1.7132 // nan_result = -1
1.7133 //
1.7134 instruct cmpF3_reg_reg(mRegI dst, regF src1, regF src2) %{
1.7135 @@ -9625,7 +9553,7 @@
1.7136 __ beq(num, R0, done);
1.7137 __ delayed()->daddu(AT, base, R0);
1.7138
1.7139 - __ move(T9, num); /* T9 = words */
1.7140 + __ move(T9, num); /* T9 = words */
1.7141
1.7142 __ bind(Loop);
1.7143 __ sd(R0, AT, 0);
1.7144 @@ -9645,7 +9573,7 @@
1.7145 format %{ "String Compare $str1[len: $cnt1], $str2[len: $cnt2] -> $result @ string_compare" %}
1.7146 ins_encode %{
1.7147 // Get the first character position in both strings
1.7148 - // [8] char array, [12] offset, [16] count
1.7149 + // [8] char array, [12] offset, [16] count
1.7150 Register str1 = $str1$$Register;
1.7151 Register str2 = $str2$$Register;
1.7152 Register cnt1 = $cnt1$$Register;
1.7153 @@ -9661,7 +9589,7 @@
1.7154 __ slt(AT, cnt2, cnt1);
1.7155 __ movn(cnt1, cnt2, AT);
1.7156
1.7157 - // Now the shorter length is in cnt1 and cnt2 can be used as a tmp register
1.7158 + // Now the shorter length is in cnt1 and cnt2 can be used as a tmp register
1.7159 __ bind(Loop); // Loop begin
1.7160 __ beq(cnt1, R0, done);
1.7161 __ delayed()->lhu(AT, str1, 0);;
1.7162 @@ -9691,7 +9619,7 @@
1.7163 format %{ "String Equal $str1, $str2, len:$cnt tmp:$temp -> $result @ string_equals" %}
1.7164 ins_encode %{
1.7165 // Get the first character position in both strings
1.7166 - // [8] char array, [12] offset, [16] count
1.7167 + // [8] char array, [12] offset, [16] count
1.7168 Register str1 = $str1$$Register;
1.7169 Register str2 = $str2$$Register;
1.7170 Register cnt = $cnt$$Register;
1.7171 @@ -9767,7 +9695,7 @@
1.7172 Register dst = $dst$$Register;
1.7173 Register src1 = $src1$$Register;
1.7174 Register src2 = $src2$$Register;
1.7175 - __ daddu(dst, src1, src2);
1.7176 + __ daddu(dst, src1, src2);
1.7177 %}
1.7178
1.7179 ins_pipe( ialu_regI_regI );
1.7180 @@ -9782,7 +9710,7 @@
1.7181 Register dst = $dst$$Register;
1.7182 Register src1 = $src1$$Register;
1.7183 Register src2 = $src2$$Register;
1.7184 - __ daddu(dst, src1, src2);
1.7185 + __ daddu(dst, src1, src2);
1.7186 %}
1.7187
1.7188 ins_pipe( ialu_regI_regI );
1.7189 @@ -10041,13 +9969,13 @@
1.7190
1.7191 //if (UseLoongsonISA) {
1.7192 if (0) {
1.7193 - // 2016.08.10
1.7194 + // 2016.08.10
1.7195 // Experiments show that gsmod is slower that div+mfhi.
1.7196 // So I just disable it here.
1.7197 __ gsmod(dst, src1, src2);
1.7198 } else {
1.7199 - __ div(src1, src2);
1.7200 - __ mfhi(dst);
1.7201 + __ div(src1, src2);
1.7202 + __ mfhi(dst);
1.7203 }
1.7204 %}
1.7205
1.7206 @@ -10083,7 +10011,7 @@
1.7207 Register src1 = $src1$$Register;
1.7208 Register src2 = $src2$$Register;
1.7209 Register dst = $dst$$Register;
1.7210 -
1.7211 +
1.7212 __ mul(dst, src1, src2);
1.7213 %}
1.7214 ins_pipe( ialu_mult );
1.7215 @@ -10099,7 +10027,7 @@
1.7216 Register src2 = $src2$$Register;
1.7217 Register src3 = $src3$$Register;
1.7218 Register dst = $dst$$Register;
1.7219 -
1.7220 +
1.7221 __ mtlo(src3);
1.7222 __ madd(src1, src2);
1.7223 __ mflo(dst);
1.7224 @@ -10118,7 +10046,7 @@
1.7225 Register dst = $dst$$Register;
1.7226
1.7227 /* 2012/4/21 Jin: In MIPS, div does not cause exception.
1.7228 - We must trap an exception manually. */
1.7229 + We must trap an exception manually. */
1.7230 __ teq(R0, src2, 0x7);
1.7231
1.7232 if (UseLoongsonISA) {
1.7233 @@ -10144,7 +10072,7 @@
1.7234 FloatRegister src2 = $src2$$FloatRegister;
1.7235 FloatRegister dst = $dst$$FloatRegister;
1.7236
1.7237 - /* Here do we need to trap an exception manually ? */
1.7238 + /* Here do we need to trap an exception manually ? */
1.7239 __ div_s(dst, src1, src2);
1.7240 %}
1.7241 ins_pipe( pipe_slow );
1.7242 @@ -10160,7 +10088,7 @@
1.7243 FloatRegister src2 = $src2$$FloatRegister;
1.7244 FloatRegister dst = $dst$$FloatRegister;
1.7245
1.7246 - /* Here do we need to trap an exception manually ? */
1.7247 + /* Here do we need to trap an exception manually ? */
1.7248 __ div_d(dst, src1, src2);
1.7249 %}
1.7250 ins_pipe( pipe_slow );
1.7251 @@ -10229,7 +10157,7 @@
1.7252 FloatRegister src2 = as_FloatRegister($src2$$reg);
1.7253 FloatRegister dst = as_FloatRegister($dst$$reg);
1.7254
1.7255 - __ add_s(dst, src1, src2);
1.7256 + __ add_s(dst, src1, src2);
1.7257 %}
1.7258 ins_pipe( fpu_regF_regF );
1.7259 %}
1.7260 @@ -10242,7 +10170,7 @@
1.7261 FloatRegister src2 = as_FloatRegister($src2$$reg);
1.7262 FloatRegister dst = as_FloatRegister($dst$$reg);
1.7263
1.7264 - __ sub_s(dst, src1, src2);
1.7265 + __ sub_s(dst, src1, src2);
1.7266 %}
1.7267 ins_pipe( fpu_regF_regF );
1.7268 %}
1.7269 @@ -10254,7 +10182,7 @@
1.7270 FloatRegister src2 = as_FloatRegister($src2$$reg);
1.7271 FloatRegister dst = as_FloatRegister($dst$$reg);
1.7272
1.7273 - __ add_d(dst, src1, src2);
1.7274 + __ add_d(dst, src1, src2);
1.7275 %}
1.7276 ins_pipe( fpu_regF_regF );
1.7277 %}
1.7278 @@ -10267,7 +10195,7 @@
1.7279 FloatRegister src2 = as_FloatRegister($src2$$reg);
1.7280 FloatRegister dst = as_FloatRegister($dst$$reg);
1.7281
1.7282 - __ sub_d(dst, src1, src2);
1.7283 + __ sub_d(dst, src1, src2);
1.7284 %}
1.7285 ins_pipe( fpu_regF_regF );
1.7286 %}
1.7287 @@ -10291,7 +10219,7 @@
1.7288 FloatRegister src = as_FloatRegister($src$$reg);
1.7289 FloatRegister dst = as_FloatRegister($dst$$reg);
1.7290
1.7291 - __ neg_d(dst, src);
1.7292 + __ neg_d(dst, src);
1.7293 %}
1.7294 ins_pipe( fpu_regF_regF );
1.7295 %}
1.7296 @@ -10305,7 +10233,7 @@
1.7297 FloatRegister src2 = $src2$$FloatRegister;
1.7298 FloatRegister dst = $dst$$FloatRegister;
1.7299
1.7300 - __ mul_s(dst, src1, src2);
1.7301 + __ mul_s(dst, src1, src2);
1.7302 %}
1.7303 ins_pipe( fpu_regF_regF );
1.7304 %}
1.7305 @@ -10321,7 +10249,7 @@
1.7306 FloatRegister src3 = $src3$$FloatRegister;
1.7307 FloatRegister dst = $dst$$FloatRegister;
1.7308
1.7309 - __ madd_s(dst, src1, src2, src3);
1.7310 + __ madd_s(dst, src1, src2, src3);
1.7311 %}
1.7312 ins_pipe( fpu_regF_regF );
1.7313 %}
1.7314 @@ -10335,7 +10263,7 @@
1.7315 FloatRegister src2 = $src2$$FloatRegister;
1.7316 FloatRegister dst = $dst$$FloatRegister;
1.7317
1.7318 - __ mul_d(dst, src1, src2);
1.7319 + __ mul_d(dst, src1, src2);
1.7320 %}
1.7321 ins_pipe( fpu_regF_regF );
1.7322 %}
1.7323 @@ -10351,7 +10279,7 @@
1.7324 FloatRegister src3 = $src3$$FloatRegister;
1.7325 FloatRegister dst = $dst$$FloatRegister;
1.7326
1.7327 - __ madd_d(dst, src1, src2, src3);
1.7328 + __ madd_d(dst, src1, src2, src3);
1.7329 %}
1.7330 ins_pipe( fpu_regF_regF );
1.7331 %}
1.7332 @@ -10364,7 +10292,7 @@
1.7333 FloatRegister src = as_FloatRegister($src$$reg);
1.7334 FloatRegister dst = as_FloatRegister($dst$$reg);
1.7335
1.7336 - __ abs_s(dst, src);
1.7337 + __ abs_s(dst, src);
1.7338 %}
1.7339 ins_pipe( fpu_regF_regF );
1.7340 %}
1.7341 @@ -10381,7 +10309,7 @@
1.7342 FloatRegister src = as_FloatRegister($src$$reg);
1.7343 FloatRegister dst = as_FloatRegister($dst$$reg);
1.7344
1.7345 - __ abs_d(dst, src);
1.7346 + __ abs_d(dst, src);
1.7347 %}
1.7348 ins_pipe( fpu_regF_regF );
1.7349 %}
1.7350 @@ -10394,7 +10322,7 @@
1.7351 FloatRegister src = as_FloatRegister($src$$reg);
1.7352 FloatRegister dst = as_FloatRegister($dst$$reg);
1.7353
1.7354 - __ sqrt_d(dst, src);
1.7355 + __ sqrt_d(dst, src);
1.7356 %}
1.7357 ins_pipe( fpu_regF_regF );
1.7358 %}
1.7359 @@ -10424,9 +10352,9 @@
1.7360 Register dst = $dst$$Register;
1.7361 Register src = $src1$$Register;
1.7362 int val = $src2$$constant;
1.7363 -
1.7364 - __ move(AT, val);
1.7365 - __ andr(dst, src, AT);
1.7366 +
1.7367 + __ move(AT, val);
1.7368 + __ andr(dst, src, AT);
1.7369 %}
1.7370 ins_pipe( ialu_regI_regI );
1.7371 %}
1.7372 @@ -10440,8 +10368,8 @@
1.7373 Register dst = $dst$$Register;
1.7374 Register src = $src1$$Register;
1.7375 int val = $src2$$constant;
1.7376 -
1.7377 - __ andi(dst, src, val);
1.7378 +
1.7379 + __ andi(dst, src, val);
1.7380 %}
1.7381 ins_pipe( ialu_regI_regI );
1.7382 %}
1.7383 @@ -10485,7 +10413,7 @@
1.7384 Register dst = $dst$$Register;
1.7385 Register src = $src1$$Register;
1.7386 int val = $src2$$constant;
1.7387 -
1.7388 +
1.7389 __ xori(dst, src, val);
1.7390 %}
1.7391 ins_pipe( ialu_regI_regI );
1.7392 @@ -10500,8 +10428,8 @@
1.7393 ins_encode %{
1.7394 Register dst = $dst$$Register;
1.7395 Register src = $src1$$Register;
1.7396 -
1.7397 - __ gsorn(dst, R0, src);
1.7398 +
1.7399 + __ gsorn(dst, R0, src);
1.7400 %}
1.7401 ins_pipe( ialu_regI_regI );
1.7402 %}
1.7403 @@ -10515,8 +10443,8 @@
1.7404 ins_encode %{
1.7405 Register dst = $dst$$Register;
1.7406 Register src = $src1$$Register;
1.7407 -
1.7408 - __ gsorn(dst, R0, src);
1.7409 +
1.7410 + __ gsorn(dst, R0, src);
1.7411 %}
1.7412 ins_pipe( ialu_regI_regI );
1.7413 %}
1.7414 @@ -10530,7 +10458,7 @@
1.7415 Register dst = $dst$$Register;
1.7416 Register src = $src1$$Register;
1.7417 int val = $src2$$constant;
1.7418 -
1.7419 +
1.7420 __ xori(dst, src, val);
1.7421 %}
1.7422 ins_pipe( ialu_regI_regI );
1.7423 @@ -10546,8 +10474,8 @@
1.7424 ins_encode %{
1.7425 Register dst = $dst$$Register;
1.7426 Register src = $src1$$Register;
1.7427 -
1.7428 - __ gsorn(dst, R0, src);
1.7429 +
1.7430 + __ gsorn(dst, R0, src);
1.7431 %}
1.7432 ins_pipe( ialu_regI_regI );
1.7433 %}
1.7434 @@ -10680,7 +10608,7 @@
1.7435 Register dst = $dst$$Register;
1.7436 Register src = $src1$$Register;
1.7437 long val = $src2$$constant;
1.7438 -
1.7439 +
1.7440 __ andi(dst, src, val);
1.7441 %}
1.7442 ins_pipe( ialu_regI_regI );
1.7443 @@ -10695,7 +10623,7 @@
1.7444 Register dst = $dst$$Register;
1.7445 Register src = $src1$$Register;
1.7446 long val = $src2$$constant;
1.7447 -
1.7448 +
1.7449 __ andi(dst, src, val);
1.7450 %}
1.7451 ins_pipe( ialu_regI_regI );
1.7452 @@ -10776,7 +10704,7 @@
1.7453 format %{ "and $dst, $dst, $M8 #@andL_Reg_immL_M8" %}
1.7454 ins_encode %{
1.7455 Register dst = $dst$$Register;
1.7456 -
1.7457 +
1.7458 __ dins(dst, R0, 0, 3);
1.7459 %}
1.7460 ins_pipe( ialu_regI_regI );
1.7461 @@ -10789,7 +10717,7 @@
1.7462 format %{ "and $dst, $dst, $M5 #@andL_Reg_immL_M5" %}
1.7463 ins_encode %{
1.7464 Register dst = $dst$$Register;
1.7465 -
1.7466 +
1.7467 __ dins(dst, R0, 2, 1);
1.7468 %}
1.7469 ins_pipe( ialu_regI_regI );
1.7470 @@ -10802,7 +10730,7 @@
1.7471 format %{ "and $dst, $dst, $M7 #@andL_Reg_immL_M7" %}
1.7472 ins_encode %{
1.7473 Register dst = $dst$$Register;
1.7474 -
1.7475 +
1.7476 __ dins(dst, R0, 1, 2);
1.7477 %}
1.7478 ins_pipe( ialu_regI_regI );
1.7479 @@ -10815,7 +10743,7 @@
1.7480 format %{ "and $dst, $dst, $M4 #@andL_Reg_immL_M4" %}
1.7481 ins_encode %{
1.7482 Register dst = $dst$$Register;
1.7483 -
1.7484 +
1.7485 __ dins(dst, R0, 0, 2);
1.7486 %}
1.7487 ins_pipe( ialu_regI_regI );
1.7488 @@ -10828,7 +10756,7 @@
1.7489 format %{ "and $dst, $dst, $M121 #@andL_Reg_immL_M121" %}
1.7490 ins_encode %{
1.7491 Register dst = $dst$$Register;
1.7492 -
1.7493 +
1.7494 __ dins(dst, R0, 3, 4);
1.7495 %}
1.7496 ins_pipe( ialu_regI_regI );
1.7497 @@ -11008,7 +10936,7 @@
1.7498 %}
1.7499
1.7500
1.7501 -// Shift Left Long
1.7502 +// Shift Left Long
1.7503 instruct salL_Reg_imm(mRegL dst, mRegL src, immI8 shift) %{
1.7504 //predicate(UseNewLongLShift);
1.7505 match(Set dst (LShiftL src shift));
1.7506 @@ -11021,14 +10949,13 @@
1.7507
1.7508 if (__ is_simm(shamt, 5))
1.7509 __ dsll(dst_reg, src_reg, shamt);
1.7510 - else
1.7511 - {
1.7512 - int sa = Assembler::low(shamt, 6);
1.7513 - if (sa < 32) {
1.7514 - __ dsll(dst_reg, src_reg, sa);
1.7515 - } else {
1.7516 - __ dsll32(dst_reg, src_reg, sa - 32);
1.7517 - }
1.7518 + else {
1.7519 + int sa = Assembler::low(shamt, 6);
1.7520 + if (sa < 32) {
1.7521 + __ dsll(dst_reg, src_reg, sa);
1.7522 + } else {
1.7523 + __ dsll32(dst_reg, src_reg, sa - 32);
1.7524 + }
1.7525 }
1.7526 %}
1.7527 ins_pipe( ialu_regL_regL );
1.7528 @@ -11046,20 +10973,19 @@
1.7529
1.7530 if (__ is_simm(shamt, 5))
1.7531 __ dsll(dst_reg, src_reg, shamt);
1.7532 - else
1.7533 - {
1.7534 - int sa = Assembler::low(shamt, 6);
1.7535 - if (sa < 32) {
1.7536 - __ dsll(dst_reg, src_reg, sa);
1.7537 - } else {
1.7538 - __ dsll32(dst_reg, src_reg, sa - 32);
1.7539 - }
1.7540 + else {
1.7541 + int sa = Assembler::low(shamt, 6);
1.7542 + if (sa < 32) {
1.7543 + __ dsll(dst_reg, src_reg, sa);
1.7544 + } else {
1.7545 + __ dsll32(dst_reg, src_reg, sa - 32);
1.7546 + }
1.7547 }
1.7548 %}
1.7549 ins_pipe( ialu_regL_regL );
1.7550 %}
1.7551
1.7552 -// Shift Left Long
1.7553 +// Shift Left Long
1.7554 instruct salL_Reg_Reg(mRegL dst, mRegL src, mRegI shift) %{
1.7555 //predicate(UseNewLongLShift);
1.7556 match(Set dst (LShiftL src shift));
1.7557 @@ -11068,7 +10994,7 @@
1.7558 ins_encode %{
1.7559 Register src_reg = as_Register($src$$reg);
1.7560 Register dst_reg = as_Register($dst$$reg);
1.7561 -
1.7562 +
1.7563 __ dsllv(dst_reg, src_reg, $shift$$Register);
1.7564 %}
1.7565 ins_pipe( ialu_regL_regL );
1.7566 @@ -11084,20 +11010,20 @@
1.7567 int shamt = $shift$$constant;
1.7568
1.7569 if (__ is_simm(shamt, 5)) {
1.7570 - __ dsll(dst_reg, src_reg, shamt);
1.7571 + __ dsll(dst_reg, src_reg, shamt);
1.7572 } else {
1.7573 - int sa = Assembler::low(shamt, 6);
1.7574 - if (sa < 32) {
1.7575 - __ dsll(dst_reg, src_reg, sa);
1.7576 - } else {
1.7577 - __ dsll32(dst_reg, src_reg, sa - 32);
1.7578 - }
1.7579 - }
1.7580 - %}
1.7581 + int sa = Assembler::low(shamt, 6);
1.7582 + if (sa < 32) {
1.7583 + __ dsll(dst_reg, src_reg, sa);
1.7584 + } else {
1.7585 + __ dsll32(dst_reg, src_reg, sa - 32);
1.7586 + }
1.7587 + }
1.7588 + %}
1.7589 ins_pipe( ialu_regL_regL );
1.7590 %}
1.7591
1.7592 -// Shift Right Long
1.7593 +// Shift Right Long
1.7594 instruct sarL_Reg_imm(mRegL dst, mRegL src, immI8 shift) %{
1.7595 match(Set dst (RShiftL src shift));
1.7596 ins_cost(100);
1.7597 @@ -11107,14 +11033,14 @@
1.7598 Register dst_reg = as_Register($dst$$reg);
1.7599 int shamt = ($shift$$constant & 0x3f);
1.7600 if (__ is_simm(shamt, 5))
1.7601 - __ dsra(dst_reg, src_reg, shamt);
1.7602 + __ dsra(dst_reg, src_reg, shamt);
1.7603 else {
1.7604 - int sa = Assembler::low(shamt, 6);
1.7605 - if (sa < 32) {
1.7606 - __ dsra(dst_reg, src_reg, sa);
1.7607 - } else {
1.7608 - __ dsra32(dst_reg, src_reg, sa - 32);
1.7609 - }
1.7610 + int sa = Assembler::low(shamt, 6);
1.7611 + if (sa < 32) {
1.7612 + __ dsra(dst_reg, src_reg, sa);
1.7613 + } else {
1.7614 + __ dsra32(dst_reg, src_reg, sa - 32);
1.7615 + }
1.7616 }
1.7617 %}
1.7618 ins_pipe( ialu_regL_regL );
1.7619 @@ -11286,7 +11212,7 @@
1.7620 match(Set dst (OrI (URShiftI src rshift) (LShiftI (AndI src one) lshift)));
1.7621 predicate(32 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int())));
1.7622
1.7623 - format %{ "rotr $dst, $src, 1 ...\n\t"
1.7624 + format %{ "rotr $dst, $src, 1 ...\n\t"
1.7625 "srl $dst, $dst, ($rshift-1) @ rotI_shr_logical_Reg" %}
1.7626 ins_encode %{
1.7627 Register dst = $dst$$Register;
1.7628 @@ -11295,7 +11221,7 @@
1.7629
1.7630 __ rotr(dst, src, 1);
1.7631 if (rshift - 1) {
1.7632 - __ srl(dst, dst, rshift - 1);
1.7633 + __ srl(dst, dst, rshift - 1);
1.7634 }
1.7635 %}
1.7636
1.7637 @@ -11319,7 +11245,7 @@
1.7638 // Logical Shift Right by 8-bit immediate
1.7639 instruct shr_logical_Reg_imm(mRegI dst, mRegI src, immI8 shift) %{
1.7640 match(Set dst (URShiftI src shift));
1.7641 - // effect(KILL cr);
1.7642 + //effect(KILL cr);
1.7643
1.7644 format %{ "SRL $dst, $src, $shift #@shr_logical_Reg_imm" %}
1.7645 ins_encode %{
1.7646 @@ -11443,7 +11369,7 @@
1.7647 ins_pipe( ialu_regI_regI );
1.7648 %}
1.7649
1.7650 -// Logical Shift Right
1.7651 +// Logical Shift Right
1.7652 instruct shr_logical_Reg_Reg(mRegI dst, mRegI src, mRegI shift) %{
1.7653 match(Set dst (URShiftI src shift));
1.7654
1.7655 @@ -11579,7 +11505,7 @@
1.7656 Label Done;
1.7657
1.7658 __ trunc_l_d(F30, src);
1.7659 - // max_long: 0x7fffffffffffffff
1.7660 + // max_long: 0x7fffffffffffffff
1.7661 // __ set64(AT, 0x7fffffffffffffff);
1.7662 __ daddiu(AT, R0, -1);
1.7663 __ dsrl(AT, AT, 1);
1.7664 @@ -11613,7 +11539,7 @@
1.7665 FloatRegister src = as_FloatRegister($src$$reg);
1.7666
1.7667 Label L;
1.7668 -
1.7669 +
1.7670 __ c_un_d(src, src); //NaN?
1.7671 __ bc1t(L);
1.7672 __ delayed();
1.7673 @@ -11650,7 +11576,7 @@
1.7674 __ mfc1(dreg, F30);
1.7675 __ c_un_s(fval, fval); //NaN?
1.7676 __ movt(dreg, R0);
1.7677 -
1.7678 +
1.7679 __ bne(AT, dreg, L);
1.7680 __ delayed()->lui(T9, 0x8000);
1.7681
1.7682 @@ -11658,7 +11584,7 @@
1.7683 __ andr(AT, AT, T9);
1.7684
1.7685 __ movn(dreg, T9, AT);
1.7686 -
1.7687 +
1.7688 __ bind(L);
1.7689
1.7690 %}
1.7691 @@ -11696,12 +11622,12 @@
1.7692 /* 2014/01/08 Fu : This bug was found when running ezDS's control-panel.
1.7693 * J 982 C2 javax.swing.text.BoxView.layoutMajorAxis(II[I[I)V (283 bytes) @ 0x000000555c46aa74
1.7694 *
1.7695 - * An interger array index has been assigned to V0, and then changed from 1 to Integer.MAX_VALUE.
1.7696 + * An interger array index has been assigned to V0, and then changed from 1 to Integer.MAX_VALUE.
1.7697 * V0 is corrupted during call_VM_leaf(), and should be preserved.
1.7698 */
1.7699 __ push(fval);
1.7700 if(dreg != V0) {
1.7701 - __ push(V0);
1.7702 + __ push(V0);
1.7703 }
1.7704 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::f2i), 1);
1.7705 if(dreg != V0) {
1.7706 @@ -11731,7 +11657,7 @@
1.7707 __ dmfc1(dreg, F30);
1.7708 __ c_un_s(fval, fval); //NaN?
1.7709 __ movt(dreg, R0);
1.7710 -
1.7711 +
1.7712 __ bne(AT, dreg, L);
1.7713 __ delayed()->lui(T9, 0x8000);
1.7714
1.7715 @@ -11827,15 +11753,15 @@
1.7716 ins_cost(400);
1.7717
1.7718 format %{ "cmpLTMask $dst, $p, $q @ cmpLTMask" %}
1.7719 - ins_encode %{
1.7720 - Register p = $p$$Register;
1.7721 - Register q = $q$$Register;
1.7722 - Register dst = $dst$$Register;
1.7723 -
1.7724 - __ slt(dst, p, q);
1.7725 - __ subu(dst, R0, dst);
1.7726 + ins_encode %{
1.7727 + Register p = $p$$Register;
1.7728 + Register q = $q$$Register;
1.7729 + Register dst = $dst$$Register;
1.7730 +
1.7731 + __ slt(dst, p, q);
1.7732 + __ subu(dst, R0, dst);
1.7733 %}
1.7734 - ins_pipe( pipe_slow );
1.7735 + ins_pipe( pipe_slow );
1.7736 %}
1.7737
1.7738 instruct convP2B(mRegI dst, mRegP src) %{
1.7739 @@ -11865,11 +11791,11 @@
1.7740 match(Set dst (ConvI2D src));
1.7741 format %{ "conI2D $dst, $src @convI2D_reg" %}
1.7742 ins_encode %{
1.7743 - Register src = $src$$Register;
1.7744 - FloatRegister dst = $dst$$FloatRegister;
1.7745 - __ mtc1(src, dst);
1.7746 - __ cvt_d_w(dst, dst);
1.7747 - %}
1.7748 + Register src = $src$$Register;
1.7749 + FloatRegister dst = $dst$$FloatRegister;
1.7750 + __ mtc1(src, dst);
1.7751 + __ cvt_d_w(dst, dst);
1.7752 + %}
1.7753 ins_pipe( fpu_regF_regF );
1.7754 %}
1.7755
1.7756 @@ -11906,29 +11832,29 @@
1.7757 format %{ "convD2I $dst, $src\t# @ convD2I_reg_reg_fast" %}
1.7758
1.7759 ins_encode %{
1.7760 - FloatRegister src = $src$$FloatRegister;
1.7761 - Register dst = $dst$$Register;
1.7762 -
1.7763 - Label Done;
1.7764 -
1.7765 - __ trunc_w_d(F30, src);
1.7766 - // max_int: 2147483647
1.7767 - __ move(AT, 0x7fffffff);
1.7768 - __ mfc1(dst, F30);
1.7769 -
1.7770 - __ bne(dst, AT, Done);
1.7771 - __ delayed()->mtc1(R0, F30);
1.7772 -
1.7773 - __ cvt_d_w(F30, F30);
1.7774 - __ c_ult_d(src, F30);
1.7775 - __ bc1f(Done);
1.7776 - __ delayed()->addiu(T9, R0, -1);
1.7777 -
1.7778 - __ c_un_d(src, src); //NaN?
1.7779 - __ subu32(dst, T9, AT);
1.7780 - __ movt(dst, R0);
1.7781 -
1.7782 - __ bind(Done);
1.7783 + FloatRegister src = $src$$FloatRegister;
1.7784 + Register dst = $dst$$Register;
1.7785 +
1.7786 + Label Done;
1.7787 +
1.7788 + __ trunc_w_d(F30, src);
1.7789 + // max_int: 2147483647
1.7790 + __ move(AT, 0x7fffffff);
1.7791 + __ mfc1(dst, F30);
1.7792 +
1.7793 + __ bne(dst, AT, Done);
1.7794 + __ delayed()->mtc1(R0, F30);
1.7795 +
1.7796 + __ cvt_d_w(F30, F30);
1.7797 + __ c_ult_d(src, F30);
1.7798 + __ bc1f(Done);
1.7799 + __ delayed()->addiu(T9, R0, -1);
1.7800 +
1.7801 + __ c_un_d(src, src); //NaN?
1.7802 + __ subu32(dst, T9, AT);
1.7803 + __ movt(dst, R0);
1.7804 +
1.7805 + __ bind(Done);
1.7806 %}
1.7807 ins_pipe( pipe_slow );
1.7808 %}
1.7809 @@ -11941,22 +11867,22 @@
1.7810 format %{ "convD2I $dst, $src\t# @ convD2I_reg_reg_slow" %}
1.7811
1.7812 ins_encode %{
1.7813 - FloatRegister src = $src$$FloatRegister;
1.7814 - Register dst = $dst$$Register;
1.7815 - Label L;
1.7816 -
1.7817 - __ trunc_w_d(F30, src);
1.7818 - __ cfc1(AT, 31);
1.7819 - __ li(T9, 0x10000);
1.7820 - __ andr(AT, AT, T9);
1.7821 - __ beq(AT, R0, L);
1.7822 - __ delayed()->mfc1(dst, F30);
1.7823 -
1.7824 - __ mov_d(F12, src);
1.7825 - __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::d2i), 1);
1.7826 - __ move(dst, V0);
1.7827 - __ bind(L);
1.7828 -
1.7829 + FloatRegister src = $src$$FloatRegister;
1.7830 + Register dst = $dst$$Register;
1.7831 + Label L;
1.7832 +
1.7833 + __ trunc_w_d(F30, src);
1.7834 + __ cfc1(AT, 31);
1.7835 + __ li(T9, 0x10000);
1.7836 + __ andr(AT, AT, T9);
1.7837 + __ beq(AT, R0, L);
1.7838 + __ delayed()->mfc1(dst, F30);
1.7839 +
1.7840 + __ mov_d(F12, src);
1.7841 + __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::d2i), 1);
1.7842 + __ move(dst, V0);
1.7843 + __ bind(L);
1.7844 +
1.7845 %}
1.7846 ins_pipe( pipe_slow );
1.7847 %}
1.7848 @@ -12092,7 +12018,7 @@
1.7849 format %{ "RET #@Ret" %}
1.7850
1.7851 ins_encode %{
1.7852 - __ jr(RA);
1.7853 + __ jr(RA);
1.7854 __ nop();
1.7855 %}
1.7856
1.7857 @@ -12156,7 +12082,7 @@
1.7858 ins_encode %{
1.7859 Label &L = *($labl$$label);
1.7860 if(&L)
1.7861 - __ b(L);
1.7862 + __ b(L);
1.7863 else
1.7864 __ b(int(0));
1.7865 __ nop();
1.7866 @@ -12193,10 +12119,10 @@
1.7867 __ move(exception_pc, RA);
1.7868 __ move(exception_oop, oop);
1.7869
1.7870 - __ jr(target);
1.7871 + __ jr(target);
1.7872 __ nop();
1.7873 %}
1.7874 - ins_pipe( pipe_jump );
1.7875 + ins_pipe( pipe_jump );
1.7876 %}
1.7877
1.7878 // ============================================================================
1.7879 @@ -12316,59 +12242,59 @@
1.7880 ins_cost(125);
1.7881 format %{ "pref $mem\t# Prefetch allocation @ prefetchAllocNTA" %}
1.7882 ins_encode %{
1.7883 - int base = $mem$$base;
1.7884 - int index = $mem$$index;
1.7885 - int scale = $mem$$scale;
1.7886 - int disp = $mem$$disp;
1.7887 -
1.7888 - Register dst = R0;
1.7889 -
1.7890 - if( index != 0 ) {
1.7891 - if( Assembler::is_simm16(disp) ) {
1.7892 - if( UseLoongsonISA ) {
1.7893 - if (scale == 0) {
1.7894 - __ gslbx(dst, as_Register(base), as_Register(index), disp);
1.7895 - } else {
1.7896 - __ dsll(AT, as_Register(index), scale);
1.7897 - __ gslbx(dst, as_Register(base), AT, disp);
1.7898 - }
1.7899 - } else {
1.7900 - if (scale == 0) {
1.7901 - __ addu(AT, as_Register(base), as_Register(index));
1.7902 - } else {
1.7903 - __ dsll(AT, as_Register(index), scale);
1.7904 - __ addu(AT, as_Register(base), AT);
1.7905 - }
1.7906 - __ lb(dst, AT, disp);
1.7907 - }
1.7908 - } else {
1.7909 - if (scale == 0) {
1.7910 - __ addu(AT, as_Register(base), as_Register(index));
1.7911 - } else {
1.7912 - __ dsll(AT, as_Register(index), scale);
1.7913 - __ addu(AT, as_Register(base), AT);
1.7914 - }
1.7915 - __ move(T9, disp);
1.7916 - if( UseLoongsonISA ) {
1.7917 - __ gslbx(dst, AT, T9, 0);
1.7918 - } else {
1.7919 - __ addu(AT, AT, T9);
1.7920 - __ lb(dst, AT, 0);
1.7921 - }
1.7922 - }
1.7923 - } else {
1.7924 - if( Assembler::is_simm16(disp) ) {
1.7925 - __ lb(dst, as_Register(base), disp);
1.7926 - } else {
1.7927 - __ move(T9, disp);
1.7928 - if( UseLoongsonISA ) {
1.7929 - __ gslbx(dst, as_Register(base), T9, 0);
1.7930 - } else {
1.7931 - __ addu(AT, as_Register(base), T9);
1.7932 - __ lb(dst, AT, 0);
1.7933 - }
1.7934 - }
1.7935 - }
1.7936 + int base = $mem$$base;
1.7937 + int index = $mem$$index;
1.7938 + int scale = $mem$$scale;
1.7939 + int disp = $mem$$disp;
1.7940 +
1.7941 + Register dst = R0;
1.7942 +
1.7943 + if( index != 0 ) {
1.7944 + if( Assembler::is_simm16(disp) ) {
1.7945 + if( UseLoongsonISA ) {
1.7946 + if (scale == 0) {
1.7947 + __ gslbx(dst, as_Register(base), as_Register(index), disp);
1.7948 + } else {
1.7949 + __ dsll(AT, as_Register(index), scale);
1.7950 + __ gslbx(dst, as_Register(base), AT, disp);
1.7951 + }
1.7952 + } else {
1.7953 + if (scale == 0) {
1.7954 + __ addu(AT, as_Register(base), as_Register(index));
1.7955 + } else {
1.7956 + __ dsll(AT, as_Register(index), scale);
1.7957 + __ addu(AT, as_Register(base), AT);
1.7958 + }
1.7959 + __ lb(dst, AT, disp);
1.7960 + }
1.7961 + } else {
1.7962 + if (scale == 0) {
1.7963 + __ addu(AT, as_Register(base), as_Register(index));
1.7964 + } else {
1.7965 + __ dsll(AT, as_Register(index), scale);
1.7966 + __ addu(AT, as_Register(base), AT);
1.7967 + }
1.7968 + __ move(T9, disp);
1.7969 + if( UseLoongsonISA ) {
1.7970 + __ gslbx(dst, AT, T9, 0);
1.7971 + } else {
1.7972 + __ addu(AT, AT, T9);
1.7973 + __ lb(dst, AT, 0);
1.7974 + }
1.7975 + }
1.7976 + } else {
1.7977 + if( Assembler::is_simm16(disp) ) {
1.7978 + __ lb(dst, as_Register(base), disp);
1.7979 + } else {
1.7980 + __ move(T9, disp);
1.7981 + if( UseLoongsonISA ) {
1.7982 + __ gslbx(dst, as_Register(base), T9, 0);
1.7983 + } else {
1.7984 + __ addu(AT, as_Register(base), T9);
1.7985 + __ lb(dst, AT, 0);
1.7986 + }
1.7987 + }
1.7988 + }
1.7989 %}
1.7990 ins_pipe(pipe_slow);
1.7991 %}
1.7992 @@ -12449,15 +12375,15 @@
1.7993 int con_offset = $constantoffset($src);
1.7994
1.7995 if (Assembler::is_simm16(con_offset)) {
1.7996 - __ lwc1($dst$$FloatRegister, $constanttablebase, con_offset);
1.7997 + __ lwc1($dst$$FloatRegister, $constanttablebase, con_offset);
1.7998 } else {
1.7999 - __ set64(AT, con_offset);
1.8000 - if (UseLoongsonISA) {
1.8001 - __ gslwxc1($dst$$FloatRegister, $constanttablebase, AT, 0);
1.8002 - } else {
1.8003 - __ daddu(AT, $constanttablebase, AT);
1.8004 - __ lwc1($dst$$FloatRegister, AT, 0);
1.8005 - }
1.8006 + __ set64(AT, con_offset);
1.8007 + if (UseLoongsonISA) {
1.8008 + __ gslwxc1($dst$$FloatRegister, $constanttablebase, AT, 0);
1.8009 + } else {
1.8010 + __ daddu(AT, $constanttablebase, AT);
1.8011 + __ lwc1($dst$$FloatRegister, AT, 0);
1.8012 + }
1.8013 }
1.8014 %}
1.8015 ins_pipe( fpu_loadF );
1.8016 @@ -12472,7 +12398,7 @@
1.8017 ins_encode %{
1.8018 FloatRegister dst = as_FloatRegister($dst$$reg);
1.8019
1.8020 - __ dmtc1(R0, dst);
1.8021 + __ dmtc1(R0, dst);
1.8022 %}
1.8023 ins_pipe( fpu_loadF );
1.8024 %}
1.8025 @@ -12486,15 +12412,15 @@
1.8026 int con_offset = $constantoffset($src);
1.8027
1.8028 if (Assembler::is_simm16(con_offset)) {
1.8029 - __ ldc1($dst$$FloatRegister, $constanttablebase, con_offset);
1.8030 + __ ldc1($dst$$FloatRegister, $constanttablebase, con_offset);
1.8031 } else {
1.8032 - __ set64(AT, con_offset);
1.8033 - if (UseLoongsonISA) {
1.8034 - __ gsldxc1($dst$$FloatRegister, $constanttablebase, AT, 0);
1.8035 - } else {
1.8036 - __ daddu(AT, $constanttablebase, AT);
1.8037 - __ ldc1($dst$$FloatRegister, AT, 0);
1.8038 - }
1.8039 + __ set64(AT, con_offset);
1.8040 + if (UseLoongsonISA) {
1.8041 + __ gsldxc1($dst$$FloatRegister, $constanttablebase, AT, 0);
1.8042 + } else {
1.8043 + __ daddu(AT, $constanttablebase, AT);
1.8044 + __ ldc1($dst$$FloatRegister, AT, 0);
1.8045 + }
1.8046 }
1.8047 %}
1.8048 ins_pipe( fpu_loadF );
1.8049 @@ -12522,66 +12448,66 @@
1.8050 int disp = $mem$$disp;
1.8051
1.8052 if( index != 0 ) {
1.8053 - if ( UseLoongsonISA ) {
1.8054 - if ( Assembler::is_simm(disp, 8) ) {
1.8055 - if ( scale == 0 ) {
1.8056 - __ gsswx(R0, as_Register(base), as_Register(index), disp);
1.8057 - } else {
1.8058 - __ dsll(T9, as_Register(index), scale);
1.8059 - __ gsswx(R0, as_Register(base), T9, disp);
1.8060 - }
1.8061 - } else if ( Assembler::is_simm16(disp) ) {
1.8062 - if ( scale == 0 ) {
1.8063 - __ daddu(AT, as_Register(base), as_Register(index));
1.8064 - } else {
1.8065 - __ dsll(T9, as_Register(index), scale);
1.8066 - __ daddu(AT, as_Register(base), T9);
1.8067 - }
1.8068 - __ sw(R0, AT, disp);
1.8069 - } else {
1.8070 - if ( scale == 0 ) {
1.8071 - __ move(T9, disp);
1.8072 - __ daddu(AT, as_Register(index), T9);
1.8073 - __ gsswx(R0, as_Register(base), AT, 0);
1.8074 - } else {
1.8075 - __ dsll(T9, as_Register(index), scale);
1.8076 - __ move(AT, disp);
1.8077 - __ daddu(AT, AT, T9);
1.8078 - __ gsswx(R0, as_Register(base), AT, 0);
1.8079 - }
1.8080 - }
1.8081 - } else { //not use loongson isa
1.8082 - if(scale != 0) {
1.8083 - __ dsll(T9, as_Register(index), scale);
1.8084 - __ daddu(AT, as_Register(base), T9);
1.8085 - } else {
1.8086 - __ daddu(AT, as_Register(base), as_Register(index));
1.8087 - }
1.8088 - if( Assembler::is_simm16(disp) ) {
1.8089 - __ sw(R0, AT, disp);
1.8090 - } else {
1.8091 - __ move(T9, disp);
1.8092 - __ daddu(AT, AT, T9);
1.8093 - __ sw(R0, AT, 0);
1.8094 - }
1.8095 - }
1.8096 + if ( UseLoongsonISA ) {
1.8097 + if ( Assembler::is_simm(disp, 8) ) {
1.8098 + if ( scale == 0 ) {
1.8099 + __ gsswx(R0, as_Register(base), as_Register(index), disp);
1.8100 + } else {
1.8101 + __ dsll(T9, as_Register(index), scale);
1.8102 + __ gsswx(R0, as_Register(base), T9, disp);
1.8103 + }
1.8104 + } else if ( Assembler::is_simm16(disp) ) {
1.8105 + if ( scale == 0 ) {
1.8106 + __ daddu(AT, as_Register(base), as_Register(index));
1.8107 + } else {
1.8108 + __ dsll(T9, as_Register(index), scale);
1.8109 + __ daddu(AT, as_Register(base), T9);
1.8110 + }
1.8111 + __ sw(R0, AT, disp);
1.8112 + } else {
1.8113 + if ( scale == 0 ) {
1.8114 + __ move(T9, disp);
1.8115 + __ daddu(AT, as_Register(index), T9);
1.8116 + __ gsswx(R0, as_Register(base), AT, 0);
1.8117 + } else {
1.8118 + __ dsll(T9, as_Register(index), scale);
1.8119 + __ move(AT, disp);
1.8120 + __ daddu(AT, AT, T9);
1.8121 + __ gsswx(R0, as_Register(base), AT, 0);
1.8122 + }
1.8123 + }
1.8124 + } else { //not use loongson isa
1.8125 + if(scale != 0) {
1.8126 + __ dsll(T9, as_Register(index), scale);
1.8127 + __ daddu(AT, as_Register(base), T9);
1.8128 + } else {
1.8129 + __ daddu(AT, as_Register(base), as_Register(index));
1.8130 + }
1.8131 + if( Assembler::is_simm16(disp) ) {
1.8132 + __ sw(R0, AT, disp);
1.8133 + } else {
1.8134 + __ move(T9, disp);
1.8135 + __ daddu(AT, AT, T9);
1.8136 + __ sw(R0, AT, 0);
1.8137 + }
1.8138 + }
1.8139 } else { //index is 0
1.8140 - if ( UseLoongsonISA ) {
1.8141 - if ( Assembler::is_simm16(disp) ) {
1.8142 - __ sw(R0, as_Register(base), disp);
1.8143 - } else {
1.8144 - __ move(T9, disp);
1.8145 - __ gsswx(R0, as_Register(base), T9, 0);
1.8146 - }
1.8147 - } else {
1.8148 - if( Assembler::is_simm16(disp) ) {
1.8149 - __ sw(R0, as_Register(base), disp);
1.8150 - } else {
1.8151 - __ move(T9, disp);
1.8152 - __ daddu(AT, as_Register(base), T9);
1.8153 - __ sw(R0, AT, 0);
1.8154 - }
1.8155 - }
1.8156 + if ( UseLoongsonISA ) {
1.8157 + if ( Assembler::is_simm16(disp) ) {
1.8158 + __ sw(R0, as_Register(base), disp);
1.8159 + } else {
1.8160 + __ move(T9, disp);
1.8161 + __ gsswx(R0, as_Register(base), T9, 0);
1.8162 + }
1.8163 + } else {
1.8164 + if( Assembler::is_simm16(disp) ) {
1.8165 + __ sw(R0, as_Register(base), disp);
1.8166 + } else {
1.8167 + __ move(T9, disp);
1.8168 + __ daddu(AT, as_Register(base), T9);
1.8169 + __ sw(R0, AT, 0);
1.8170 + }
1.8171 + }
1.8172 }
1.8173 %}
1.8174 ins_pipe( ialu_storeI );
1.8175 @@ -12631,67 +12557,67 @@
1.8176 __ cvt_d_w(F30, F30);
1.8177
1.8178 if( index != 0 ) {
1.8179 - if ( UseLoongsonISA ) {
1.8180 - if ( Assembler::is_simm(disp, 8) ) {
1.8181 - if (scale == 0) {
1.8182 - __ gssdxc1(F30, as_Register(base), as_Register(index), disp);
1.8183 - } else {
1.8184 - __ dsll(T9, as_Register(index), scale);
1.8185 - __ gssdxc1(F30, as_Register(base), T9, disp);
1.8186 - }
1.8187 - } else if ( Assembler::is_simm16(disp) ) {
1.8188 - if (scale == 0) {
1.8189 - __ daddu(AT, as_Register(base), as_Register(index));
1.8190 - __ sdc1(F30, AT, disp);
1.8191 - } else {
1.8192 - __ dsll(T9, as_Register(index), scale);
1.8193 - __ daddu(AT, as_Register(base), T9);
1.8194 - __ sdc1(F30, AT, disp);
1.8195 - }
1.8196 - } else {
1.8197 - if (scale == 0) {
1.8198 - __ move(T9, disp);
1.8199 - __ daddu(AT, as_Register(index), T9);
1.8200 - __ gssdxc1(F30, as_Register(base), AT, 0);
1.8201 - } else {
1.8202 - __ move(T9, disp);
1.8203 - __ dsll(AT, as_Register(index), scale);
1.8204 - __ daddu(AT, AT, T9);
1.8205 - __ gssdxc1(F30, as_Register(base), AT, 0);
1.8206 - }
1.8207 - }
1.8208 - } else { // not use loongson isa
1.8209 - if(scale != 0) {
1.8210 - __ dsll(T9, as_Register(index), scale);
1.8211 - __ daddu(AT, as_Register(base), T9);
1.8212 - } else {
1.8213 - __ daddu(AT, as_Register(base), as_Register(index));
1.8214 - }
1.8215 - if( Assembler::is_simm16(disp) ) {
1.8216 - __ sdc1(F30, AT, disp);
1.8217 - } else {
1.8218 - __ move(T9, disp);
1.8219 - __ daddu(AT, AT, T9);
1.8220 - __ sdc1(F30, AT, 0);
1.8221 - }
1.8222 - }
1.8223 + if ( UseLoongsonISA ) {
1.8224 + if ( Assembler::is_simm(disp, 8) ) {
1.8225 + if (scale == 0) {
1.8226 + __ gssdxc1(F30, as_Register(base), as_Register(index), disp);
1.8227 + } else {
1.8228 + __ dsll(T9, as_Register(index), scale);
1.8229 + __ gssdxc1(F30, as_Register(base), T9, disp);
1.8230 + }
1.8231 + } else if ( Assembler::is_simm16(disp) ) {
1.8232 + if (scale == 0) {
1.8233 + __ daddu(AT, as_Register(base), as_Register(index));
1.8234 + __ sdc1(F30, AT, disp);
1.8235 + } else {
1.8236 + __ dsll(T9, as_Register(index), scale);
1.8237 + __ daddu(AT, as_Register(base), T9);
1.8238 + __ sdc1(F30, AT, disp);
1.8239 + }
1.8240 + } else {
1.8241 + if (scale == 0) {
1.8242 + __ move(T9, disp);
1.8243 + __ daddu(AT, as_Register(index), T9);
1.8244 + __ gssdxc1(F30, as_Register(base), AT, 0);
1.8245 + } else {
1.8246 + __ move(T9, disp);
1.8247 + __ dsll(AT, as_Register(index), scale);
1.8248 + __ daddu(AT, AT, T9);
1.8249 + __ gssdxc1(F30, as_Register(base), AT, 0);
1.8250 + }
1.8251 + }
1.8252 + } else { // not use loongson isa
1.8253 + if(scale != 0) {
1.8254 + __ dsll(T9, as_Register(index), scale);
1.8255 + __ daddu(AT, as_Register(base), T9);
1.8256 + } else {
1.8257 + __ daddu(AT, as_Register(base), as_Register(index));
1.8258 + }
1.8259 + if( Assembler::is_simm16(disp) ) {
1.8260 + __ sdc1(F30, AT, disp);
1.8261 + } else {
1.8262 + __ move(T9, disp);
1.8263 + __ daddu(AT, AT, T9);
1.8264 + __ sdc1(F30, AT, 0);
1.8265 + }
1.8266 + }
1.8267 } else {// index is 0
1.8268 - if ( UseLoongsonISA ) {
1.8269 - if ( Assembler::is_simm16(disp) ) {
1.8270 - __ sdc1(F30, as_Register(base), disp);
1.8271 - } else {
1.8272 - __ move(T9, disp);
1.8273 - __ gssdxc1(F30, as_Register(base), T9, 0);
1.8274 - }
1.8275 - } else {
1.8276 - if( Assembler::is_simm16(disp) ) {
1.8277 - __ sdc1(F30, as_Register(base), disp);
1.8278 - } else {
1.8279 - __ move(T9, disp);
1.8280 - __ daddu(AT, as_Register(base), T9);
1.8281 - __ sdc1(F30, AT, 0);
1.8282 - }
1.8283 - }
1.8284 + if ( UseLoongsonISA ) {
1.8285 + if ( Assembler::is_simm16(disp) ) {
1.8286 + __ sdc1(F30, as_Register(base), disp);
1.8287 + } else {
1.8288 + __ move(T9, disp);
1.8289 + __ gssdxc1(F30, as_Register(base), T9, 0);
1.8290 + }
1.8291 + } else {
1.8292 + if( Assembler::is_simm16(disp) ) {
1.8293 + __ sdc1(F30, as_Register(base), disp);
1.8294 + } else {
1.8295 + __ move(T9, disp);
1.8296 + __ daddu(AT, as_Register(base), T9);
1.8297 + __ sdc1(F30, AT, 0);
1.8298 + }
1.8299 + }
1.8300 }
1.8301 %}
1.8302 ins_pipe( ialu_storeI );
1.8303 @@ -12887,7 +12813,7 @@
1.8304 predicate(Universe::narrow_oop_shift() == 0);
1.8305 match(Set dst mem);
1.8306
1.8307 - ins_cost(110);
1.8308 + ins_cost(110);
1.8309 format %{ "leaq $dst, $mem\t# ptr off8narrow @ leaP8Narrow" %}
1.8310 ins_encode %{
1.8311 Register dst = $dst$$Register;
1.8312 @@ -12913,12 +12839,12 @@
1.8313 int disp = $mem$$disp;
1.8314
1.8315 if (scale == 0) {
1.8316 - __ daddu(AT, base, index);
1.8317 - __ daddiu(dst, AT, disp);
1.8318 + __ daddu(AT, base, index);
1.8319 + __ daddiu(dst, AT, disp);
1.8320 } else {
1.8321 - __ dsll(AT, index, scale);
1.8322 - __ daddu(AT, base, AT);
1.8323 - __ daddiu(dst, AT, disp);
1.8324 + __ dsll(AT, index, scale);
1.8325 + __ daddu(AT, base, AT);
1.8326 + __ daddiu(dst, AT, disp);
1.8327 }
1.8328 %}
1.8329
1.8330 @@ -12952,7 +12878,7 @@
1.8331 instruct jmpLoopEnd(cmpOp cop, mRegI src1, mRegI src2, label labl) %{
1.8332 match(CountedLoopEnd cop (CmpI src1 src2));
1.8333 effect(USE labl);
1.8334 -
1.8335 +
1.8336 ins_cost(300);
1.8337 format %{ "J$cop $src1, $src2, $labl\t# Loop end @ jmpLoopEnd" %}
1.8338 ins_encode %{
1.8339 @@ -12961,51 +12887,50 @@
1.8340 Label &L = *($labl$$label);
1.8341 int flag = $cop$$cmpcode;
1.8342
1.8343 - switch(flag)
1.8344 - {
1.8345 + switch(flag) {
1.8346 case 0x01: //equal
1.8347 - if (&L)
1.8348 - __ beq(op1, op2, L);
1.8349 - else
1.8350 - __ beq(op1, op2, (int)0);
1.8351 + if (&L)
1.8352 + __ beq(op1, op2, L);
1.8353 + else
1.8354 + __ beq(op1, op2, (int)0);
1.8355 break;
1.8356 case 0x02: //not_equal
1.8357 - if (&L)
1.8358 - __ bne(op1, op2, L);
1.8359 - else
1.8360 - __ bne(op1, op2, (int)0);
1.8361 + if (&L)
1.8362 + __ bne(op1, op2, L);
1.8363 + else
1.8364 + __ bne(op1, op2, (int)0);
1.8365 break;
1.8366 case 0x03: //above
1.8367 __ slt(AT, op2, op1);
1.8368 if(&L)
1.8369 - __ bne(AT, R0, L);
1.8370 - else
1.8371 - __ bne(AT, R0, (int)0);
1.8372 + __ bne(AT, R0, L);
1.8373 + else
1.8374 + __ bne(AT, R0, (int)0);
1.8375 break;
1.8376 case 0x04: //above_equal
1.8377 __ slt(AT, op1, op2);
1.8378 if(&L)
1.8379 - __ beq(AT, R0, L);
1.8380 - else
1.8381 - __ beq(AT, R0, (int)0);
1.8382 + __ beq(AT, R0, L);
1.8383 + else
1.8384 + __ beq(AT, R0, (int)0);
1.8385 break;
1.8386 case 0x05: //below
1.8387 __ slt(AT, op1, op2);
1.8388 if(&L)
1.8389 - __ bne(AT, R0, L);
1.8390 - else
1.8391 - __ bne(AT, R0, (int)0);
1.8392 + __ bne(AT, R0, L);
1.8393 + else
1.8394 + __ bne(AT, R0, (int)0);
1.8395 break;
1.8396 case 0x06: //below_equal
1.8397 __ slt(AT, op2, op1);
1.8398 if(&L)
1.8399 - __ beq(AT, R0, L);
1.8400 - else
1.8401 - __ beq(AT, R0, (int)0);
1.8402 - break;
1.8403 + __ beq(AT, R0, L);
1.8404 + else
1.8405 + __ beq(AT, R0, (int)0);
1.8406 + break;
1.8407 default:
1.8408 - Unimplemented();
1.8409 - }
1.8410 + Unimplemented();
1.8411 + }
1.8412 __ nop();
1.8413 %}
1.8414 ins_pipe( pipe_jump );
1.8415 @@ -13015,7 +12940,7 @@
1.8416 instruct jmpLoopEnd_reg_immI(cmpOp cop, mRegI src1, immI src2, label labl) %{
1.8417 match(CountedLoopEnd cop (CmpI src1 src2));
1.8418 effect(USE labl);
1.8419 -
1.8420 +
1.8421 ins_cost(300);
1.8422 format %{ "J$cop $src1, $src2, $labl\t# Loop end @ jmpLoopEnd_reg_immI" %}
1.8423 ins_encode %{
1.8424 @@ -13026,51 +12951,50 @@
1.8425
1.8426 __ move(op2, $src2$$constant);
1.8427
1.8428 - switch(flag)
1.8429 - {
1.8430 + switch(flag) {
1.8431 case 0x01: //equal
1.8432 - if (&L)
1.8433 - __ beq(op1, op2, L);
1.8434 - else
1.8435 - __ beq(op1, op2, (int)0);
1.8436 + if (&L)
1.8437 + __ beq(op1, op2, L);
1.8438 + else
1.8439 + __ beq(op1, op2, (int)0);
1.8440 break;
1.8441 case 0x02: //not_equal
1.8442 - if (&L)
1.8443 - __ bne(op1, op2, L);
1.8444 - else
1.8445 - __ bne(op1, op2, (int)0);
1.8446 + if (&L)
1.8447 + __ bne(op1, op2, L);
1.8448 + else
1.8449 + __ bne(op1, op2, (int)0);
1.8450 break;
1.8451 case 0x03: //above
1.8452 __ slt(AT, op2, op1);
1.8453 if(&L)
1.8454 - __ bne(AT, R0, L);
1.8455 - else
1.8456 - __ bne(AT, R0, (int)0);
1.8457 + __ bne(AT, R0, L);
1.8458 + else
1.8459 + __ bne(AT, R0, (int)0);
1.8460 break;
1.8461 case 0x04: //above_equal
1.8462 __ slt(AT, op1, op2);
1.8463 if(&L)
1.8464 - __ beq(AT, R0, L);
1.8465 - else
1.8466 - __ beq(AT, R0, (int)0);
1.8467 + __ beq(AT, R0, L);
1.8468 + else
1.8469 + __ beq(AT, R0, (int)0);
1.8470 break;
1.8471 case 0x05: //below
1.8472 __ slt(AT, op1, op2);
1.8473 if(&L)
1.8474 - __ bne(AT, R0, L);
1.8475 - else
1.8476 - __ bne(AT, R0, (int)0);
1.8477 + __ bne(AT, R0, L);
1.8478 + else
1.8479 + __ bne(AT, R0, (int)0);
1.8480 break;
1.8481 case 0x06: //below_equal
1.8482 __ slt(AT, op2, op1);
1.8483 if(&L)
1.8484 - __ beq(AT, R0, L);
1.8485 - else
1.8486 - __ beq(AT, R0, (int)0);
1.8487 - break;
1.8488 + __ beq(AT, R0, L);
1.8489 + else
1.8490 + __ beq(AT, R0, (int)0);
1.8491 + break;
1.8492 default:
1.8493 - Unimplemented();
1.8494 - }
1.8495 + Unimplemented();
1.8496 + }
1.8497 __ nop();
1.8498 %}
1.8499 ins_pipe( pipe_jump );
1.8500 @@ -13088,22 +13012,21 @@
1.8501
1.8502 ins_encode %{
1.8503 Label &L = *($labl$$label);
1.8504 - switch($cop$$cmpcode)
1.8505 - {
1.8506 + switch($cop$$cmpcode) {
1.8507 case 0x01: //equal
1.8508 - if (&L)
1.8509 - __ bne(AT, R0, L);
1.8510 - else
1.8511 - __ bne(AT, R0, (int)0);
1.8512 + if (&L)
1.8513 + __ bne(AT, R0, L);
1.8514 + else
1.8515 + __ bne(AT, R0, (int)0);
1.8516 break;
1.8517 case 0x02: //not equal
1.8518 - if (&L)
1.8519 - __ beq(AT, R0, L);
1.8520 - else
1.8521 - __ beq(AT, R0, (int)0);
1.8522 + if (&L)
1.8523 + __ beq(AT, R0, L);
1.8524 + else
1.8525 + __ beq(AT, R0, (int)0);
1.8526 break;
1.8527 default:
1.8528 - Unimplemented();
1.8529 + Unimplemented();
1.8530 }
1.8531 __ nop();
1.8532 %}
1.8533 @@ -13142,28 +13065,27 @@
1.8534 Address addr(as_Register($mem$$base), $mem$$disp);
1.8535 Label again, failure;
1.8536
1.8537 -// int base = $mem$$base;
1.8538 int index = $mem$$index;
1.8539 int scale = $mem$$scale;
1.8540 int disp = $mem$$disp;
1.8541 -
1.8542 - guarantee(Assembler::is_simm16(disp), "");
1.8543 +
1.8544 + guarantee(Assembler::is_simm16(disp), "");
1.8545
1.8546 if( index != 0 ) {
1.8547 - __ stop("in storeIConditional: index != 0");
1.8548 + __ stop("in storeIConditional: index != 0");
1.8549 } else {
1.8550 - __ bind(again);
1.8551 - if(!Use3A2000) __ sync();
1.8552 - __ ll(AT, addr);
1.8553 - __ bne(AT, oldval, failure);
1.8554 - __ delayed()->addu(AT, R0, R0);
1.8555 -
1.8556 - __ addu(AT, newval, R0);
1.8557 - __ sc(AT, addr);
1.8558 - __ beq(AT, R0, again);
1.8559 - __ delayed()->addiu(AT, R0, 0xFF);
1.8560 - __ bind(failure);
1.8561 - __ sync();
1.8562 + __ bind(again);
1.8563 + if(!Use3A2000) __ sync();
1.8564 + __ ll(AT, addr);
1.8565 + __ bne(AT, oldval, failure);
1.8566 + __ delayed()->addu(AT, R0, R0);
1.8567 +
1.8568 + __ addu(AT, newval, R0);
1.8569 + __ sc(AT, addr);
1.8570 + __ beq(AT, R0, again);
1.8571 + __ delayed()->addiu(AT, R0, 0xFF);
1.8572 + __ bind(failure);
1.8573 + __ sync();
1.8574 }
1.8575 %}
1.8576
1.8577 @@ -13179,21 +13101,21 @@
1.8578
1.8579 format %{ "cmpxchg $mem, $newval\t# If $oldval == $mem then store $newval into $mem" %}
1.8580 ins_encode%{
1.8581 - Register oldval = $oldval$$Register;
1.8582 - Register newval = $newval$$Register;
1.8583 - Address addr((Register)$mem$$base, $mem$$disp);
1.8584 -
1.8585 - int index = $mem$$index;
1.8586 - int scale = $mem$$scale;
1.8587 - int disp = $mem$$disp;
1.8588 -
1.8589 - guarantee(Assembler::is_simm16(disp), "");
1.8590 -
1.8591 - if( index != 0 ) {
1.8592 - __ stop("in storeIConditional: index != 0");
1.8593 - } else {
1.8594 - __ cmpxchg(newval, addr, oldval);
1.8595 - }
1.8596 + Register oldval = $oldval$$Register;
1.8597 + Register newval = $newval$$Register;
1.8598 + Address addr((Register)$mem$$base, $mem$$disp);
1.8599 +
1.8600 + int index = $mem$$index;
1.8601 + int scale = $mem$$scale;
1.8602 + int disp = $mem$$disp;
1.8603 +
1.8604 + guarantee(Assembler::is_simm16(disp), "");
1.8605 +
1.8606 + if( index != 0 ) {
1.8607 + __ stop("in storeIConditional: index != 0");
1.8608 + } else {
1.8609 + __ cmpxchg(newval, addr, oldval);
1.8610 + }
1.8611 %}
1.8612 ins_pipe( long_memory_op );
1.8613 %}
1.8614 @@ -13212,7 +13134,7 @@
1.8615 Register newval = $newval$$Register;
1.8616 Register oldval = $oldval$$Register;
1.8617 Register res = $res$$Register;
1.8618 - Address addr($mem_ptr$$Register, 0);
1.8619 + Address addr($mem_ptr$$Register, 0);
1.8620 Label L;
1.8621
1.8622 __ cmpxchg32(newval, addr, oldval);
1.8623 @@ -13232,7 +13154,7 @@
1.8624 Register newval = $newval$$Register;
1.8625 Register oldval = $oldval$$Register;
1.8626 Register res = $res$$Register;
1.8627 - Address addr($mem_ptr$$Register, 0);
1.8628 + Address addr($mem_ptr$$Register, 0);
1.8629 Label L;
1.8630
1.8631 __ cmpxchg(newval, addr, oldval);
1.8632 @@ -13251,7 +13173,7 @@
1.8633 Register newval = $newval$$Register;
1.8634 Register oldval = $oldval$$Register;
1.8635 Register res = $res$$Register;
1.8636 - Address addr($mem_ptr$$Register, 0);
1.8637 + Address addr($mem_ptr$$Register, 0);
1.8638 Label L;
1.8639
1.8640 /* 2013/7/19 Jin: cmpxchg32 is implemented with ll/sc, which will do sign extension.
1.8641 @@ -13304,7 +13226,7 @@
1.8642
1.8643 __ slt(AT, src, dst);
1.8644 __ movn(dst, src, AT);
1.8645 -
1.8646 +
1.8647 %}
1.8648
1.8649 ins_pipe( pipe_slow );
1.8650 @@ -13397,7 +13319,7 @@
1.8651 if (src1 == dst) {
1.8652 __ dinsu(dst, src2, 32, 32);
1.8653 } else if (src2 == dst) {
1.8654 - __ dsll32(dst, dst, 0);
1.8655 + __ dsll32(dst, dst, 0);
1.8656 __ dins(dst, src1, 0, 32);
1.8657 } else {
1.8658 __ dext(dst, src1, 0, 32);
1.8659 @@ -13513,7 +13435,7 @@
1.8660 %}
1.8661
1.8662 //---------- Zeros Count Instructions ------------------------------------------
1.8663 -// CountLeadingZerosINode CountTrailingZerosINode
1.8664 +// CountLeadingZerosINode CountTrailingZerosINode
1.8665 instruct countLeadingZerosI(mRegI dst, mRegI src) %{
1.8666 predicate(UseCountLeadingZerosInstruction);
1.8667 match(Set dst (CountLeadingZerosI src));
1.8668 @@ -13917,7 +13839,7 @@
1.8669 //----------PEEPHOLE RULES-----------------------------------------------------
1.8670 // These must follow all instruction definitions as they use the names
1.8671 // defined in the instructions definitions.
1.8672 -//
1.8673 +//
1.8674 // peepmatch ( root_instr_name [preceeding_instruction]* );
1.8675 //
1.8676 // peepconstraint %{
1.8677 @@ -13930,16 +13852,16 @@
1.8678 // // in the replacement instruction's match rule
1.8679 //
1.8680 // ---------VM FLAGS---------------------------------------------------------
1.8681 -//
1.8682 +//
1.8683 // All peephole optimizations can be turned off using -XX:-OptoPeephole
1.8684 -//
1.8685 +//
1.8686 // Each peephole rule is given an identifying number starting with zero and
1.8687 // increasing by one in the order seen by the parser. An individual peephole
1.8688 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
1.8689 // on the command-line.
1.8690 -//
1.8691 +//
1.8692 // ---------CURRENT LIMITATIONS----------------------------------------------
1.8693 -//
1.8694 +//
1.8695 // Only match adjacent instructions in same basic block
1.8696 // Only equality constraints
1.8697 // Only constraints between operands, not (0.dest_reg == EAX_enc)
1.8698 @@ -13951,45 +13873,45 @@
1.8699 // instruct movI(eRegI dst, eRegI src) %{
1.8700 // match(Set dst (CopyI src));
1.8701 // %}
1.8702 -//
1.8703 +//
1.8704 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
1.8705 // match(Set dst (AddI dst src));
1.8706 // effect(KILL cr);
1.8707 // %}
1.8708 -//
1.8709 +//
1.8710 // // Change (inc mov) to lea
1.8711 // peephole %{
1.8712 // // increment preceeded by register-register move
1.8713 // peepmatch ( incI_eReg movI );
1.8714 -// // require that the destination register of the increment
1.8715 +// // require that the destination register of the increment
1.8716 // // match the destination register of the move
1.8717 // peepconstraint ( 0.dst == 1.dst );
1.8718 // // construct a replacement instruction that sets
1.8719 // // the destination to ( move's source register + one )
1.8720 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
1.8721 // %}
1.8722 -//
1.8723 -// Implementation no longer uses movX instructions since
1.8724 +//
1.8725 +// Implementation no longer uses movX instructions since
1.8726 // machine-independent system no longer uses CopyX nodes.
1.8727 -//
1.8728 +//
1.8729 // peephole %{
1.8730 // peepmatch ( incI_eReg movI );
1.8731 // peepconstraint ( 0.dst == 1.dst );
1.8732 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
1.8733 // %}
1.8734 -//
1.8735 +//
1.8736 // peephole %{
1.8737 // peepmatch ( decI_eReg movI );
1.8738 // peepconstraint ( 0.dst == 1.dst );
1.8739 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
1.8740 // %}
1.8741 -//
1.8742 +//
1.8743 // peephole %{
1.8744 // peepmatch ( addI_eReg_imm movI );
1.8745 // peepconstraint ( 0.dst == 1.dst );
1.8746 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
1.8747 // %}
1.8748 -//
1.8749 +//
1.8750 // peephole %{
1.8751 // peepmatch ( addP_eReg_imm movP );
1.8752 // peepconstraint ( 0.dst == 1.dst );
1.8753 @@ -14000,11 +13922,11 @@
1.8754 // instruct storeI(memory mem, eRegI src) %{
1.8755 // match(Set mem (StoreI mem src));
1.8756 // %}
1.8757 -//
1.8758 +//
1.8759 // instruct loadI(eRegI dst, memory mem) %{
1.8760 // match(Set dst (LoadI mem));
1.8761 // %}
1.8762 -//
1.8763 +//
1.8764 //peephole %{
1.8765 // peepmatch ( loadI storeI );
1.8766 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
