1.1 --- a/src/cpu/x86/vm/assembler_x86.cpp Mon Mar 21 14:58:37 2016 -0700 1.2 +++ b/src/cpu/x86/vm/assembler_x86.cpp Wed Feb 17 13:40:12 2016 +0300 1.3 @@ -2318,6 +2318,13 @@ 1.4 emit_arith(0x0B, 0xC0, dst, src); 1.5 } 1.6 1.7 +void Assembler::orl(Address dst, Register src) { 1.8 + InstructionMark im(this); 1.9 + prefix(dst, src); 1.10 + emit_int8(0x09); 1.11 + emit_operand(src, dst); 1.12 +} 1.13 + 1.14 void Assembler::packuswb(XMMRegister dst, Address src) { 1.15 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1.16 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); 1.17 @@ -5613,6 +5620,19 @@ 1.18 } 1.19 } 1.20 1.21 +void Assembler::rcrq(Register dst, int imm8) { 1.22 + assert(isShiftCount(imm8 >> 1), "illegal shift count"); 1.23 + int encode = prefixq_and_encode(dst->encoding()); 1.24 + if (imm8 == 1) { 1.25 + emit_int8((unsigned char)0xD1); 1.26 + emit_int8((unsigned char)(0xD8 | encode)); 1.27 + } else { 1.28 + emit_int8((unsigned char)0xC1); 1.29 + emit_int8((unsigned char)(0xD8 | encode)); 1.30 + emit_int8(imm8); 1.31 + } 1.32 +} 1.33 + 1.34 void Assembler::rorq(Register dst, int imm8) { 1.35 assert(isShiftCount(imm8 >> 1), "illegal shift count"); 1.36 int encode = prefixq_and_encode(dst->encoding());