1.1 --- a/src/cpu/sparc/vm/assembler_sparc.hpp Fri Jun 07 11:43:53 2013 -0700
1.2 +++ b/src/cpu/sparc/vm/assembler_sparc.hpp Fri Jun 07 16:46:37 2013 -0700
1.3 @@ -57,7 +57,6 @@
1.4 fbp_op2 = 5,
1.5 br_op2 = 2,
1.6 bp_op2 = 1,
1.7 - cb_op2 = 7, // V8
1.8 sethi_op2 = 4
1.9 };
1.10
1.11 @@ -145,7 +144,6 @@
1.12 ldsh_op3 = 0x0a,
1.13 ldx_op3 = 0x0b,
1.14
1.15 - ldstub_op3 = 0x0d,
1.16 stx_op3 = 0x0e,
1.17 swap_op3 = 0x0f,
1.18
1.19 @@ -163,15 +161,6 @@
1.20
1.21 prefetch_op3 = 0x2d,
1.22
1.23 -
1.24 - ldc_op3 = 0x30,
1.25 - ldcsr_op3 = 0x31,
1.26 - lddc_op3 = 0x33,
1.27 - stc_op3 = 0x34,
1.28 - stcsr_op3 = 0x35,
1.29 - stdcq_op3 = 0x36,
1.30 - stdc_op3 = 0x37,
1.31 -
1.32 casa_op3 = 0x3c,
1.33 casxa_op3 = 0x3e,
1.34
1.35 @@ -574,17 +563,11 @@
1.36 static void vis3_only() { assert( VM_Version::has_vis3(), "This instruction only works on SPARC with VIS3"); }
1.37
1.38 // instruction only in v9
1.39 - static void v9_only() { assert( VM_Version::v9_instructions_work(), "This instruction only works on SPARC V9"); }
1.40 -
1.41 - // instruction only in v8
1.42 - static void v8_only() { assert( VM_Version::v8_instructions_work(), "This instruction only works on SPARC V8"); }
1.43 + static void v9_only() { } // do nothing
1.44
1.45 // instruction deprecated in v9
1.46 static void v9_dep() { } // do nothing for now
1.47
1.48 - // some float instructions only exist for single prec. on v8
1.49 - static void v8_s_only(FloatRegisterImpl::Width w) { if (w != FloatRegisterImpl::S) v9_only(); }
1.50 -
1.51 // v8 has no CC field
1.52 static void v8_no_cc(CC cc) { if (cc) v9_only(); }
1.53
1.54 @@ -730,11 +713,6 @@
1.55 inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1.56 inline void bp( Condition c, bool a, CC cc, Predict p, Label& L );
1.57
1.58 - // pp 121 (V8)
1.59 -
1.60 - inline void cb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
1.61 - inline void cb( Condition c, bool a, Label& L );
1.62 -
1.63 // pp 149
1.64
1.65 inline void call( address d, relocInfo::relocType rt = relocInfo::runtime_call_type );
1.66 @@ -775,8 +753,8 @@
1.67
1.68 // pp 157
1.69
1.70 - void fcmp( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { v8_no_cc(cc); emit_int32( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x50 + w) | fs2(s2, w)); }
1.71 - void fcmpe( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { v8_no_cc(cc); emit_int32( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x54 + w) | fs2(s2, w)); }
1.72 + void fcmp( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { emit_int32( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x50 + w) | fs2(s2, w)); }
1.73 + void fcmpe( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { emit_int32( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x54 + w) | fs2(s2, w)); }
1.74
1.75 // pp 159
1.76
1.77 @@ -794,21 +772,11 @@
1.78
1.79 // pp 162
1.80
1.81 - void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w); emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x00 + w) | fs2(s, w)); }
1.82 + void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x00 + w) | fs2(s, w)); }
1.83
1.84 - void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w); emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(s, w)); }
1.85 + void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(s, w)); }
1.86
1.87 - // page 144 sparc v8 architecture (double prec works on v8 if the source and destination registers are the same). fnegs is the only instruction available
1.88 - // on v8 to do negation of single, double and quad precision floats.
1.89 -
1.90 - void fneg( FloatRegisterImpl::Width w, FloatRegister sd ) { if (VM_Version::v9_instructions_work()) emit_int32( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(sd, w)); else emit_int32( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x05) | fs2(sd, w)); }
1.91 -
1.92 - void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w); emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(s, w)); }
1.93 -
1.94 - // page 144 sparc v8 architecture (double prec works on v8 if the source and destination registers are the same). fabss is the only instruction available
1.95 - // on v8 to do abs operation on single/double/quad precision floats.
1.96 -
1.97 - void fabs( FloatRegisterImpl::Width w, FloatRegister sd ) { if (VM_Version::v9_instructions_work()) emit_int32( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(sd, w)); else emit_int32( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x09) | fs2(sd, w)); }
1.98 + void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(s, w)); }
1.99
1.100 // pp 163
1.101
1.102 @@ -839,11 +807,6 @@
1.103 void impdep1( int id1, int const19a ) { v9_only(); emit_int32( op(arith_op) | fcn(id1) | op3(impdep1_op3) | u_field(const19a, 18, 0)); }
1.104 void impdep2( int id1, int const19a ) { v9_only(); emit_int32( op(arith_op) | fcn(id1) | op3(impdep2_op3) | u_field(const19a, 18, 0)); }
1.105
1.106 - // pp 149 (v8)
1.107 -
1.108 - void cpop1( int opc, int cr1, int cr2, int crd ) { v8_only(); emit_int32( op(arith_op) | fcn(crd) | op3(impdep1_op3) | u_field(cr1, 18, 14) | opf(opc) | u_field(cr2, 4, 0)); }
1.109 - void cpop2( int opc, int cr1, int cr2, int crd ) { v8_only(); emit_int32( op(arith_op) | fcn(crd) | op3(impdep2_op3) | u_field(cr1, 18, 14) | opf(opc) | u_field(cr2, 4, 0)); }
1.110 -
1.111 // pp 170
1.112
1.113 void jmpl( Register s1, Register s2, Register d );
1.114 @@ -860,16 +823,6 @@
1.115 inline void ldxfsr( Register s1, Register s2 );
1.116 inline void ldxfsr( Register s1, int simm13a);
1.117
1.118 - // pp 94 (v8)
1.119 -
1.120 - inline void ldc( Register s1, Register s2, int crd );
1.121 - inline void ldc( Register s1, int simm13a, int crd);
1.122 - inline void lddc( Register s1, Register s2, int crd );
1.123 - inline void lddc( Register s1, int simm13a, int crd);
1.124 - inline void ldcsr( Register s1, Register s2, int crd );
1.125 - inline void ldcsr( Register s1, int simm13a, int crd);
1.126 -
1.127 -
1.128 // 173
1.129
1.130 void ldfa( FloatRegisterImpl::Width w, Register s1, Register s2, int ia, FloatRegister d ) { v9_only(); emit_int32( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1.131 @@ -910,18 +863,6 @@
1.132 void lduwa( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1.133 void ldxa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1.134 void ldxa( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1.135 - void ldda( Register s1, Register s2, int ia, Register d ) { v9_dep(); emit_int32( op(ldst_op) | rd(d) | op3(ldd_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1.136 - void ldda( Register s1, int simm13a, Register d ) { v9_dep(); emit_int32( op(ldst_op) | rd(d) | op3(ldd_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1.137 -
1.138 - // pp 179
1.139 -
1.140 - inline void ldstub( Register s1, Register s2, Register d );
1.141 - inline void ldstub( Register s1, int simm13a, Register d);
1.142 -
1.143 - // pp 180
1.144 -
1.145 - void ldstuba( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldstub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1.146 - void ldstuba( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldstub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1.147
1.148 // pp 181
1.149
1.150 @@ -992,11 +933,6 @@
1.151 void smulcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1.152 void smulcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1.153
1.154 - // pp 199
1.155 -
1.156 - void mulscc( Register s1, Register s2, Register d ) { v9_dep(); emit_int32( op(arith_op) | rd(d) | op3(mulscc_op3) | rs1(s1) | rs2(s2) ); }
1.157 - void mulscc( Register s1, int simm13a, Register d ) { v9_dep(); emit_int32( op(arith_op) | rd(d) | op3(mulscc_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1.158 -
1.159 // pp 201
1.160
1.161 void nop() { emit_int32( op(branch_op) | op2(sethi_op2) ); }
1.162 @@ -1116,17 +1052,6 @@
1.163 void stda( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1.164 void stda( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1.165
1.166 - // pp 97 (v8)
1.167 -
1.168 - inline void stc( int crd, Register s1, Register s2 );
1.169 - inline void stc( int crd, Register s1, int simm13a);
1.170 - inline void stdc( int crd, Register s1, Register s2 );
1.171 - inline void stdc( int crd, Register s1, int simm13a);
1.172 - inline void stcsr( int crd, Register s1, Register s2 );
1.173 - inline void stcsr( int crd, Register s1, int simm13a);
1.174 - inline void stdcq( int crd, Register s1, Register s2 );
1.175 - inline void stdcq( int crd, Register s1, int simm13a);
1.176 -
1.177 // pp 230
1.178
1.179 void sub( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | rs2(s2) ); }
1.180 @@ -1153,20 +1078,16 @@
1.181
1.182 void taddcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(taddcc_op3 ) | rs1(s1) | rs2(s2) ); }
1.183 void taddcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(taddcc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1.184 - void taddcctv( Register s1, Register s2, Register d ) { v9_dep(); emit_int32( op(arith_op) | rd(d) | op3(taddcctv_op3) | rs1(s1) | rs2(s2) ); }
1.185 - void taddcctv( Register s1, int simm13a, Register d ) { v9_dep(); emit_int32( op(arith_op) | rd(d) | op3(taddcctv_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1.186
1.187 // pp 235
1.188
1.189 void tsubcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(tsubcc_op3 ) | rs1(s1) | rs2(s2) ); }
1.190 void tsubcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(tsubcc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1.191 - void tsubcctv( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(tsubcctv_op3) | rs1(s1) | rs2(s2) ); }
1.192 - void tsubcctv( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(tsubcctv_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1.193
1.194 // pp 237
1.195
1.196 - void trap( Condition c, CC cc, Register s1, Register s2 ) { v8_no_cc(cc); emit_int32( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | rs2(s2)); }
1.197 - void trap( Condition c, CC cc, Register s1, int trapa ) { v8_no_cc(cc); emit_int32( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | immed(true) | u_field(trapa, 6, 0)); }
1.198 + void trap( Condition c, CC cc, Register s1, Register s2 ) { emit_int32( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | rs2(s2)); }
1.199 + void trap( Condition c, CC cc, Register s1, int trapa ) { emit_int32( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | immed(true) | u_field(trapa, 6, 0)); }
1.200 // simple uncond. trap
1.201 void trap( int trapa ) { trap( always, icc, G0, trapa ); }
1.202
